diff --git a/arch/mips/include/asm/mach-ip27/pcibr.h b/arch/mips/include/asm/mach-ip27/pcibr.h
new file mode 100644
index 0000000..80ef8e3
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/pcibr.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Definitions for the built-in PCI bridge
+ * Copyright (C) 2004-2007 Stanislaw Skowronek
+ */
+#ifndef __ASM_MACH_IP27_PCIBR_H
+#define __ASM_MACH_IP27_PCIBR_H
+
+#include <asm/pci/bridge.h>
+#include <asm/mach-ip27/irq.h>
+
+/* Xtalk */
+#define PCIBR_OFFSET_MEM	0x200000
+#define PCIBR_OFFSET_IO		0xa00000
+#define PCIBR_OFFSET_END	0xc00000
+
+#endif /* __ASM_MACH_IP27_PCIBR_H */
+
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 0f09eaf..d1531ba 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -17,6 +17,8 @@
 #include <asm/sn/intr.h>
 #include <asm/sn/sn0/hub.h>
 
+#include <asm/mach-ip27/pcibr.h>
+
 /*
  * Max #PCI busses we can handle; ie, max #PCI bridges.
  */
@@ -41,11 +43,13 @@ int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
 
 extern struct pci_ops bridge_pci_ops;
 
+/* Increments for each additional bridge. */
+static int num_bridges = 0;
+
 int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
 {
 	unsigned long offset = NODE_OFFSET(nasid);
 	struct bridge_controller *bc;
-	static int num_bridges = 0;
 	bridge_t *bridge;
 	int slot;
 
@@ -59,23 +63,31 @@ int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
 
 	bc = &bridges[num_bridges];
 
-	bc->pc.pci_ops		= &bridge_pci_ops;
-	bc->pc.mem_resource	= &bc->mem;
-	bc->pc.io_resource	= &bc->io;
-
-	bc->pc.index		= num_bridges;
-
-	bc->mem.name		= "Bridge PCI MEM";
-	bc->pc.mem_offset	= offset;
-	bc->mem.start		= 0;
-	bc->mem.end		= ~0UL;
-	bc->mem.flags		= IORESOURCE_MEM;
-
-	bc->io.name		= "Bridge IO MEM";
-	bc->pc.io_offset	= offset;
-	bc->io.start		= 0UL;
-	bc->io.end		= ~0UL;
-	bc->io.flags		= IORESOURCE_IO;
+	bc->pc.pci_ops = &bridge_pci_ops;
+	bc->pc.mem_resource = &bc->mem;
+	bc->pc.io_resource = &bc->io;
+	bc->pc.busn_resource = &bc->busn;
+	bc->pc.io_map_base = NODE_SWIN_BASE(nasid, widget_id);
+
+	bc->pc.index = num_bridges;
+
+	bc->mem.name = "Bridge PCI MEM";
+	bc->pc.mem_offset = offset;
+	bc->mem.start = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_MEM);
+	bc->mem.end = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_IO - 1);
+	bc->mem.flags = IORESOURCE_MEM;
+
+	bc->io.name = "Bridge IO MEM";
+	bc->pc.io_offset = offset;
+	bc->io.start = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_IO);
+	bc->io.end = (NODE_SWIN_BASE(nasid, widget_id) + PCIBR_OFFSET_END - 1);
+	bc->io.flags = IORESOURCE_IO;
+
+	bc->busn.name = "Bridge BUSN";
+	bc->pc.busn_offset = offset;
+	bc->busn.start = num_bridges;
+	bc->busn.end = 255;
+	bc->busn.flags = IORESOURCE_BUS;
 
 	bc->irq_cpu = smp_processor_id();
 	bc->widget_id = widget_id;