diff -Naurp linux.orig/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c
--- linux.orig/arch/mips/kernel/cpu-probe.c	2005-10-05 21:19:35.000000000 -0400
+++ linux/arch/mips/kernel/cpu-probe.c	2005-10-12 12:10:10.000000000 -0400
@@ -438,6 +438,15 @@ static inline void cpu_probe_legacy(stru
 		             MIPS_CPU_LLSC;
 		c->tlbsize = 64;
 		break;
+	case PRID_IMP_R14000:
+		c->cputype = CPU_R14000;
+		c->isa_level = MIPS_CPU_ISA_IV;
+		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
+			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
+		             MIPS_CPU_LLSC;
+		c->tlbsize = 64;
+		break;
 	}
 }
 
diff -Naurp linux.orig/arch/mips/kernel/proc.c linux/arch/mips/kernel/proc.c
--- linux.orig/arch/mips/kernel/proc.c	2005-09-29 15:44:42.000000000 -0400
+++ linux/arch/mips/kernel/proc.c	2005-10-12 12:09:36.000000000 -0400
@@ -42,6 +42,7 @@ static const char *cpu_name[] = {
 	[CPU_R8000]	= "R8000",
 	[CPU_R10000]	= "R10000",
 	[CPU_R12000]	= "R12000",
+	[CPU_R14000]	= "R14000",
 	[CPU_R4300]	= "R4300",
 	[CPU_R4650]	= "R4650",
 	[CPU_R4700]	= "R4700",
diff -Naurp linux.orig/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c
--- linux.orig/arch/mips/mm/c-r4k.c	2005-10-03 20:18:14.000000000 -0400
+++ linux/arch/mips/mm/c-r4k.c	2005-10-12 12:09:16.000000000 -0400
@@ -307,6 +307,7 @@ static inline void local_r4k___flush_cac
 	case CPU_R4400MC:
 	case CPU_R10000:
 	case CPU_R12000:
+	case CPU_R14000:
 		r4k_blast_scache();
 	}
 }
@@ -876,6 +877,7 @@ static void __init probe_pcache(void)
 
 	case CPU_R10000:
 	case CPU_R12000:
+	case CPU_R14000:
 		icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 		c->icache.linesz = 64;
 		c->icache.ways = 2;
@@ -1028,6 +1030,7 @@ static void __init probe_pcache(void)
 	case CPU_25KF:
 	case CPU_R10000:
 	case CPU_R12000:
+	case CPU_R14000:
 	case CPU_SB1:
 		break;
 	case CPU_24K:
@@ -1154,6 +1157,7 @@ static void __init setup_scache(void)
 
 	case CPU_R10000:
 	case CPU_R12000:
+	case CPU_R14000:
 		scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
 		c->scache.linesz = 64 << ((config >> 13) & 1);
 		c->scache.ways = 2;
diff -Naurp linux.orig/arch/mips/mm/pg-r4k.c linux/arch/mips/mm/pg-r4k.c
--- linux.orig/arch/mips/mm/pg-r4k.c	2005-09-29 15:44:42.000000000 -0400
+++ linux/arch/mips/mm/pg-r4k.c	2005-10-12 12:08:36.000000000 -0400
@@ -351,6 +351,7 @@ void __init build_clear_page(void)
 
 		case CPU_R10000:
 		case CPU_R12000:
+		case CPU_R14000:
 			pref_src_mode = Pref_LoadStreamed;
 			pref_dst_mode = Pref_StoreStreamed;
 			break;
diff -Naurp linux.orig/arch/mips/mm/tlbex.c linux/arch/mips/mm/tlbex.c
--- linux.orig/arch/mips/mm/tlbex.c	2005-10-05 21:19:35.000000000 -0400
+++ linux/arch/mips/mm/tlbex.c	2005-10-12 12:08:03.000000000 -0400
@@ -852,6 +852,7 @@ static __init void build_tlb_write_entry
 
 	case CPU_R10000:
 	case CPU_R12000:
+	case CPU_R14000:
 	case CPU_4KC:
 	case CPU_SB1:
 	case CPU_4KSC:
diff -Naurp linux.orig/include/asm-mips/cpu.h linux/include/asm-mips/cpu.h
--- linux.orig/include/asm-mips/cpu.h	2005-10-03 20:18:14.000000000 -0400
+++ linux/include/asm-mips/cpu.h	2005-10-12 12:10:55.000000000 -0400
@@ -51,6 +51,7 @@
 #define PRID_IMP_R4300		0x0b00
 #define PRID_IMP_VR41XX		0x0c00
 #define PRID_IMP_R12000		0x0e00
+#define PRID_IMP_R14000		0x0f00
 #define PRID_IMP_R8000		0x1000
 #define PRID_IMP_PR4450		0x1200
 #define PRID_IMP_R4600		0x2000
@@ -194,7 +195,8 @@
 #define CPU_AU1200		59
 #define CPU_34K			60
 #define CPU_PR4450		61
-#define CPU_LAST		61
+#define CPU_R14000		62
+#define CPU_LAST		62
 
 /*
  * ISA Level encodings