diff -Naurp linux-2.6.12.5.orig/arch/mips/mm/c-r4k.c linux-2.6.12.5/arch/mips/mm/c-r4k.c --- linux-2.6.12.5.orig/arch/mips/mm/c-r4k.c 2005-10-15 20:03:48.000000000 -0400 +++ linux-2.6.12.5/arch/mips/mm/c-r4k.c 2005-10-15 20:04:15.000000000 -0400 @@ -1175,6 +1175,12 @@ static inline void coherency_setup(void) } } +/* + * This variable indicates if we prepared boot cpu caches yet or not. + * Secondary CPUs don't need to change any global data/memory + */ +static __initdata int boot_cpu_ready=0; + void __init ld_mmu_r4xx0(void) { extern void build_clear_page(void); @@ -1184,50 +1190,56 @@ void __init ld_mmu_r4xx0(void) /* Default cache error handler for R4000 and R5000 family */ memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80); - memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80); + + /* This only needs to happen once. One above can be done locally to fill in the local cache? */ + if(boot_cpu_ready == 0){ + memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80); + } probe_pcache(); setup_scache(); - r4k_blast_dcache_page_setup(); - r4k_blast_dcache_page_indexed_setup(); - r4k_blast_dcache_setup(); - r4k_blast_icache_page_setup(); - r4k_blast_icache_page_indexed_setup(); - r4k_blast_icache_setup(); - r4k_blast_scache_page_setup(); - r4k_blast_scache_setup(); - - /* - * Some MIPS32 and MIPS64 processors have physically indexed caches. - * This code supports virtually indexed processors and will be - * unnecessarily inefficient on physically indexed processors. - */ - shm_align_mask = max_t( unsigned long, - c->dcache.sets * c->dcache.linesz - 1, - PAGE_SIZE - 1); - - flush_cache_all = r4k_flush_cache_all; - __flush_cache_all = r4k___flush_cache_all; - flush_cache_mm = r4k_flush_cache_mm; - flush_cache_page = r4k_flush_cache_page; - flush_icache_page = r4k_flush_icache_page; - flush_cache_range = r4k_flush_cache_range; - - flush_cache_sigtramp = r4k_flush_cache_sigtramp; - flush_icache_all = r4k_flush_icache_all; - flush_data_cache_page = r4k_flush_data_cache_page; - flush_icache_range = r4k_flush_icache_range; + if(boot_cpu_ready == 0) { + r4k_blast_dcache_page_setup(); + r4k_blast_dcache_page_indexed_setup(); + r4k_blast_dcache_setup(); + r4k_blast_icache_page_setup(); + r4k_blast_icache_page_indexed_setup(); + r4k_blast_icache_setup(); + r4k_blast_scache_page_setup(); + r4k_blast_scache_setup(); + + /* + * Some MIPS32 and MIPS64 processors have physically indexed caches. + * This code supports virtually indexed processors and will be + * unnecessarily inefficient on physically indexed processors. + */ + shm_align_mask = max_t( unsigned long, + c->dcache.sets * c->dcache.linesz - 1, + PAGE_SIZE - 1); + + flush_cache_all = r4k_flush_cache_all; + __flush_cache_all = r4k___flush_cache_all; + flush_cache_mm = r4k_flush_cache_mm; + flush_cache_page = r4k_flush_cache_page; + flush_icache_page = r4k_flush_icache_page; + flush_cache_range = r4k_flush_cache_range; + + flush_cache_sigtramp = r4k_flush_cache_sigtramp; + flush_icache_all = r4k_flush_icache_all; + flush_data_cache_page = r4k_flush_data_cache_page; + flush_icache_range = r4k_flush_icache_range; #ifdef CONFIG_DMA_NONCOHERENT - _dma_cache_wback_inv = r4k_dma_cache_wback_inv; - _dma_cache_wback = r4k_dma_cache_wback_inv; - _dma_cache_inv = r4k_dma_cache_inv; + _dma_cache_wback_inv = r4k_dma_cache_wback_inv; + _dma_cache_wback = r4k_dma_cache_wback_inv; + _dma_cache_inv = r4k_dma_cache_inv; #endif - __flush_cache_all(); + build_clear_page(); + build_copy_page(); + boot_cpu_ready++; + } + local_r4k___flush_cache_all(NULL); coherency_setup(); - - build_clear_page(); - build_copy_page(); } diff -Naurp linux-2.6.12.5.orig/arch/mips/mm/pg-r4k.c linux-2.6.12.5/arch/mips/mm/pg-r4k.c --- linux-2.6.12.5.orig/arch/mips/mm/pg-r4k.c 2005-10-15 20:03:48.000000000 -0400 +++ linux-2.6.12.5/arch/mips/mm/pg-r4k.c 2005-10-15 20:03:59.000000000 -0400 @@ -404,9 +404,6 @@ dest = label(); build_jr_ra(); - flush_icache_range((unsigned long)&clear_page_array, - (unsigned long) epc); - BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); } @@ -482,8 +479,5 @@ dest = label(); build_jr_ra(); - flush_icache_range((unsigned long)©_page_array, - (unsigned long) epc); - BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); } diff -Naurp linux-2.6.12.5.orig/arch/mips/mm/tlbex.c linux-2.6.12.5/arch/mips/mm/tlbex.c --- linux-2.6.12.5.orig/arch/mips/mm/tlbex.c 2005-10-15 20:03:48.000000000 -0400 +++ linux-2.6.12.5/arch/mips/mm/tlbex.c 2005-10-15 20:03:59.000000000 -0400 @@ -743,7 +743,6 @@ static void __init build_r3000_tlb_refil #endif memcpy((void *)CAC_BASE, tlb_handler, 0x80); - flush_icache_range(CAC_BASE, CAC_BASE + 0x80); } /* @@ -1256,7 +1255,6 @@ static void __init build_r4000_tlb_refil #endif memcpy((void *)CAC_BASE, final_handler, 0x100); - flush_icache_range(CAC_BASE, CAC_BASE + 0x100); } /* @@ -1517,9 +1515,6 @@ static void __init build_r3000_tlb_load_ printk("%08x\n", handle_tlbl[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbl, - (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r3000_tlb_store_handler(void) @@ -1557,9 +1552,6 @@ static void __init build_r3000_tlb_store printk("%08x\n", handle_tlbs[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbs, - (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r3000_tlb_modify_handler(void) @@ -1597,9 +1589,6 @@ static void __init build_r3000_tlb_modif printk("%08x\n", handle_tlbm[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbm, - (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32)); } /* @@ -1689,9 +1678,6 @@ static void __init build_r4000_tlb_load_ printk("%08x\n", handle_tlbl[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbl, - (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r4000_tlb_store_handler(void) @@ -1728,9 +1714,6 @@ static void __init build_r4000_tlb_store printk("%08x\n", handle_tlbs[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbs, - (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32)); } static void __init build_r4000_tlb_modify_handler(void) @@ -1768,9 +1751,6 @@ static void __init build_r4000_tlb_modif printk("%08x\n", handle_tlbm[i]); } #endif - - flush_icache_range((unsigned long)handle_tlbm, - (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32)); } void __init build_tlb_refill_handler(void)