diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/Makefile.am binutils/bfd/Makefile.am --- binutils-2.16.1/bfd/Makefile.am 2005-06-12 20:58:52.000000000 +0200 +++ binutils/bfd/Makefile.am 2006-03-30 01:23:21.000000000 +0200 @@ -58,6 +58,7 @@ cpu-arc.lo \ cpu-arm.lo \ cpu-avr.lo \ + cpu-spu.lo \ cpu-cr16c.lo \ cpu-cris.lo \ cpu-crx.lo \ @@ -116,6 +117,7 @@ cpu-arc.c \ cpu-arm.c \ cpu-avr.c \ + cpu-spu.c \ cpu-cris.c \ cpu-cr16c.c \ cpu-crx.c \ @@ -262,6 +264,7 @@ elf32-sh64.lo \ elf32-sh64-com.lo \ elf32-sparc.lo \ + elf32-spu.lo \ elf32-v850.lo \ elf32-vax.lo \ elf32-xstormy16.lo \ @@ -430,6 +433,7 @@ elf32-sh.c \ elf32-sh-symbian.c \ elf32-sparc.c \ + elf32-spu.c \ elf32-v850.c \ elf32-vax.c \ elf32-xstormy16.c \ @@ -944,6 +948,7 @@ cpu-arc.lo: cpu-arc.c $(INCDIR)/filenames.h cpu-arm.lo: cpu-arm.c $(INCDIR)/filenames.h $(INCDIR)/libiberty.h cpu-avr.lo: cpu-avr.c $(INCDIR)/filenames.h +cpu-spu.lo: cpu-spu.c $(INCDIR)/filenames.h cpu-cris.lo: cpu-cris.c $(INCDIR)/filenames.h cpu-cr16c.lo: cpu-cr16c.c $(INCDIR)/filenames.h cpu-crx.lo: cpu-crx.c $(INCDIR)/filenames.h @@ -1336,6 +1341,10 @@ $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sparc.h \ $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/sparc.h \ elf32-target.h +elf32-spu.lo: elf32-spu.c $(INCDIR)/filenames.h elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/spu.h $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elf32-v850.lo: elf32-v850.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \ elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \ diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/archures.c binutils/bfd/archures.c --- binutils-2.16.1/bfd/archures.c 2005-01-17 15:08:03.000000000 +0100 +++ binutils/bfd/archures.c 2006-03-30 01:23:21.000000000 +0200 @@ -204,11 +204,14 @@ .#define bfd_mach_ppc_rs64iii 643 .#define bfd_mach_ppc_7400 7400 .#define bfd_mach_ppc_e500 500 +.#define bfd_mach_cell_ppu 501 . bfd_arch_rs6000, {* IBM RS/6000 *} .#define bfd_mach_rs6k 6000 .#define bfd_mach_rs6k_rs1 6001 .#define bfd_mach_rs6k_rsc 6003 .#define bfd_mach_rs6k_rs2 6002 +. bfd_arch_spu, {* PowerPC SPU *} +.#define bfd_mach_spu 256 . bfd_arch_hppa, {* HP PA RISC *} .#define bfd_mach_hppa10 10 .#define bfd_mach_hppa11 11 @@ -442,6 +445,7 @@ extern const bfd_arch_info_type bfd_s390_arch; extern const bfd_arch_info_type bfd_sh_arch; extern const bfd_arch_info_type bfd_sparc_arch; +extern const bfd_arch_info_type bfd_spu_arch; extern const bfd_arch_info_type bfd_tic30_arch; extern const bfd_arch_info_type bfd_tic4x_arch; extern const bfd_arch_info_type bfd_tic54x_arch; @@ -503,6 +507,7 @@ &bfd_s390_arch, &bfd_sh_arch, &bfd_sparc_arch, + &bfd_spu_arch, &bfd_tic30_arch, &bfd_tic4x_arch, &bfd_tic54x_arch, diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/bfd-in2.h binutils/bfd/bfd-in2.h --- binutils-2.16.1/bfd/bfd-in2.h 2005-03-02 22:23:20.000000000 +0100 +++ binutils/bfd/bfd-in2.h 2006-03-30 01:23:21.000000000 +0200 @@ -921,6 +921,8 @@ bfd_boolean bfd_fill_in_gnu_debuglink_section (bfd *abfd, struct bfd_section *sect, const char *filename); +void bfd_set_direction(bfd *abfd, int fdflags); + /* Extracted from libbfd.c. */ /* Byte swapping macros for user section data. */ @@ -1649,11 +1651,15 @@ #define bfd_mach_ppc_rs64iii 643 #define bfd_mach_ppc_7400 7400 #define bfd_mach_ppc_e500 500 +#define bfd_mach_cell_ppu 501 +#define bfd_mach_cell_ppu_mambo 502 bfd_arch_rs6000, /* IBM RS/6000 */ #define bfd_mach_rs6k 6000 #define bfd_mach_rs6k_rs1 6001 #define bfd_mach_rs6k_rsc 6003 #define bfd_mach_rs6k_rs2 6002 + bfd_arch_spu, /* PowerPC SPU */ +#define bfd_mach_spu 256 bfd_arch_hppa, /* HP PA RISC */ #define bfd_mach_hppa10 10 #define bfd_mach_hppa11 11 @@ -3638,6 +3644,20 @@ BFD_RELOC_860_HIGOT, BFD_RELOC_860_HIGOTOFF, +/* SPU Relocations. */ + BFD_RELOC_SPU_IMM7, + BFD_RELOC_SPU_IMM8, + BFD_RELOC_SPU_IMM10, + BFD_RELOC_SPU_IMM10W, + BFD_RELOC_SPU_IMM16, + BFD_RELOC_SPU_IMM16W, + BFD_RELOC_SPU_IMM18, + BFD_RELOC_SPU_PCREL9a, + BFD_RELOC_SPU_PCREL9b, + BFD_RELOC_SPU_PCREL16, + BFD_RELOC_SPU_LO16, + BFD_RELOC_SPU_HI16, + /* OpenRISC Relocations. */ BFD_RELOC_OPENRISC_ABS_26, BFD_RELOC_OPENRISC_REL_26, diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/coffcode.h binutils/bfd/coffcode.h --- binutils-2.16.1/bfd/coffcode.h 2005-02-24 21:16:55.000000000 +0100 +++ binutils/bfd/coffcode.h 2006-03-30 01:23:21.000000000 +0200 @@ -303,6 +303,7 @@ #ifdef COFF_WITH_PE #include "peicode.h" +#include "libiberty.h" #else #include "coffswap.h" #endif @@ -3415,6 +3416,12 @@ unsigned int computed; unsigned int checksum = 0; + /* If output to 'nul.*', just pretend we've succeeded. */ +#ifdef HAVE_DOS_BASED_FILE_SYSTEM + if (strncasecmp ("nul.",lbasename(abfd->filename),4) == 0) + return TRUE; +#endif + if (bfd_seek (abfd, 0x3c, SEEK_SET) != 0) return FALSE; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/config.bfd binutils/bfd/config.bfd --- binutils-2.16.1/bfd/config.bfd 2005-01-31 18:18:47.000000000 +0100 +++ binutils/bfd/config.bfd 2006-03-30 01:23:21.000000000 +0200 @@ -77,10 +77,12 @@ pdp11*) targ_archs=bfd_pdp11_arch ;; pj*) targ_archs="bfd_pj_arch bfd_i386_arch";; powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; +ppu*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; s390*) targ_archs=bfd_s390_arch ;; sh*) targ_archs=bfd_sh_arch ;; sparc*) targ_archs=bfd_sparc_arch ;; +spu*) targ_archs=bfd_spu_arch ;; strongarm*) targ_archs=bfd_arm_arch ;; thumb*) targ_archs=bfd_arm_arch ;; v850*) targ_archs=bfd_v850_arch ;; @@ -1053,6 +1055,12 @@ targ_selvecs="bfd_powerpcle_pei_vec bfd_powerpc_pei_vec bfd_powerpcle_pe_vec bfd_powerpc_pe_vec" ;; + ppu-*-lv2) + targ_defvec=bfd_elf64_powerpc_vec + targ_selvecs="bfd_elf32_spu_vec" + want64=true + ;; + s390-*-linux*) targ_defvec=bfd_elf32_s390_vec targ64_selvecs=bfd_elf64_s390_vec @@ -1286,6 +1294,16 @@ targ_underscore=yes ;; + spu-*-lv2) + targ_defvec=bfd_elf32_spu_vec + targ_selvecs="bfd_elf64_powerpc_vec" + ;; + + spu-*-elf) + targ_defvec=bfd_elf32_spu_vec + targ_selvecs="bfd_elf32_powerpc_vec bfd_elf64_powerpc_vec" + ;; + #if HAVE_host_aout_vec tahoe-*-*) targ_defvec=host_aout_vec diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/configure binutils/bfd/configure --- binutils-2.16.1/bfd/configure 2005-06-12 20:58:46.000000000 +0200 +++ binutils/bfd/configure 2006-03-30 01:23:21.000000000 +0200 @@ -11612,6 +11612,7 @@ bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_shnbsd_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elf32.lo $elf" ;; + bfd_elf32_spu_vec) tb="$tb elf32-spu.lo elf32.lo $elf" ;; bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_us_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/configure.in binutils/bfd/configure.in --- binutils-2.16.1/bfd/configure.in 2005-06-12 20:58:40.000000000 +0200 +++ binutils/bfd/configure.in 2006-03-30 01:23:21.000000000 +0200 @@ -659,6 +659,7 @@ bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_shnbsd_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elf32.lo $elf" ;; + bfd_elf32_spu_vec) tb="$tb elf32-spu.lo elf32.lo $elf" ;; bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_us_cris_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/cpu-powerpc.c binutils/bfd/cpu-powerpc.c --- binutils-2.16.1/bfd/cpu-powerpc.c 2005-03-03 12:40:58.000000000 +0100 +++ binutils/bfd/cpu-powerpc.c 2006-03-30 01:23:21.000000000 +0200 @@ -295,6 +295,34 @@ FALSE, /* not the default */ powerpc_compatible, bfd_default_scan, - 0 + &bfd_powerpc_archs[15], + }, + { + 64, /* 64 bits in a word */ + 64, /* 64 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_powerpc, + bfd_mach_cell_ppu, + "powerpc", + "Cell:PPU", + 3, + FALSE, + powerpc_compatible, + bfd_default_scan, + &bfd_powerpc_archs[16], + }, + { + 64, /* 64 bits in a word */ + 64, /* 64 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_powerpc, + bfd_mach_cell_ppu_mambo, + "powerpc", + "Cell:Mambo", + 3, + FALSE, + powerpc_compatible, + bfd_default_scan, + 0 /* pointer to next bfd_arch_info_type objenct */ } }; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/cpu-spu.c binutils/bfd/cpu-spu.c --- binutils-2.16.1/bfd/cpu-spu.c 1970-01-01 01:00:00.000000000 +0100 +++ binutils/bfd/cpu-spu.c 2006-03-30 01:23:21.000000000 +0200 @@ -0,0 +1,63 @@ + +/* (C) Copyright + Sony Computer Entertainment, Inc., + Toshiba Corporation, + International Business Machines Corporation, + 2001,2002,2003,2004,2005. + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + + +static const bfd_arch_info_type *spu_compatible + PARAMS ((const bfd_arch_info_type *, const bfd_arch_info_type *)); + +static const bfd_arch_info_type * +spu_compatible (a,b) + const bfd_arch_info_type *a; + const bfd_arch_info_type *b; +{ + BFD_ASSERT (a->arch == bfd_arch_spu); + switch (b->arch) + { + default: + return NULL; + case bfd_arch_spu: + return bfd_default_compatible (a, b); + } + /*NOTREACHED*/ +} + +const bfd_arch_info_type bfd_spu_arch[] = +{ + { + 32, /* 32 bits in a word */ + 32, /* 32 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_spu, /* architecture */ + bfd_mach_spu, /* machine */ + "spu", /* architecture name */ + "spu:256K", /* printable name */ + 3, /* aligned power */ + TRUE, /* the default machine for the architecture */ + spu_compatible, /* the spu is only compatible with itself, see above */ + bfd_default_scan, + 0, /* next -- there are none! */ + } +}; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/doc/bfd.info binutils/bfd/doc/bfd.info --- binutils-2.16.1/bfd/doc/bfd.info 2005-06-12 21:32:58.000000000 +0200 +++ binutils/bfd/doc/bfd.info 2006-03-30 01:23:21.000000000 +0200 @@ -1,5 +1,5 @@ -This is ../.././bfd/doc/bfd.info, produced by makeinfo version 4.7 from -../.././bfd/doc/bfd.texinfo. +This is /vobs/toolchain/binutils/bfd/doc/bfd.info, produced by makeinfo +version 4.5 from /vobs/toolchain/binutils/bfd/doc/bfd.texinfo. START-INFO-DIR-ENTRY * Bfd: (bfd). The Binary File Descriptor library. @@ -18,72 +18,71 @@  Indirect: -bfd.info-1: 724 -bfd.info-2: 298309 +bfd.info-1: 758  Tag Table: (Indirect) -Node: Top724 -Node: Overview1056 -Node: History2107 -Node: How It Works3053 -Node: What BFD Version 2 Can Do4595 -Node: BFD information loss5910 -Node: Canonical format8442 -Node: BFD front end12814 -Node: Memory Usage38041 -Node: Initialization39269 -Node: Sections39665 -Node: Section Input40148 -Node: Section Output41513 -Node: typedef asection43999 -Node: section prototypes61598 -Node: Symbols70581 -Node: Reading Symbols72176 -Node: Writing Symbols73283 -Node: Mini Symbols74992 -Node: typedef asymbol75966 -Node: symbol handling functions80884 -Node: Archives86226 -Node: Formats89903 -Node: Relocations92794 -Node: typedef arelent93521 -Node: howto manager109239 -Node: Core Files165412 -Node: Targets166491 -Node: bfd_target168461 -Node: Architectures187781 -Node: Opening and Closing208078 -Node: Internal217791 -Node: File Caching224063 -Node: Linker Functions227370 -Node: Creating a Linker Hash Table229043 -Node: Adding Symbols to the Hash Table230781 -Node: Differing file formats231681 -Node: Adding symbols from an object file233429 -Node: Adding symbols from an archive235580 -Node: Performing the Final Link237994 -Node: Information provided by the linker239236 -Node: Relocating the section contents240386 -Node: Writing the symbol table242137 -Node: Hash Tables245130 -Node: Creating and Freeing a Hash Table246328 -Node: Looking Up or Entering a String247578 -Node: Traversing a Hash Table248831 -Node: Deriving a New Hash Table Type249620 -Node: Define the Derived Structures250686 -Node: Write the Derived Creation Routine251767 -Node: Write Other Derived Routines254461 -Node: BFD back ends255776 -Node: What to Put Where256046 -Node: aout256184 -Node: coff262435 -Node: elf287111 -Node: mmo287965 -Node: File layout288893 -Node: Symbol-table294540 -Node: mmo section mapping298309 -Node: GNU Free Documentation License301961 -Node: Index321681 +Node: Top758 +Node: Overview1090 +Node: History2140 +Node: How It Works3081 +Node: What BFD Version 2 Can Do4621 +Node: BFD information loss5931 +Node: Canonical format8454 +Node: BFD front end12815 +Node: Memory Usage37874 +Node: Initialization39097 +Node: Sections39475 +Node: Section Input39953 +Node: Section Output41309 +Node: typedef asection43777 +Node: section prototypes61797 +Node: Symbols70519 +Node: Reading Symbols72109 +Node: Writing Symbols73237 +Node: Mini Symbols74957 +Node: typedef asymbol75922 +Node: symbol handling functions80966 +Node: Archives86095 +Node: Formats89728 +Node: Relocations92562 +Node: typedef arelent93282 +Node: howto manager109026 +Node: Core Files164414 +Node: Targets165441 +Node: bfd_target167404 +Node: Architectures186908 +Node: Opening and Closing207039 +Node: Internal216437 +Node: File Caching222684 +Node: Linker Functions225864 +Node: Creating a Linker Hash Table227530 +Node: Adding Symbols to the Hash Table229257 +Node: Differing file formats230147 +Node: Adding symbols from an object file231880 +Node: Adding symbols from an archive234016 +Node: Performing the Final Link236415 +Node: Information provided by the linker237646 +Node: Relocating the section contents238781 +Node: Writing the symbol table240517 +Node: Hash Tables243465 +Node: Creating and Freeing a Hash Table244656 +Node: Looking Up or Entering a String245895 +Node: Traversing a Hash Table247137 +Node: Deriving a New Hash Table Type247915 +Node: Define the Derived Structures248970 +Node: Write the Derived Creation Routine250036 +Node: Write Other Derived Routines252735 +Node: BFD back ends254035 +Node: What to Put Where254301 +Node: aout254439 +Node: coff260576 +Node: elf285497 +Node: mmo286334 +Node: File layout287257 +Node: Symbol-table292895 +Node: mmo section mapping296690 +Node: GNU Free Documentation License300333 +Node: Index320038  End Tag Table diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/doc/bfd.info-1 binutils/bfd/doc/bfd.info-1 --- binutils-2.16.1/bfd/doc/bfd.info-1 2005-06-12 21:32:58.000000000 +0200 +++ binutils/bfd/doc/bfd.info-1 2006-03-30 01:23:21.000000000 +0200 @@ -1,5 +1,5 @@ -This is ../.././bfd/doc/bfd.info, produced by makeinfo version 4.7 from -../.././bfd/doc/bfd.texinfo. +This is /vobs/toolchain/binutils/bfd/doc/bfd.info, produced by makeinfo +version 4.5 from /vobs/toolchain/binutils/bfd/doc/bfd.texinfo. START-INFO-DIR-ENTRY * Bfd: (bfd). The Binary File Descriptor library. @@ -32,13 +32,13 @@  File: bfd.info, Node: Overview, Next: BFD front end, Prev: Top, Up: Top -1 Introduction -************** +Introduction +************ -BFD is a package which allows applications to use the same routines to -operate on object files whatever the object file format. A new object -file format can be supported simply by creating a new BFD back end and -adding it to the library. + BFD is a package which allows applications to use the same routines +to operate on object files whatever the object file format. A new +object file format can be supported simply by creating a new BFD back +end and adding it to the library. BFD is split into two parts: the front end, and the back ends (one for each object file format). @@ -60,11 +60,11 @@  File: bfd.info, Node: History, Next: How It Works, Prev: Overview, Up: Overview -1.1 History -=========== +History +======= -One spur behind BFD was the desire, on the part of the GNU 960 team at -Intel Oregon, for interoperability of applications on their COFF and + One spur behind BFD was the desire, on the part of the GNU 960 team +at Intel Oregon, for interoperability of applications on their COFF and b.out file formats. Cygnus was providing GNU support for the team, and was contracted to provide the required functionality. @@ -84,10 +84,10 @@  File: bfd.info, Node: How It Works, Next: What BFD Version 2 Can Do, Prev: History, Up: Overview -1.2 How To Use BFD -================== +How To Use BFD +============== -To use the library, include `bfd.h' and link with `libbfd.a'. + To use the library, include `bfd.h' and link with `libbfd.a'. BFD provides a common interface to the parts of an object file for a calling application. @@ -106,7 +106,7 @@ `abfd'. #include "bfd.h" - + unsigned int number_of_sections (abfd) bfd *abfd; { @@ -122,21 +122,22 @@ * a set of relocations (*note Relocations::), and * some symbol information (*note Symbols::). - Also, BFDs opened for archives have the additional attribute of an -index and contain subordinate BFDs. This approach is fine for a.out and -coff, but loses efficiency when applied to formats such as S-records and + +Also, BFDs opened for archives have the additional attribute of an index +and contain subordinate BFDs. This approach is fine for a.out and coff, +but loses efficiency when applied to formats such as S-records and IEEE-695.  File: bfd.info, Node: What BFD Version 2 Can Do, Prev: How It Works, Up: Overview -1.3 What BFD Version 2 Can Do -============================= +What BFD Version 2 Can Do +========================= -When an object file is opened, BFD subroutines automatically determine -the format of the input object file. They then build a descriptor in -memory with pointers to routines that will be used to access elements of -the object file's data structures. + When an object file is opened, BFD subroutines automatically +determine the format of the input object file. They then build a +descriptor in memory with pointers to routines that will be used to +access elements of the object file's data structures. As different information from the object files is required, BFD reads from different sections of the file and processes them. For @@ -159,14 +160,14 @@  File: bfd.info, Node: BFD information loss, Next: Canonical format, Up: What BFD Version 2 Can Do -1.3.1 Information Loss ----------------------- +Information Loss +---------------- -_Information can be lost during output._ The output formats supported -by BFD do not provide identical facilities, and information which can -be described in one form has nowhere to go in another format. One -example of this is alignment information in `b.out'. There is nowhere -in an `a.out' format file to store alignment information on the + _Information can be lost during output._ The output formats +supported by BFD do not provide identical facilities, and information +which can be described in one form has nowhere to go in another format. +One example of this is alignment information in `b.out'. There is +nowhere in an `a.out' format file to store alignment information on the contained data, so when a file is linked from `b.out' and an `a.out' image is produced, alignment information will not propagate to the output file. (The linker will still use the alignment information @@ -205,15 +206,15 @@  File: bfd.info, Node: Canonical format, Prev: BFD information loss, Up: What BFD Version 2 Can Do -1.3.2 The BFD canonical object-file format ------------------------------------------- +The BFD canonical object-file format +------------------------------------ -The greatest potential for loss of information occurs when there is the -least overlap between the information provided by the source format, -that stored by the canonical format, and that needed by the destination -format. A brief description of the canonical form may help you -understand which kinds of data you can count on preserving across -conversions. + The greatest potential for loss of information occurs when there is +the least overlap between the information provided by the source +format, that stored by the canonical format, and that needed by the +destination format. A brief description of the canonical form may help +you understand which kinds of data you can count on preserving across +conversions. _files_ Information stored on a per-file basis includes target machine @@ -287,15 +288,15 @@  File: bfd.info, Node: BFD front end, Next: BFD back ends, Prev: Overview, Up: Top -2 BFD Front End -*************** +BFD Front End +************* -2.1 `typedef bfd' -================= +`typedef bfd' +============= -A BFD has type `bfd'; objects of this type are the cornerstone of any -application using BFD. Using BFD consists of making references though -the BFD and to data in the BFD. + A BFD has type `bfd'; objects of this type are the cornerstone of +any application using BFD. Using BFD consists of making references +though the BFD and to data in the BFD. Here is the structure that defines the type `bfd'. It contains the major data about the file and pointers to the rest of the data. @@ -305,51 +306,51 @@ { /* A unique identifier of the BFD */ unsigned int id; - + /* The filename the application opened the BFD with. */ const char *filename; - + /* A pointer to the target jump table. */ const struct bfd_target *xvec; - + /* The IOSTREAM, and corresponding IO vector that provide access to the file backing the BFD. */ void *iostream; const struct bfd_iovec *iovec; - + /* Is the file descriptor being cached? That is, can it be closed as needed, and re-opened when accessed later? */ bfd_boolean cacheable; - + /* Marks whether there was a default target specified when the BFD was opened. This is used to select which matching algorithm to use to choose the back end. */ bfd_boolean target_defaulted; - + /* The caching routines use these to maintain a least-recently-used list of BFDs. */ struct bfd *lru_prev, *lru_next; - + /* When a file is closed by the caching routines, BFD retains state information on the file here... */ ufile_ptr where; - + /* ... and here: (``once'' means at least once). */ bfd_boolean opened_once; - + /* Set if we have a locally maintained mtime value, rather than getting it from the file each time. */ bfd_boolean mtime_set; - + /* File modified time, if mtime_set is TRUE. */ long mtime; - + /* Reserved for an unimplemented file locking extension. */ int ifd; - + /* The format which belongs to the BFD. (object, core, etc.) */ bfd_format format; - + /* The direction with which the BFD was opened. */ enum bfd_direction { @@ -359,64 +360,64 @@ both_direction = 3 } direction; - + /* Format_specific flags. */ flagword flags; - + /* Currently my_archive is tested before adding origin to anything. I believe that this can become always an add of origin, with origin set to 0 for non archive files. */ ufile_ptr origin; - + /* Remember when output has begun, to stop strange things from happening. */ bfd_boolean output_has_begun; - + /* A hash table for section names. */ struct bfd_hash_table section_htab; - + /* Pointer to linked list of sections. */ struct bfd_section *sections; - + /* The place where we add to the section list. */ struct bfd_section **section_tail; - + /* The number of sections. */ unsigned int section_count; - + /* Stuff only useful for object files: The start address. */ bfd_vma start_address; - + /* Used for input and output. */ unsigned int symcount; - + /* Symbol table for output BFD (with symcount entries). */ struct bfd_symbol **outsymbols; - + /* Used for slurped dynamic symbol tables. */ unsigned int dynsymcount; - + /* Pointer to structure which contains architecture information. */ const struct bfd_arch_info *arch_info; - + /* Flag set if symbols from this BFD should not be exported. */ bfd_boolean no_export; - + /* Stuff only useful for archives. */ void *arelt_data; struct bfd *my_archive; /* The containing archive BFD. */ struct bfd *next; /* The next BFD in the archive. */ struct bfd *archive_head; /* The first BFD in the archive. */ bfd_boolean has_armap; - + /* A chain of BFD structures involved in a link. */ struct bfd *link_next; - + /* A field used by _bfd_generic_link_add_archive_symbols. This will be used only for archive elements. */ int archive_pass; - + /* Used by the back end to hold private data. */ union { @@ -457,20 +458,20 @@ void *any; } tdata; - + /* Used by the application to hold private data. */ void *usrdata; - + /* Where all the allocated stuff under this BFD goes. This is a struct objalloc *, but we use void * to avoid requiring the inclusion of objalloc.h. */ void *memory; }; -2.2 Error reporting -=================== +Error reporting +=============== -Most BFD functions return nonzero on success (check their individual + Most BFD functions return nonzero on success (check their individual documentation for precise semantics). On an error, they call `bfd_set_error' to set an error condition that callers can check by calling `bfd_get_error'. If that returns `bfd_error_system_call', then @@ -479,10 +480,10 @@ The easiest way to report a BFD error to the user is to use `bfd_perror'. -2.2.1 Type `bfd_error_type' ---------------------------- +Type `bfd_error_type' +--------------------- -The values returned by `bfd_get_error' are defined by the enumerated + The values returned by `bfd_get_error' are defined by the enumerated type `bfd_error_type'. @@ -510,36 +511,36 @@ bfd_error_invalid_error_code } bfd_error_type; - -2.2.1.1 `bfd_get_error' -....................... -*Synopsis* +`bfd_get_error' +............... + + *Synopsis* bfd_error_type bfd_get_error (void); *Description* Return the current BFD error condition. -2.2.1.2 `bfd_set_error' -....................... +`bfd_set_error' +............... -*Synopsis* + *Synopsis* void bfd_set_error (bfd_error_type error_tag); *Description* Set the BFD error condition to be ERROR_TAG. -2.2.1.3 `bfd_errmsg' -.................... +`bfd_errmsg' +............ -*Synopsis* + *Synopsis* const char *bfd_errmsg (bfd_error_type error_tag); *Description* Return a string describing the error ERROR_TAG, or the system error if ERROR_TAG is `bfd_error_system_call'. -2.2.1.4 `bfd_perror' -.................... +`bfd_perror' +............ -*Synopsis* + *Synopsis* void bfd_perror (const char *message); *Description* Print to the standard error stream a string describing the last BFD @@ -548,61 +549,61 @@ string printed is preceded by MESSAGE, a colon, and a space. It is followed by a newline. -2.2.2 BFD error handler ------------------------ +BFD error handler +----------------- -Some BFD functions want to print messages describing the problem. They -call a BFD error handler function. This function may be overridden by -the program. + Some BFD functions want to print messages describing the problem. +They call a BFD error handler function. This function may be +overridden by the program. The BFD error handler acts like printf. typedef void (*bfd_error_handler_type) (const char *, ...); - -2.2.2.1 `bfd_set_error_handler' -............................... -*Synopsis* +`bfd_set_error_handler' +....................... + + *Synopsis* bfd_error_handler_type bfd_set_error_handler (bfd_error_handler_type); *Description* Set the BFD error handler function. Returns the previous function. -2.2.2.2 `bfd_set_error_program_name' -.................................... +`bfd_set_error_program_name' +............................ -*Synopsis* + *Synopsis* void bfd_set_error_program_name (const char *); *Description* Set the program name to use when printing a BFD error. This is printed before the error message followed by a colon and space. The string must not be changed after it is passed to this function. -2.2.2.3 `bfd_get_error_handler' -............................... +`bfd_get_error_handler' +....................... -*Synopsis* + *Synopsis* bfd_error_handler_type bfd_get_error_handler (void); *Description* Return the BFD error handler function. -2.3 Symbols -=========== +Symbols +======= -2.3.0.1 `bfd_get_reloc_upper_bound' -................................... +`bfd_get_reloc_upper_bound' +........................... -*Synopsis* + *Synopsis* long bfd_get_reloc_upper_bound (bfd *abfd, asection *sect); *Description* Return the number of bytes required to store the relocation information associated with section SECT attached to bfd ABFD. If an error occurs, return -1. -2.3.0.2 `bfd_canonicalize_reloc' -................................ +`bfd_canonicalize_reloc' +........................ -*Synopsis* + *Synopsis* long bfd_canonicalize_reloc (bfd *abfd, asection *sec, arelent **loc, asymbol **syms); *Description* @@ -614,20 +615,20 @@ The SYMS table is also needed for horrible internal magic reasons. -2.3.0.3 `bfd_set_reloc' -....................... +`bfd_set_reloc' +............... -*Synopsis* + *Synopsis* void bfd_set_reloc (bfd *abfd, asection *sec, arelent **rel, unsigned int count); *Description* Set the relocation pointer and count within section SEC to the values REL and COUNT. The argument ABFD is ignored. -2.3.0.4 `bfd_set_file_flags' -............................ +`bfd_set_file_flags' +.................... -*Synopsis* + *Synopsis* bfd_boolean bfd_set_file_flags (bfd *abfd, flagword flags); *Description* Set the flag word in the BFD ABFD to the value FLAGS. @@ -643,10 +644,10 @@ was made to set the `D_PAGED' bit on a BFD format which does not support demand paging. -2.3.0.5 `bfd_get_arch_size' -........................... +`bfd_get_arch_size' +................... -*Synopsis* + *Synopsis* int bfd_get_arch_size (bfd *abfd); *Description* Returns the architecture address size, in bits, as determined by the @@ -656,10 +657,10 @@ *Returns* Returns the arch size in bits if known, `-1' otherwise. -2.3.0.6 `bfd_get_sign_extend_vma' -................................. +`bfd_get_sign_extend_vma' +......................... -*Synopsis* + *Synopsis* int bfd_get_sign_extend_vma (bfd *abfd); *Description* Indicates if the target architecture "naturally" sign extends an @@ -673,10 +674,10 @@ addresses, `0' if the target architecture is known to not sign extend addresses, and `-1' otherwise. -2.3.0.7 `bfd_set_start_address' -............................... +`bfd_set_start_address' +....................... -*Synopsis* + *Synopsis* bfd_boolean bfd_set_start_address (bfd *abfd, bfd_vma vma); *Description* Make VMA the entry point of output BFD ABFD. @@ -684,30 +685,30 @@ *Returns* Returns `TRUE' on success, `FALSE' otherwise. -2.3.0.8 `bfd_get_gp_size' -......................... +`bfd_get_gp_size' +................. -*Synopsis* + *Synopsis* unsigned int bfd_get_gp_size (bfd *abfd); *Description* Return the maximum size of objects to be optimized using the GP register under MIPS ECOFF. This is typically set by the `-G' argument to the compiler, assembler or linker. -2.3.0.9 `bfd_set_gp_size' -......................... +`bfd_set_gp_size' +................. -*Synopsis* + *Synopsis* void bfd_set_gp_size (bfd *abfd, unsigned int i); *Description* Set the maximum size of objects to be optimized using the GP register under ECOFF or MIPS ELF. This is typically set by the `-G' argument to the compiler, assembler or linker. -2.3.0.10 `bfd_scan_vma' -....................... +`bfd_scan_vma' +.............. -*Synopsis* + *Synopsis* bfd_vma bfd_scan_vma (const char *string, const char **end, int base); *Description* Convert, like `strtoul', a numerical expression STRING into a `bfd_vma' @@ -720,10 +721,10 @@ If the value would overflow, the maximum `bfd_vma' value is returned. -2.3.0.11 `bfd_copy_private_header_data' -....................................... +`bfd_copy_private_header_data' +.............................. -*Synopsis* + *Synopsis* bfd_boolean bfd_copy_private_header_data (bfd *ibfd, bfd *obfd); *Description* Copy private BFD header information from the BFD IBFD to the the BFD @@ -738,10 +739,10 @@ BFD_SEND (obfd, _bfd_copy_private_header_data, \ (ibfd, obfd)) -2.3.0.12 `bfd_copy_private_bfd_data' -.................................... +`bfd_copy_private_bfd_data' +........................... -*Synopsis* + *Synopsis* bfd_boolean bfd_copy_private_bfd_data (bfd *ibfd, bfd *obfd); *Description* Copy private BFD information from the BFD IBFD to the the BFD OBFD. @@ -754,10 +755,10 @@ BFD_SEND (obfd, _bfd_copy_private_bfd_data, \ (ibfd, obfd)) -2.3.0.13 `bfd_merge_private_bfd_data' -..................................... +`bfd_merge_private_bfd_data' +............................ -*Synopsis* + *Synopsis* bfd_boolean bfd_merge_private_bfd_data (bfd *ibfd, bfd *obfd); *Description* Merge private BFD information from the BFD IBFD to the the output file @@ -771,10 +772,10 @@ BFD_SEND (obfd, _bfd_merge_private_bfd_data, \ (ibfd, obfd)) -2.3.0.14 `bfd_set_private_flags' -................................ +`bfd_set_private_flags' +....................... -*Synopsis* + *Synopsis* bfd_boolean bfd_set_private_flags (bfd *abfd, flagword flags); *Description* Set private BFD flag information in the BFD ABFD. Return `TRUE' on @@ -786,96 +787,96 @@ #define bfd_set_private_flags(abfd, flags) \ BFD_SEND (abfd, _bfd_set_private_flags, (abfd, flags)) -2.3.0.15 `Other functions' -.......................... +`Other functions' +................. -*Description* + *Description* The following functions exist but have not yet been documented. #define bfd_sizeof_headers(abfd, reloc) \ BFD_SEND (abfd, _bfd_sizeof_headers, (abfd, reloc)) - + #define bfd_find_nearest_line(abfd, sec, syms, off, file, func, line) \ BFD_SEND (abfd, _bfd_find_nearest_line, \ (abfd, sec, syms, off, file, func, line)) - + #define bfd_debug_info_start(abfd) \ BFD_SEND (abfd, _bfd_debug_info_start, (abfd)) - + #define bfd_debug_info_end(abfd) \ BFD_SEND (abfd, _bfd_debug_info_end, (abfd)) - + #define bfd_debug_info_accumulate(abfd, section) \ BFD_SEND (abfd, _bfd_debug_info_accumulate, (abfd, section)) - + #define bfd_stat_arch_elt(abfd, stat) \ BFD_SEND (abfd, _bfd_stat_arch_elt,(abfd, stat)) - + #define bfd_update_armap_timestamp(abfd) \ BFD_SEND (abfd, _bfd_update_armap_timestamp, (abfd)) - + #define bfd_set_arch_mach(abfd, arch, mach)\ BFD_SEND ( abfd, _bfd_set_arch_mach, (abfd, arch, mach)) - + #define bfd_relax_section(abfd, section, link_info, again) \ BFD_SEND (abfd, _bfd_relax_section, (abfd, section, link_info, again)) - + #define bfd_gc_sections(abfd, link_info) \ BFD_SEND (abfd, _bfd_gc_sections, (abfd, link_info)) - + #define bfd_merge_sections(abfd, link_info) \ BFD_SEND (abfd, _bfd_merge_sections, (abfd, link_info)) - + #define bfd_is_group_section(abfd, sec) \ BFD_SEND (abfd, _bfd_is_group_section, (abfd, sec)) - + #define bfd_discard_group(abfd, sec) \ BFD_SEND (abfd, _bfd_discard_group, (abfd, sec)) - + #define bfd_link_hash_table_create(abfd) \ BFD_SEND (abfd, _bfd_link_hash_table_create, (abfd)) - + #define bfd_link_hash_table_free(abfd, hash) \ BFD_SEND (abfd, _bfd_link_hash_table_free, (hash)) - + #define bfd_link_add_symbols(abfd, info) \ BFD_SEND (abfd, _bfd_link_add_symbols, (abfd, info)) - + #define bfd_link_just_syms(abfd, sec, info) \ BFD_SEND (abfd, _bfd_link_just_syms, (sec, info)) - + #define bfd_final_link(abfd, info) \ BFD_SEND (abfd, _bfd_final_link, (abfd, info)) - + #define bfd_free_cached_info(abfd) \ BFD_SEND (abfd, _bfd_free_cached_info, (abfd)) - + #define bfd_get_dynamic_symtab_upper_bound(abfd) \ BFD_SEND (abfd, _bfd_get_dynamic_symtab_upper_bound, (abfd)) - + #define bfd_print_private_bfd_data(abfd, file)\ BFD_SEND (abfd, _bfd_print_private_bfd_data, (abfd, file)) - + #define bfd_canonicalize_dynamic_symtab(abfd, asymbols) \ BFD_SEND (abfd, _bfd_canonicalize_dynamic_symtab, (abfd, asymbols)) - + #define bfd_get_synthetic_symtab(abfd, count, syms, dyncount, dynsyms, ret) \ BFD_SEND (abfd, _bfd_get_synthetic_symtab, (abfd, count, syms, \ dyncount, dynsyms, ret)) - + #define bfd_get_dynamic_reloc_upper_bound(abfd) \ BFD_SEND (abfd, _bfd_get_dynamic_reloc_upper_bound, (abfd)) - + #define bfd_canonicalize_dynamic_reloc(abfd, arels, asyms) \ BFD_SEND (abfd, _bfd_canonicalize_dynamic_reloc, (abfd, arels, asyms)) - + extern bfd_byte *bfd_get_relocated_section_contents (bfd *, struct bfd_link_info *, struct bfd_link_order *, bfd_byte *, bfd_boolean, asymbol **); -2.3.0.16 `bfd_alt_mach_code' -............................ +`bfd_alt_mach_code' +................... -*Synopsis* + *Synopsis* bfd_boolean bfd_alt_mach_code (bfd *abfd, int alternative); *Description* When more than one machine code number is available for the same @@ -894,11 +895,11 @@ unsigned int section_count; struct bfd_hash_table section_htab; }; - -2.3.0.17 `bfd_preserve_save' -............................ -*Synopsis* +`bfd_preserve_save' +................... + + *Synopsis* bfd_boolean bfd_preserve_save (bfd *, struct bfd_preserve *); *Description* When testing an object for compatibility with a particular target @@ -910,30 +911,30 @@ state works in practice. This function stores the subset and reinitializes the bfd. -2.3.0.18 `bfd_preserve_restore' -............................... +`bfd_preserve_restore' +...................... -*Synopsis* + *Synopsis* void bfd_preserve_restore (bfd *, struct bfd_preserve *); *Description* This function restores bfd state saved by bfd_preserve_save. If MARKER is non-NULL in struct bfd_preserve then that block and all subsequently bfd_alloc'd memory is freed. -2.3.0.19 `bfd_preserve_finish' -.............................. +`bfd_preserve_finish' +..................... -*Synopsis* + *Synopsis* void bfd_preserve_finish (bfd *, struct bfd_preserve *); *Description* This function should be called when the bfd state saved by bfd_preserve_save is no longer needed. ie. when the back-end object_p function returns with success. -2.3.0.20 `struct bfd_iovec' -........................... +`struct bfd_iovec' +.................. -*Description* + *Description* The `struct bfd_iovec' contains the internal file I/O class. Each `BFD' has an instance of this class and all file I/O is routed through it (it is assumed that the instance implements all methods listed @@ -960,19 +961,19 @@ int (*bstat) (struct bfd *abfd, struct stat *sb); }; -2.3.0.21 `bfd_get_mtime' -........................ +`bfd_get_mtime' +............... -*Synopsis* + *Synopsis* long bfd_get_mtime (bfd *abfd); *Description* Return the file modification time (as read from the file system, or from the archive header for archive members). -2.3.0.22 `bfd_get_size' -....................... +`bfd_get_size' +.............. -*Synopsis* + *Synopsis* long bfd_get_size (bfd *abfd); *Description* Return the file size (as read from file system) for the file associated @@ -1019,10 +1020,10 @@  File: bfd.info, Node: Memory Usage, Next: Initialization, Prev: BFD front end, Up: BFD front end -2.4 Memory Usage -================ +Memory Usage +============ -BFD keeps all of its internal structures in obstacks. There is one + BFD keeps all of its internal structures in obstacks. There is one obstack per open BFD file, into which the current state is stored. When a BFD is closed, the obstack is deleted, and so everything which has been allocated by BFD for the closing file is thrown away. @@ -1045,15 +1046,15 @@  File: bfd.info, Node: Initialization, Next: Sections, Prev: Memory Usage, Up: BFD front end -2.5 Initialization -================== +Initialization +============== -These are the functions that handle initializing a BFD. + These are the functions that handle initializing a BFD. -2.5.0.1 `bfd_init' -.................. +`bfd_init' +.......... -*Synopsis* + *Synopsis* void bfd_init (void); *Description* This routine must be called before any other BFD function to initialize @@ -1062,13 +1063,13 @@  File: bfd.info, Node: Sections, Next: Symbols, Prev: Initialization, Up: BFD front end -2.6 Sections -============ +Sections +======== -The raw data contained within a BFD is maintained through the section -abstraction. A single BFD may have any number of sections. It keeps -hold of them by pointing to the first; each one points to the next in -the list. + The raw data contained within a BFD is maintained through the +section abstraction. A single BFD may have any number of sections. It +keeps hold of them by pointing to the first; each one points to the +next in the list. Sections are supported in BFD in `section.c'. @@ -1082,10 +1083,10 @@  File: bfd.info, Node: Section Input, Next: Section Output, Prev: Sections, Up: Sections -2.6.1 Section input -------------------- +Section input +------------- -When a BFD is opened for reading, the section structures are created + When a BFD is opened for reading, the section structures are created and attached to the BFD. Each section has a name which describes the section in the outside @@ -1114,10 +1115,10 @@  File: bfd.info, Node: Section Output, Next: typedef asection, Prev: Section Input, Up: Sections -2.6.2 Section output --------------------- +Section output +-------------- -To write a new object style BFD, the various sections to be written + To write a new object style BFD, the various sections to be written have to be created. They are attached to the BFD in the same way as input sections; data is written to the sections using `bfd_set_section_contents'. @@ -1151,12 +1152,12 @@ size 0x103 | output_section --------| -2.6.3 Link orders ------------------ +Link orders +----------- -The data within a section is stored in a "link_order". These are much -like the fixups in `gas'. The link_order abstraction allows a section -to grow and shrink within itself. + The data within a section is stored in a "link_order". These are +much like the fixups in `gas'. The link_order abstraction allows a +section to grow and shrink within itself. A link_order knows how big it is, and which is the next link_order and where the raw data for it is; it also points to a list of @@ -1172,10 +1173,10 @@  File: bfd.info, Node: typedef asection, Next: section prototypes, Prev: Section Output, Up: Sections -2.6.4 typedef asection ----------------------- +typedef asection +---------------- -Here is the section structure: + Here is the section structure: typedef struct bfd_section @@ -1183,47 +1184,47 @@ /* The name of the section; the name isn't a copy, the pointer is the same as that passed to bfd_make_section. */ const char *name; - + /* A unique sequence number. */ int id; - + /* Which section in the bfd; 0..n-1 as sections are created in a bfd. */ int index; - + /* The next section in the list belonging to the BFD, or NULL. */ struct bfd_section *next; - + /* The field flags contains attributes of the section. Some flags are read in from the object file, and some are synthesized from other information. */ flagword flags; - + #define SEC_NO_FLAGS 0x000 - + /* Tells the OS to allocate space for this section when loading. This is clear for a section containing debug information only. */ #define SEC_ALLOC 0x001 - + /* Tells the OS to load the section from the file when loading. This is clear for a .bss section. */ #define SEC_LOAD 0x002 - + /* The section contains data still to be relocated, so there is some relocation information too. */ #define SEC_RELOC 0x004 - + /* A signal to the OS that the section contains read only data. */ #define SEC_READONLY 0x008 - + /* The section contains code only. */ #define SEC_CODE 0x010 - + /* The section contains data only. */ #define SEC_DATA 0x020 - + /* The section will reside in ROM. */ #define SEC_ROM 0x040 - + /* The section contains constructor information. This section type is used by the linker to create lists of constructors and destructors used by `g++'. When a back end sees a symbol @@ -1235,19 +1236,19 @@ contained within - exactly the operations it would peform on standard data. */ #define SEC_CONSTRUCTOR 0x080 - + /* The section has contents - a data section could be `SEC_ALLOC' | `SEC_HAS_CONTENTS'; a debug section could be `SEC_HAS_CONTENTS' */ #define SEC_HAS_CONTENTS 0x100 - + /* An instruction to the linker to not output the section even if it has information which would normally be written. */ #define SEC_NEVER_LOAD 0x200 - + /* The section contains thread local data. */ #define SEC_THREAD_LOCAL 0x400 - + /* The section has GOT references. This flag is only for the linker, and is currently only used by the elf32-hppa back end. It will be set if global offset table references were detected @@ -1255,90 +1256,90 @@ contains PIC code, and must be handled specially when doing a static link. */ #define SEC_HAS_GOT_REF 0x800 - + /* The section contains common symbols (symbols may be defined multiple times, the value of a symbol is the amount of space it requires, and the largest symbol value is the one used). Most targets have exactly one of these (which we translate to bfd_com_section_ptr), but ECOFF has two. */ #define SEC_IS_COMMON 0x1000 - + /* The section contains only debugging information. For example, this is set for ELF .debug and .stab sections. strip tests this flag to see if a section can be discarded. */ #define SEC_DEBUGGING 0x2000 - + /* The contents of this section are held in memory pointed to by the contents field. This is checked by bfd_get_section_contents, and the data is retrieved from memory if appropriate. */ #define SEC_IN_MEMORY 0x4000 - + /* The contents of this section are to be excluded by the linker for executable and shared objects unless those objects are to be further relocated. */ #define SEC_EXCLUDE 0x8000 - + /* The contents of this section are to be sorted based on the sum of the symbol and addend values specified by the associated relocation entries. Entries without associated relocation entries will be appended to the end of the section in an unspecified order. */ #define SEC_SORT_ENTRIES 0x10000 - + /* When linking, duplicate sections of the same name should be discarded, rather than being combined into a single section as is usually done. This is similar to how common symbols are handled. See SEC_LINK_DUPLICATES below. */ #define SEC_LINK_ONCE 0x20000 - + /* If SEC_LINK_ONCE is set, this bitfield describes how the linker should handle duplicate sections. */ #define SEC_LINK_DUPLICATES 0x40000 - + /* This value for SEC_LINK_DUPLICATES means that duplicate sections with the same name should simply be discarded. */ #define SEC_LINK_DUPLICATES_DISCARD 0x0 - + /* This value for SEC_LINK_DUPLICATES means that the linker should warn if there are any duplicate sections, although it should still only link one copy. */ #define SEC_LINK_DUPLICATES_ONE_ONLY 0x80000 - + /* This value for SEC_LINK_DUPLICATES means that the linker should warn if any duplicate sections are a different size. */ #define SEC_LINK_DUPLICATES_SAME_SIZE 0x100000 - + /* This value for SEC_LINK_DUPLICATES means that the linker should warn if any duplicate sections contain different contents. */ #define SEC_LINK_DUPLICATES_SAME_CONTENTS \ (SEC_LINK_DUPLICATES_ONE_ONLY | SEC_LINK_DUPLICATES_SAME_SIZE) - + /* This section was created by the linker as part of dynamic relocation or other arcane processing. It is skipped when going through the first-pass output, trusting that someone else up the line will take care of it later. */ #define SEC_LINKER_CREATED 0x200000 - + /* This section should not be subject to garbage collection. */ #define SEC_KEEP 0x400000 - + /* This section contains "short" data, and should be placed "near" the GP. */ #define SEC_SMALL_DATA 0x800000 - + /* Attempt to merge identical entities in the section. Entity size is given in the entsize field. */ #define SEC_MERGE 0x1000000 - + /* If given with SEC_MERGE, entities to merge are zero terminated strings where entsize specifies character size instead of fixed size entries. */ #define SEC_STRINGS 0x2000000 - + /* This section contains data about section groups. */ #define SEC_GROUP 0x4000000 - + /* The section is a COFF shared library section. This flag is only for the linker. If this type of section appears in the input file, the linker must copy it to the output file @@ -1349,45 +1350,45 @@ allow the back end to control what the linker does with sections. */ #define SEC_COFF_SHARED_LIBRARY 0x10000000 - + /* This section contains data which may be shared with other executables or shared objects. This is for COFF only. */ #define SEC_COFF_SHARED 0x20000000 - + /* When a section with this flag is being linked, then if the size of the input section is less than a page, it should not cross a page boundary. If the size of the input section is one page or more, it should be aligned on a page boundary. This is for TI TMS320C54X only. */ #define SEC_TIC54X_BLOCK 0x40000000 - + /* Conditionally link this section; do not link if there are no references found to any symbol in the section. This is for TI TMS320C54X only. */ #define SEC_TIC54X_CLINK 0x80000000 - + /* End of section flags. */ - + /* Some internal packed boolean fields. */ - + /* See the vma field. */ unsigned int user_set_vma : 1; - + /* A mark flag used by some of the linker backends. */ unsigned int linker_mark : 1; - + /* Another mark flag used by some of the linker backends. Set for output sections that have an input section. */ unsigned int linker_has_input : 1; - + /* A mark flag used by some linker backends for garbage collection. */ unsigned int gc_mark : 1; - + /* The following flags are used by the ELF linker. */ - + /* Mark sections which have been allocated to segments. */ unsigned int segment_mark : 1; - + /* Type of sec_info information. */ unsigned int sec_info_type:3; #define ELF_INFO_TYPE_NONE 0 @@ -1395,27 +1396,27 @@ #define ELF_INFO_TYPE_MERGE 2 #define ELF_INFO_TYPE_EH_FRAME 3 #define ELF_INFO_TYPE_JUST_SYMS 4 - + /* Nonzero if this section uses RELA relocations, rather than REL. */ unsigned int use_rela_p:1; - + /* Bits used by various backends. The generic code doesn't touch these fields. */ - + /* Nonzero if this section has TLS related relocations. */ unsigned int has_tls_reloc:1; - + /* Nonzero if this section has a gp reloc. */ unsigned int has_gp_reloc:1; - + /* Nonzero if this section needs the relax finalize pass. */ unsigned int need_finalize_relax:1; - + /* Whether relocations have been processed. */ unsigned int reloc_done : 1; - + /* End of internal packed boolean fields. */ - + /* The virtual memory address of the section - where it will be at run time. The symbols are relocated against this. The user_set_vma flag is maintained by bfd; if it's not set, the @@ -1423,17 +1424,17 @@ the default address for `.data' is dependent on the specific target and various flags). */ bfd_vma vma; - + /* The load address of the section - where it would be in a rom image; really only used for writing section header information. */ bfd_vma lma; - + /* The size of the section in octets, as it will be output. Contains a value even if the section has no contents (e.g., the size of `.bss'). */ bfd_size_type size; - + /* For input sections, the original size on disk of the section, in octets. This field is used by the linker relaxation code. It is currently only set for sections where the linker relaxation scheme @@ -1443,7 +1444,7 @@ For output sections, rawsize holds the section size calculated on a previous linker relaxation pass. */ bfd_size_type rawsize; - + /* If this section is going to be output, then this value is the offset in *bytes* into the output section of the first byte in the input section (byte ==> smallest addressable unit on the @@ -1452,81 +1453,81 @@ would be 100. However, if the target byte size is 16 bits (bfd_octets_per_byte is "2"), this value would be 50. */ bfd_vma output_offset; - + /* The output section through which to map on output. */ struct bfd_section *output_section; - + /* The alignment requirement of the section, as an exponent of 2 - e.g., 3 aligns to 2^3 (or 8). */ unsigned int alignment_power; - + /* If an input section, a pointer to a vector of relocation records for the data in this section. */ struct reloc_cache_entry *relocation; - + /* If an output section, a pointer to a vector of pointers to relocation records for the data in this section. */ struct reloc_cache_entry **orelocation; - + /* The number of relocation records in one of the above. */ unsigned reloc_count; - + /* Information below is back end specific - and not always used or updated. */ - + /* File position of section data. */ file_ptr filepos; - + /* File position of relocation info. */ file_ptr rel_filepos; - + /* File position of line data. */ file_ptr line_filepos; - + /* Pointer to data for applications. */ void *userdata; - + /* If the SEC_IN_MEMORY flag is set, this points to the actual contents. */ unsigned char *contents; - + /* Attached line number information. */ alent *lineno; - + /* Number of line number records. */ unsigned int lineno_count; - + /* Entity size for merging purposes. */ unsigned int entsize; - + /* Points to the kept section if this section is a link-once section, and is discarded. */ struct bfd_section *kept_section; - + /* When a section is being output, this value changes as more linenumbers are written out. */ file_ptr moving_line_filepos; - + /* What the section number is in the target world. */ int target_index; - + void *used_by_bfd; - + /* If this is a constructor section then here is a list of the relocations created to relocate items within it. */ struct relent_chain *constructor_chain; - + /* The BFD which owns the section. */ bfd *owner; - + /* A symbol which points at this section only. */ struct bfd_symbol *symbol; struct bfd_symbol **symbol_ptr_ptr; - + struct bfd_link_order *link_order_head; struct bfd_link_order *link_order_tail; } asection; - + /* These sections are global, and are managed by BFD. The application and target back end are not permitted to change the values in these sections. New code should use the section_ptr macros rather @@ -1536,7 +1537,7 @@ #define BFD_UND_SECTION_NAME "*UND*" #define BFD_COM_SECTION_NAME "*COM*" #define BFD_IND_SECTION_NAME "*IND*" - + /* The absolute section. */ extern asection bfd_abs_section; #define bfd_abs_section_ptr ((asection *) &bfd_abs_section) @@ -1552,18 +1553,18 @@ extern asection bfd_ind_section; #define bfd_ind_section_ptr ((asection *) &bfd_ind_section) #define bfd_is_ind_section(sec) ((sec) == bfd_ind_section_ptr) - + #define bfd_is_const_section(SEC) \ ( ((SEC) == bfd_abs_section_ptr) \ || ((SEC) == bfd_und_section_ptr) \ || ((SEC) == bfd_com_section_ptr) \ || ((SEC) == bfd_ind_section_ptr)) - + extern const struct bfd_symbol * const bfd_abs_symbol; extern const struct bfd_symbol * const bfd_com_symbol; extern const struct bfd_symbol * const bfd_und_symbol; extern const struct bfd_symbol * const bfd_ind_symbol; - + /* Macros to handle insertion and deletion of a bfd's sections. These only handle the list pointers, ie. do not adjust section_count, target_index etc. */ @@ -1592,24 +1593,24 @@  File: bfd.info, Node: section prototypes, Prev: typedef asection, Up: Sections -2.6.5 Section prototypes ------------------------- +Section prototypes +------------------ -These are the functions exported by the section handling part of BFD. + These are the functions exported by the section handling part of BFD. -2.6.5.1 `bfd_section_list_clear' -................................ +`bfd_section_list_clear' +........................ -*Synopsis* + *Synopsis* void bfd_section_list_clear (bfd *); *Description* Clears the section list, and also resets the section count and hash table entries. -2.6.5.2 `bfd_get_section_by_name' -................................. +`bfd_get_section_by_name' +......................... -*Synopsis* + *Synopsis* asection *bfd_get_section_by_name (bfd *abfd, const char *name); *Description* Run through ABFD and return the one of the `asection's whose name @@ -1620,10 +1621,10 @@ `strcmp' on the name (or better yet, base it on the section flags or something else) for each section. -2.6.5.3 `bfd_get_section_by_name_if' -.................................... +`bfd_get_section_by_name_if' +............................ -*Synopsis* + *Synopsis* asection *bfd_get_section_by_name_if (bfd *abfd, const char *name, @@ -1639,10 +1640,10 @@ It returns the first section for which FUNC returns true, otherwise `NULL'. -2.6.5.4 `bfd_get_unique_section_name' -..................................... +`bfd_get_unique_section_name' +............................. -*Synopsis* + *Synopsis* char *bfd_get_unique_section_name (bfd *abfd, const char *templat, int *count); *Description* @@ -1651,10 +1652,10 @@ specifies the first number tried as a suffix to generate a unique name. The value pointed to by COUNT will be incremented in this case. -2.6.5.5 `bfd_make_section_old_way' -.................................. +`bfd_make_section_old_way' +.......................... -*Synopsis* + *Synopsis* asection *bfd_make_section_old_way (bfd *abfd, const char *name); *Description* Create a new empty section called NAME and attach it to the end of the @@ -1671,10 +1672,10 @@ * `bfd_error_no_memory' - If memory allocation fails. -2.6.5.6 `bfd_make_section_anyway' -................................. +`bfd_make_section_anyway' +......................... -*Synopsis* + *Synopsis* asection *bfd_make_section_anyway (bfd *abfd, const char *name); *Description* Create a new empty section called NAME and attach it to the end of the @@ -1687,10 +1688,10 @@ * `bfd_error_no_memory' - If memory allocation fails. -2.6.5.7 `bfd_make_section' -.......................... +`bfd_make_section' +.................. -*Synopsis* + *Synopsis* asection *bfd_make_section (bfd *, const char *name); *Description* Like `bfd_make_section_anyway', but return `NULL' (without calling @@ -1698,10 +1699,10 @@ already a section named NAME. If there is an error, return `NULL' and set `bfd_error'. -2.6.5.8 `bfd_set_section_flags' -............................... +`bfd_set_section_flags' +....................... -*Synopsis* + *Synopsis* bfd_boolean bfd_set_section_flags (bfd *abfd, asection *sec, flagword flags); *Description* @@ -1713,10 +1714,10 @@ more of the attributes requested. For example, a .bss section in `a.out' may not have the `SEC_HAS_CONTENTS' field set. -2.6.5.9 `bfd_map_over_sections' -............................... +`bfd_map_over_sections' +....................... -*Synopsis* + *Synopsis* void bfd_map_over_sections (bfd *abfd, void (*func) (bfd *abfd, asection *sect, void *obj), @@ -1734,10 +1735,10 @@ for (p = abfd->sections; p != NULL; p = p->next) func (abfd, p, ...) -2.6.5.10 `bfd_sections_find_if' -............................... +`bfd_sections_find_if' +...................... -*Synopsis* + *Synopsis* asection *bfd_sections_find_if (bfd *abfd, bfd_boolean (*operation) (bfd *abfd, asection *sect, void *obj), @@ -1751,10 +1752,10 @@ It returns the first section for which OPERATION returns true. -2.6.5.11 `bfd_set_section_size' -............................... +`bfd_set_section_size' +...................... -*Synopsis* + *Synopsis* bfd_boolean bfd_set_section_size (bfd *abfd, asection *sec, bfd_size_type val); *Description* @@ -1765,10 +1766,10 @@ * `bfd_error_invalid_operation' - Writing has started to the BFD, so setting the size is invalid. -2.6.5.12 `bfd_set_section_contents' -................................... +`bfd_set_section_contents' +.......................... -*Synopsis* + *Synopsis* bfd_boolean bfd_set_section_contents (bfd *abfd, asection *section, const void *data, file_ptr offset, bfd_size_type count); @@ -1786,10 +1787,10 @@ This routine is front end to the back end function `_bfd_set_section_contents'. -2.6.5.13 `bfd_get_section_contents' -................................... +`bfd_get_section_contents' +.......................... -*Synopsis* + *Synopsis* bfd_boolean bfd_get_section_contents (bfd *abfd, asection *section, void *location, file_ptr offset, bfd_size_type count); @@ -1803,20 +1804,20 @@ flag set, then the LOCATION is filled with zeroes. If no errors occur, `TRUE' is returned, else `FALSE'. -2.6.5.14 `bfd_malloc_and_get_section' -..................................... +`bfd_malloc_and_get_section' +............................ -*Synopsis* + *Synopsis* bfd_boolean bfd_malloc_and_get_section (bfd *abfd, asection *section, bfd_byte **buf); *Description* Read all data from SECTION in BFD ABFD into a buffer, *BUF, malloc'd by this function. -2.6.5.15 `bfd_copy_private_section_data' -........................................ +`bfd_copy_private_section_data' +............................... -*Synopsis* + *Synopsis* bfd_boolean bfd_copy_private_section_data (bfd *ibfd, asection *isec, bfd *obfd, asection *osec); *Description* @@ -1831,10 +1832,10 @@ BFD_SEND (obfd, _bfd_copy_private_section_data, \ (ibfd, isection, obfd, osection)) -2.6.5.16 `_bfd_strip_section_from_output' -......................................... +`_bfd_strip_section_from_output' +................................ -*Synopsis* + *Synopsis* void _bfd_strip_section_from_output (struct bfd_link_info *info, asection *section); *Description* @@ -1845,18 +1846,18 @@ called too late in the linking process, when it's not safe to remove sections. -2.6.5.17 `bfd_generic_is_group_section' -....................................... +`bfd_generic_is_group_section' +.............................. -*Synopsis* + *Synopsis* bfd_boolean bfd_generic_is_group_section (bfd *, const asection *sec); *Description* Returns TRUE if SEC is a member of a group. -2.6.5.18 `bfd_generic_discard_group' -.................................... +`bfd_generic_discard_group' +........................... -*Synopsis* + *Synopsis* bfd_boolean bfd_generic_discard_group (bfd *abfd, asection *group); *Description* Remove all members of GROUP from the output. @@ -1864,10 +1865,10 @@  File: bfd.info, Node: Symbols, Next: Archives, Prev: Sections, Up: BFD front end -2.7 Symbols -=========== +Symbols +======= -BFD tries to maintain as much symbol information as it can when it + BFD tries to maintain as much symbol information as it can when it moves information from file to file. BFD passes information to applications though the `asymbol' structure. When the application requests the symbol table, BFD reads the table in the native form and @@ -1899,34 +1900,34 @@  File: bfd.info, Node: Reading Symbols, Next: Writing Symbols, Prev: Symbols, Up: Symbols -2.7.1 Reading symbols ---------------------- +Reading symbols +--------------- -There are two stages to reading a symbol table from a BFD: allocating -storage, and the actual reading process. This is an excerpt from an -application which reads the symbol table: + There are two stages to reading a symbol table from a BFD: +allocating storage, and the actual reading process. This is an excerpt +from an application which reads the symbol table: long storage_needed; asymbol **symbol_table; long number_of_symbols; long i; - + storage_needed = bfd_get_symtab_upper_bound (abfd); - + if (storage_needed < 0) FAIL - + if (storage_needed == 0) return; - + symbol_table = xmalloc (storage_needed); ... number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); - + if (number_of_symbols < 0) FAIL - + for (i = 0; i < number_of_symbols; i++) process_symbol (symbol_table[i]); @@ -1936,11 +1937,11 @@  File: bfd.info, Node: Writing Symbols, Next: Mini Symbols, Prev: Reading Symbols, Up: Symbols -2.7.2 Writing symbols ---------------------- +Writing symbols +--------------- -Writing of a symbol table is automatic when a BFD open for writing is -closed. The application attaches a vector of pointers to pointers to + Writing of a symbol table is automatic when a BFD open for writing +is closed. The application attaches a vector of pointers to pointers to symbols to the BFD being written, and fills in the symbol count. The close and cleanup code reads through the table provided and performs all the necessary operations. The BFD output code must always be @@ -1954,7 +1955,7 @@ bfd *abfd; asymbol *ptrs[2]; asymbol *new; - + abfd = bfd_openw ("foo","a.out-sunos-big"); bfd_set_format (abfd, bfd_object); new = bfd_make_empty_symbol (abfd); @@ -1962,15 +1963,15 @@ new->section = bfd_make_section_old_way (abfd, ".text"); new->flags = BSF_GLOBAL; new->value = 0x12345; - + ptrs[0] = new; ptrs[1] = 0; - + bfd_set_symtab (abfd, ptrs, 1); bfd_close (abfd); return 0; } - + ./makesym nm foo 00012345 A dummy_symbol @@ -1983,10 +1984,10 @@  File: bfd.info, Node: Mini Symbols, Next: typedef asymbol, Prev: Writing Symbols, Up: Symbols -2.7.3 Mini Symbols ------------------- +Mini Symbols +------------ -Mini symbols provide read-only access to the symbol table. They use + Mini symbols provide read-only access to the symbol table. They use less memory space, but require more time to access. They can be useful for tools like nm or objdump, which may have to handle symbol tables of extremely large executables. @@ -2006,10 +2007,10 @@  File: bfd.info, Node: typedef asymbol, Next: symbol handling functions, Prev: Mini Symbols, Up: Symbols -2.7.4 typedef asymbol ---------------------- +typedef asymbol +--------------- -An `asymbol' has the form: + An `asymbol' has the form: typedef struct bfd_symbol @@ -2018,114 +2019,114 @@ is necessary so that a back end can work out what additional information (invisible to the application writer) is carried with the symbol. - + This field is *almost* redundant, since you can use section->owner instead, except that some symbols point to the global sections bfd_{abs,com,und}_section. This could be fixed by making these globals be per-bfd (or per-target-flavor). FIXME. */ struct bfd *the_bfd; /* Use bfd_asymbol_bfd(sym) to access this field. */ - + /* The text of the symbol. The name is left alone, and not copied; the application may not alter it. */ const char *name; - + /* The value of the symbol. This really should be a union of a numeric value with a pointer, since some flags indicate that a pointer to another symbol is stored here. */ symvalue value; - + /* Attributes of a symbol. */ #define BSF_NO_FLAGS 0x00 - + /* The symbol has local scope; `static' in `C'. The value is the offset into the section of the data. */ #define BSF_LOCAL 0x01 - + /* The symbol has global scope; initialized data in `C'. The value is the offset into the section of the data. */ #define BSF_GLOBAL 0x02 - + /* The symbol has global scope and is exported. The value is the offset into the section of the data. */ #define BSF_EXPORT BSF_GLOBAL /* No real difference. */ - + /* A normal C symbol would be one of: `BSF_LOCAL', `BSF_FORT_COMM', `BSF_UNDEFINED' or `BSF_GLOBAL'. */ - + /* The symbol is a debugging record. The value has an arbitrary meaning, unless BSF_DEBUGGING_RELOC is also set. */ #define BSF_DEBUGGING 0x08 - + /* The symbol denotes a function entry point. Used in ELF, perhaps others someday. */ #define BSF_FUNCTION 0x10 - + /* Used by the linker. */ #define BSF_KEEP 0x20 #define BSF_KEEP_G 0x40 - + /* A weak global symbol, overridable without warnings by a regular global symbol of the same name. */ #define BSF_WEAK 0x80 - + /* This symbol was created to point to a section, e.g. ELF's STT_SECTION symbols. */ #define BSF_SECTION_SYM 0x100 - + /* The symbol used to be a common symbol, but now it is allocated. */ #define BSF_OLD_COMMON 0x200 - + /* The default value for common data. */ #define BFD_FORT_COMM_DEFAULT_VALUE 0 - + /* In some files the type of a symbol sometimes alters its location in an output file - ie in coff a `ISFCN' symbol which is also `C_EXT' symbol appears where it was declared and not at the end of a section. This bit is set by the target BFD part to convey this information. */ #define BSF_NOT_AT_END 0x400 - + /* Signal that the symbol is the label of constructor section. */ #define BSF_CONSTRUCTOR 0x800 - + /* Signal that the symbol is a warning symbol. The name is a warning. The name of the next symbol is the one to warn about; if a reference is made to a symbol with the same name as the next symbol, a warning is issued by the linker. */ #define BSF_WARNING 0x1000 - + /* Signal that the symbol is indirect. This symbol is an indirect pointer to the symbol with the same name as the next symbol. */ #define BSF_INDIRECT 0x2000 - + /* BSF_FILE marks symbols that contain a file name. This is used for ELF STT_FILE symbols. */ #define BSF_FILE 0x4000 - + /* Symbol is from dynamic linking information. */ #define BSF_DYNAMIC 0x8000 - + /* The symbol denotes a data object. Used in ELF, and perhaps others someday. */ #define BSF_OBJECT 0x10000 - + /* This symbol is a debugging symbol. The value is the offset into the section of the data. BSF_DEBUGGING should be set as well. */ #define BSF_DEBUGGING_RELOC 0x20000 - + /* This symbol is thread local. Used in ELF. */ #define BSF_THREAD_LOCAL 0x40000 - + flagword flags; - + /* A pointer to the section to which this symbol is relative. This will always be non NULL, there are special sections for undefined and absolute symbols. */ struct bfd_section *section; - + /* Back end special data. */ union { @@ -2139,13 +2140,13 @@  File: bfd.info, Node: symbol handling functions, Prev: typedef asymbol, Up: Symbols -2.7.5 Symbol handling functions -------------------------------- +Symbol handling functions +------------------------- -2.7.5.1 `bfd_get_symtab_upper_bound' -.................................... +`bfd_get_symtab_upper_bound' +............................ -*Description* + *Description* Return the number of bytes required to store a vector of pointers to `asymbols' for all the symbols in the BFD ABFD, including a terminal NULL pointer. If there are no symbols in the BFD, then return 0. If an @@ -2153,19 +2154,19 @@ #define bfd_get_symtab_upper_bound(abfd) \ BFD_SEND (abfd, _bfd_get_symtab_upper_bound, (abfd)) -2.7.5.2 `bfd_is_local_label' -............................ +`bfd_is_local_label' +.................... -*Synopsis* + *Synopsis* bfd_boolean bfd_is_local_label (bfd *abfd, asymbol *sym); *Description* Return TRUE if the given symbol SYM in the BFD ABFD is a compiler generated local label, else return FALSE. -2.7.5.3 `bfd_is_local_label_name' -................................. +`bfd_is_local_label_name' +......................... -*Synopsis* + *Synopsis* bfd_boolean bfd_is_local_label_name (bfd *abfd, const char *name); *Description* Return TRUE if a symbol with the name NAME in the BFD ABFD is a @@ -2174,10 +2175,10 @@ #define bfd_is_local_label_name(abfd, name) \ BFD_SEND (abfd, _bfd_is_local_label_name, (abfd, name)) -2.7.5.4 `bfd_is_target_special_symbol' -...................................... +`bfd_is_target_special_symbol' +.............................. -*Synopsis* + *Synopsis* bfd_boolean bfd_is_target_special_symbol (bfd *abfd, asymbol *sym); *Description* Return TRUE iff a symbol SYM in the BFD ABFD is something special to @@ -2186,38 +2187,38 @@ #define bfd_is_target_special_symbol(abfd, sym) \ BFD_SEND (abfd, _bfd_is_target_special_symbol, (abfd, sym)) -2.7.5.5 `bfd_canonicalize_symtab' -................................. +`bfd_canonicalize_symtab' +......................... -*Description* + *Description* Read the symbols from the BFD ABFD, and fills in the vector LOCATION with pointers to the symbols and a trailing NULL. Return the actual number of symbol pointers, not including the NULL. #define bfd_canonicalize_symtab(abfd, location) \ BFD_SEND (abfd, _bfd_canonicalize_symtab, (abfd, location)) -2.7.5.6 `bfd_set_symtab' -........................ +`bfd_set_symtab' +................ -*Synopsis* + *Synopsis* bfd_boolean bfd_set_symtab (bfd *abfd, asymbol **location, unsigned int count); *Description* Arrange that when the output BFD ABFD is closed, the table LOCATION of COUNT pointers to symbols will be written. -2.7.5.7 `bfd_print_symbol_vandf' -................................ +`bfd_print_symbol_vandf' +........................ -*Synopsis* + *Synopsis* void bfd_print_symbol_vandf (bfd *abfd, void *file, asymbol *symbol); *Description* Print the value and flags of the SYMBOL supplied to the stream FILE. -2.7.5.8 `bfd_make_empty_symbol' -............................... +`bfd_make_empty_symbol' +....................... -*Description* + *Description* Create a new `asymbol' structure for the BFD ABFD and return a pointer to it. @@ -2228,59 +2229,59 @@ #define bfd_make_empty_symbol(abfd) \ BFD_SEND (abfd, _bfd_make_empty_symbol, (abfd)) -2.7.5.9 `_bfd_generic_make_empty_symbol' -........................................ +`_bfd_generic_make_empty_symbol' +................................ -*Synopsis* + *Synopsis* asymbol *_bfd_generic_make_empty_symbol (bfd *); *Description* Create a new `asymbol' structure for the BFD ABFD and return a pointer to it. Used by core file routines, binary back-end and anywhere else where no private info is needed. -2.7.5.10 `bfd_make_debug_symbol' -................................ +`bfd_make_debug_symbol' +....................... -*Description* + *Description* Create a new `asymbol' structure for the BFD ABFD, to be used as a debugging symbol. Further details of its use have yet to be worked out. #define bfd_make_debug_symbol(abfd,ptr,size) \ BFD_SEND (abfd, _bfd_make_debug_symbol, (abfd, ptr, size)) -2.7.5.11 `bfd_decode_symclass' -.............................. +`bfd_decode_symclass' +..................... -*Description* + *Description* Return a character corresponding to the symbol class of SYMBOL, or '?' for an unknown class. *Synopsis* int bfd_decode_symclass (asymbol *symbol); - -2.7.5.12 `bfd_is_undefined_symclass' -.................................... -*Description* +`bfd_is_undefined_symclass' +........................... + + *Description* Returns non-zero if the class symbol returned by bfd_decode_symclass represents an undefined symbol. Returns zero otherwise. *Synopsis* bfd_boolean bfd_is_undefined_symclass (int symclass); - -2.7.5.13 `bfd_symbol_info' -.......................... -*Description* +`bfd_symbol_info' +................. + + *Description* Fill in the basic info about symbol that nm needs. Additional info may be added by the back-ends after calling this function. *Synopsis* void bfd_symbol_info (asymbol *symbol, symbol_info *ret); - -2.7.5.14 `bfd_copy_private_symbol_data' -....................................... -*Synopsis* +`bfd_copy_private_symbol_data' +.............................. + + *Synopsis* bfd_boolean bfd_copy_private_symbol_data (bfd *ibfd, asymbol *isym, bfd *obfd, asymbol *osym); *Description* @@ -2298,10 +2299,10 @@  File: bfd.info, Node: Archives, Next: Formats, Prev: Symbols, Up: BFD front end -2.8 Archives -============ +Archives +======== -*Description* + *Description* An archive (or library) is just another BFD. It has a symbol table, although there's not much a user program will do with it. @@ -2344,10 +2345,10 @@ Archives are supported in BFD in `archive.c'. -2.8.0.1 `bfd_get_next_mapent' -............................. +`bfd_get_next_mapent' +..................... -*Synopsis* + *Synopsis* symindex bfd_get_next_mapent (bfd *abfd, symindex previous, carsym **sym); *Description* @@ -2361,19 +2362,19 @@ A `carsym' is a canonical archive symbol. The only user-visible element is its name, a null-terminated string. -2.8.0.2 `bfd_set_archive_head' -.............................. +`bfd_set_archive_head' +...................... -*Synopsis* + *Synopsis* bfd_boolean bfd_set_archive_head (bfd *output, bfd *new_head); *Description* Set the head of the chain of BFDs contained in the archive OUTPUT to NEW_HEAD. -2.8.0.3 `bfd_openr_next_archived_file' -...................................... +`bfd_openr_next_archived_file' +.............................. -*Synopsis* + *Synopsis* bfd *bfd_openr_next_archived_file (bfd *archive, bfd *previous); *Description* Provided a BFD, ARCHIVE, containing an archive and NULL, open an input @@ -2385,11 +2386,11 @@  File: bfd.info, Node: Formats, Next: Relocations, Prev: Archives, Up: BFD front end -2.9 File formats -================ +File formats +============ -A format is a BFD concept of high level file contents type. The formats -supported by BFD are: + A format is a BFD concept of high level file contents type. The +formats supported by BFD are: * `bfd_object' The BFD may contain data, symbols, relocations and debug info. @@ -2400,10 +2401,10 @@ * `bfd_core' The BFD contains the result of an executable core dump. -2.9.0.1 `bfd_check_format' -.......................... +`bfd_check_format' +.................. -*Synopsis* + *Synopsis* bfd_boolean bfd_check_format (bfd *abfd, bfd_format format); *Description* Verify if the file attached to the BFD ABFD is compatible with the @@ -2431,10 +2432,10 @@ * `bfd_error_file_ambiguously_recognized' - more than one backend recognised the file format. -2.9.0.2 `bfd_check_format_matches' -.................................. +`bfd_check_format_matches' +.......................... -*Synopsis* + *Synopsis* bfd_boolean bfd_check_format_matches (bfd *abfd, bfd_format format, char ***matching); *Description* @@ -2447,10 +2448,10 @@ When done with the list that MATCHING points to, the caller should free it. -2.9.0.3 `bfd_set_format' -........................ +`bfd_set_format' +................ -*Synopsis* + *Synopsis* bfd_boolean bfd_set_format (bfd *abfd, bfd_format format); *Description* This function sets the file format of the BFD ABFD to the format @@ -2458,10 +2459,10 @@ requested, the format is invalid, or the BFD is not open for writing, then an error occurs. -2.9.0.4 `bfd_format_string' -........................... +`bfd_format_string' +................... -*Synopsis* + *Synopsis* const char *bfd_format_string (bfd_format format); *Description* Return a pointer to a const string `invalid', `object', `archive', @@ -2470,10 +2471,10 @@  File: bfd.info, Node: Relocations, Next: Core Files, Prev: Formats, Up: BFD front end -2.10 Relocations -================ +Relocations +=========== -BFD maintains relocations in much the same way it maintains symbols: + BFD maintains relocations in much the same way it maintains symbols: they are left alone until required, then read in en-masse and translated into an internal form. A common routine `bfd_perform_relocation' acts upon the canonical form to do the fixup. @@ -2493,35 +2494,35 @@  File: bfd.info, Node: typedef arelent, Next: howto manager, Prev: Relocations, Up: Relocations -2.10.1 typedef arelent ----------------------- +typedef arelent +--------------- -This is the structure of a relocation entry: + This is the structure of a relocation entry: typedef enum bfd_reloc_status { /* No errors detected. */ bfd_reloc_ok, - + /* The relocation was performed, but there was an overflow. */ bfd_reloc_overflow, - + /* The address to relocate was not within the section supplied. */ bfd_reloc_outofrange, - + /* Used by special functions. */ bfd_reloc_continue, - + /* Unsupported relocation size requested. */ bfd_reloc_notsupported, - + /* Unused. */ bfd_reloc_other, - + /* The symbol to relocate against was undefined. */ bfd_reloc_undefined, - + /* The relocation was performed, but may not be ok - presently generated only when linking i960 coff files with i960 b.out symbols. If this type is returned, the error_message argument @@ -2529,22 +2530,22 @@ bfd_reloc_dangerous } bfd_reloc_status_type; - - + + typedef struct reloc_cache_entry { /* A pointer into the canonical table of pointers. */ struct bfd_symbol **sym_ptr_ptr; - + /* offset in section. */ bfd_size_type address; - + /* addend for relocation value. */ bfd_vma addend; - + /* Pointer to how to perform the required relocation. */ reloc_howto_type *howto; - + } arelent; *Description* @@ -2594,7 +2595,7 @@ RELOCATION RECORDS FOR [.text]: offset type value 00000006 32 _foo - + 00000000 4e56 fffc ; linkw fp,#-4 00000004 1039 1234 5678 ; moveb @#12345678,d0 0000000a 49c0 ; extbl d0 @@ -2616,7 +2617,7 @@ offset type value 00000002 HVRT16 _foo+0x12340000 00000006 LVRT16 _foo+0x12340000 - + 00000000 5da05678 ; or.u r13,r0,0x5678 00000004 1c4d5678 ; ld.b r2,r13,0x5678 00000008 f400c001 ; jmp r1 @@ -2645,7 +2646,7 @@ offset type value 00000004 HI22 _foo+0x12345678 00000008 LO10 _foo+0x12345678 - + 00000000 9de3bf90 ; save %sp,-112,%sp 00000004 05000000 ; sethi %hi(_foo+0),%g2 00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 @@ -2660,39 +2661,39 @@ relocations into pointers to the correct structure on input - but it would be possible to create each howto field on demand. -2.10.1.1 `enum complain_overflow' -................................. +`enum complain_overflow' +........................ -Indicates what sort of overflow checking should be done when performing -a relocation. + Indicates what sort of overflow checking should be done when +performing a relocation. enum complain_overflow { /* Do not complain on overflow. */ complain_overflow_dont, - + /* Complain if the bitfield overflows, whether it is considered as signed or unsigned. */ complain_overflow_bitfield, - + /* Complain if the value overflows when considered as signed number. */ complain_overflow_signed, - + /* Complain if the value overflows when considered as an unsigned number. */ complain_overflow_unsigned }; -2.10.1.2 `reloc_howto_type' -........................... +`reloc_howto_type' +.................. -The `reloc_howto_type' is a structure which contains all the + The `reloc_howto_type' is a structure which contains all the information that libbfd needs to know to tie up a back end's data. struct bfd_symbol; /* Forward declaration. */ - + struct reloc_howto_struct { /* The type field has mainly a documentary use - the back end can @@ -2702,34 +2703,34 @@ in a coff environment has the type 023 - because that's what the outside world calls a R_PCRWORD reloc. */ unsigned int type; - + /* The value the final relocation is shifted right by. This drops unwanted data from the relocation. */ unsigned int rightshift; - + /* The size of the item to be relocated. This is *not* a power-of-two measure. To get the number of bytes operated on by a type of relocation, use bfd_get_reloc_size. */ int size; - + /* The number of bits in the item to be relocated. This is used when doing overflow checking. */ unsigned int bitsize; - + /* Notes that the relocation is relative to the location in the data section of the addend. The relocation function will subtract from the relocation value the address of the location being relocated. */ bfd_boolean pc_relative; - + /* The bit position of the reloc value in the destination. The relocated value is left shifted by this amount. */ unsigned int bitpos; - + /* What type of overflow error should be checked for when relocating. */ enum complain_overflow complain_on_overflow; - + /* If this field is non null, then the supplied function is called rather than the normal function. This allows really strange relocation methods to be accommodated (e.g., i960 callj @@ -2737,10 +2738,10 @@ bfd_reloc_status_type (*special_function) (bfd *, arelent *, struct bfd_symbol *, void *, asection *, bfd *, char **); - + /* The textual name of the relocation type. */ char *name; - + /* Some formats record a relocation addend in the section contents rather than with the relocation. For ELF formats this is the distinction between USE_REL and USE_RELA (though the code checks @@ -2757,7 +2758,7 @@ to each particular target. For relocs that aren't used in partial links (e.g. GOT stuff) it doesn't matter what this is set to. */ bfd_boolean partial_inplace; - + /* src_mask selects the part of the instruction (or data) to be used in the relocation sum. If the target relocations don't have an addend in the reloc, eg. ELF USE_REL, src_mask will normally equal @@ -2767,11 +2768,11 @@ bogus as in those cases the value in the dst_mask part of the section contents should be treated as garbage. */ bfd_vma src_mask; - + /* dst_mask selects which parts of the instruction (or data) are replaced with a relocated value. */ bfd_vma dst_mask; - + /* When some formats create PC relative instructions, they leave the value of the pc of the place being relocated in the offset slot of the instruction, so that a PC relative relocation can @@ -2780,11 +2781,11 @@ empty (e.g., m88k bcs); this flag signals the fact. */ bfd_boolean pcrel_offset; }; - -2.10.1.3 `The HOWTO Macro' -.......................... -*Description* +`The HOWTO Macro' +................. + + *Description* The HOWTO define is horrible and will go away. #define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC } @@ -2819,19 +2820,19 @@ } \ } -2.10.1.4 `bfd_get_reloc_size' -............................. +`bfd_get_reloc_size' +.................... -*Synopsis* + *Synopsis* unsigned int bfd_get_reloc_size (reloc_howto_type *); *Description* For a reloc_howto_type that operates on a fixed number of bytes, this returns the number of bytes operated on. -2.10.1.5 `arelent_chain' -........................ +`arelent_chain' +............... -*Description* + *Description* How relocs are tied together in an `asection': typedef struct relent_chain { @@ -2840,10 +2841,10 @@ } arelent_chain; -2.10.1.6 `bfd_check_overflow' -............................. +`bfd_check_overflow' +.................... -*Synopsis* + *Synopsis* bfd_reloc_status_type bfd_check_overflow (enum complain_overflow how, unsigned int bitsize, @@ -2856,10 +2857,10 @@ addresses containing ADDRSIZE significant bits. The result is either of `bfd_reloc_ok' or `bfd_reloc_overflow'. -2.10.1.7 `bfd_perform_relocation' -................................. +`bfd_perform_relocation' +........................ -*Synopsis* + *Synopsis* bfd_reloc_status_type bfd_perform_relocation (bfd *abfd, arelent *reloc_entry, @@ -2881,10 +2882,10 @@ ERROR_MESSAGE argument is set to an error message if this return `bfd_reloc_dangerous'. -2.10.1.8 `bfd_install_relocation' -................................. +`bfd_install_relocation' +........................ -*Synopsis* + *Synopsis* bfd_reloc_status_type bfd_install_relocation (bfd *abfd, arelent *reloc_entry, @@ -2902,17 +2903,17 @@  File: bfd.info, Node: howto manager, Prev: typedef arelent, Up: Relocations -2.11 The howto manager -====================== +The howto manager +================= -When an application wants to create a relocation, but doesn't know what -the target machine might call it, it can find out by using this bit of -code. + When an application wants to create a relocation, but doesn't know +what the target machine might call it, it can find out by using this +bit of code. -2.11.0.1 `bfd_reloc_code_type' -.............................. +`bfd_reloc_code_type' +..................... -*Description* + *Description* The insides of a reloc code. The idea is that, eventually, there will be one enumerator for every type of relocation we ever do. Pass one of these values to `bfd_reloc_type_lookup', and it'll return a howto @@ -2924,21 +2925,21 @@ Here are the possible values for `enum bfd_reloc_code_real': - -- : BFD_RELOC_64 - -- : BFD_RELOC_32 - -- : BFD_RELOC_26 - -- : BFD_RELOC_24 - -- : BFD_RELOC_16 - -- : BFD_RELOC_14 - -- : BFD_RELOC_8 + - : BFD_RELOC_64 + - : BFD_RELOC_32 + - : BFD_RELOC_26 + - : BFD_RELOC_24 + - : BFD_RELOC_16 + - : BFD_RELOC_14 + - : BFD_RELOC_8 Basic absolute relocations of N bits. - -- : BFD_RELOC_64_PCREL - -- : BFD_RELOC_32_PCREL - -- : BFD_RELOC_24_PCREL - -- : BFD_RELOC_16_PCREL - -- : BFD_RELOC_12_PCREL - -- : BFD_RELOC_8_PCREL + - : BFD_RELOC_64_PCREL + - : BFD_RELOC_32_PCREL + - : BFD_RELOC_24_PCREL + - : BFD_RELOC_16_PCREL + - : BFD_RELOC_12_PCREL + - : BFD_RELOC_8_PCREL PC-relative relocations. Sometimes these are relative to the address of the relocation itself; sometimes they are relative to the start of the section containing the relocation. It depends on @@ -2946,52 +2947,52 @@ The 24-bit relocation is used in some Intel 960 configurations. - -- : BFD_RELOC_32_SECREL + - : BFD_RELOC_32_SECREL Section relative relocations. Some targets need this for DWARF2. - -- : BFD_RELOC_32_GOT_PCREL - -- : BFD_RELOC_16_GOT_PCREL - -- : BFD_RELOC_8_GOT_PCREL - -- : BFD_RELOC_32_GOTOFF - -- : BFD_RELOC_16_GOTOFF - -- : BFD_RELOC_LO16_GOTOFF - -- : BFD_RELOC_HI16_GOTOFF - -- : BFD_RELOC_HI16_S_GOTOFF - -- : BFD_RELOC_8_GOTOFF - -- : BFD_RELOC_64_PLT_PCREL - -- : BFD_RELOC_32_PLT_PCREL - -- : BFD_RELOC_24_PLT_PCREL - -- : BFD_RELOC_16_PLT_PCREL - -- : BFD_RELOC_8_PLT_PCREL - -- : BFD_RELOC_64_PLTOFF - -- : BFD_RELOC_32_PLTOFF - -- : BFD_RELOC_16_PLTOFF - -- : BFD_RELOC_LO16_PLTOFF - -- : BFD_RELOC_HI16_PLTOFF - -- : BFD_RELOC_HI16_S_PLTOFF - -- : BFD_RELOC_8_PLTOFF + - : BFD_RELOC_32_GOT_PCREL + - : BFD_RELOC_16_GOT_PCREL + - : BFD_RELOC_8_GOT_PCREL + - : BFD_RELOC_32_GOTOFF + - : BFD_RELOC_16_GOTOFF + - : BFD_RELOC_LO16_GOTOFF + - : BFD_RELOC_HI16_GOTOFF + - : BFD_RELOC_HI16_S_GOTOFF + - : BFD_RELOC_8_GOTOFF + - : BFD_RELOC_64_PLT_PCREL + - : BFD_RELOC_32_PLT_PCREL + - : BFD_RELOC_24_PLT_PCREL + - : BFD_RELOC_16_PLT_PCREL + - : BFD_RELOC_8_PLT_PCREL + - : BFD_RELOC_64_PLTOFF + - : BFD_RELOC_32_PLTOFF + - : BFD_RELOC_16_PLTOFF + - : BFD_RELOC_LO16_PLTOFF + - : BFD_RELOC_HI16_PLTOFF + - : BFD_RELOC_HI16_S_PLTOFF + - : BFD_RELOC_8_PLTOFF For ELF. - -- : BFD_RELOC_68K_GLOB_DAT - -- : BFD_RELOC_68K_JMP_SLOT - -- : BFD_RELOC_68K_RELATIVE + - : BFD_RELOC_68K_GLOB_DAT + - : BFD_RELOC_68K_JMP_SLOT + - : BFD_RELOC_68K_RELATIVE Relocations used by 68K ELF. - -- : BFD_RELOC_32_BASEREL - -- : BFD_RELOC_16_BASEREL - -- : BFD_RELOC_LO16_BASEREL - -- : BFD_RELOC_HI16_BASEREL - -- : BFD_RELOC_HI16_S_BASEREL - -- : BFD_RELOC_8_BASEREL - -- : BFD_RELOC_RVA + - : BFD_RELOC_32_BASEREL + - : BFD_RELOC_16_BASEREL + - : BFD_RELOC_LO16_BASEREL + - : BFD_RELOC_HI16_BASEREL + - : BFD_RELOC_HI16_S_BASEREL + - : BFD_RELOC_8_BASEREL + - : BFD_RELOC_RVA Linkage-table relative. - -- : BFD_RELOC_8_FFnn + - : BFD_RELOC_8_FFnn Absolute 8-bit relocation, but used to form an address like 0xFFnn. - -- : BFD_RELOC_32_PCREL_S2 - -- : BFD_RELOC_16_PCREL_S2 - -- : BFD_RELOC_23_PCREL_S2 + - : BFD_RELOC_32_PCREL_S2 + - : BFD_RELOC_16_PCREL_S2 + - : BFD_RELOC_23_PCREL_S2 These PC-relative relocations are stored as word displacements - i.e., byte displacements shifted right two bits. The 30-bit word displacement (<<32_PCREL_S2>> - 32 bits, shifted 2) is used on the @@ -2999,101 +3000,101 @@ signed 16-bit displacement is used on the MIPS, and the 23-bit displacement is used on the Alpha. - -- : BFD_RELOC_HI22 - -- : BFD_RELOC_LO10 + - : BFD_RELOC_HI22 + - : BFD_RELOC_LO10 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of the target word. These are used on the SPARC. - -- : BFD_RELOC_GPREL16 - -- : BFD_RELOC_GPREL32 + - : BFD_RELOC_GPREL16 + - : BFD_RELOC_GPREL32 For systems that allocate a Global Pointer register, these are displacements off that register. These relocation types are handled specially, because the value the register will have is decided relatively late. - -- : BFD_RELOC_I960_CALLJ + - : BFD_RELOC_I960_CALLJ Reloc types used for i960/b.out. - -- : BFD_RELOC_NONE - -- : BFD_RELOC_SPARC_WDISP22 - -- : BFD_RELOC_SPARC22 - -- : BFD_RELOC_SPARC13 - -- : BFD_RELOC_SPARC_GOT10 - -- : BFD_RELOC_SPARC_GOT13 - -- : BFD_RELOC_SPARC_GOT22 - -- : BFD_RELOC_SPARC_PC10 - -- : BFD_RELOC_SPARC_PC22 - -- : BFD_RELOC_SPARC_WPLT30 - -- : BFD_RELOC_SPARC_COPY - -- : BFD_RELOC_SPARC_GLOB_DAT - -- : BFD_RELOC_SPARC_JMP_SLOT - -- : BFD_RELOC_SPARC_RELATIVE - -- : BFD_RELOC_SPARC_UA16 - -- : BFD_RELOC_SPARC_UA32 - -- : BFD_RELOC_SPARC_UA64 + - : BFD_RELOC_NONE + - : BFD_RELOC_SPARC_WDISP22 + - : BFD_RELOC_SPARC22 + - : BFD_RELOC_SPARC13 + - : BFD_RELOC_SPARC_GOT10 + - : BFD_RELOC_SPARC_GOT13 + - : BFD_RELOC_SPARC_GOT22 + - : BFD_RELOC_SPARC_PC10 + - : BFD_RELOC_SPARC_PC22 + - : BFD_RELOC_SPARC_WPLT30 + - : BFD_RELOC_SPARC_COPY + - : BFD_RELOC_SPARC_GLOB_DAT + - : BFD_RELOC_SPARC_JMP_SLOT + - : BFD_RELOC_SPARC_RELATIVE + - : BFD_RELOC_SPARC_UA16 + - : BFD_RELOC_SPARC_UA32 + - : BFD_RELOC_SPARC_UA64 SPARC ELF relocations. There is probably some overlap with other relocation types already defined. - -- : BFD_RELOC_SPARC_BASE13 - -- : BFD_RELOC_SPARC_BASE22 + - : BFD_RELOC_SPARC_BASE13 + - : BFD_RELOC_SPARC_BASE22 I think these are specific to SPARC a.out (e.g., Sun 4). - -- : BFD_RELOC_SPARC_64 - -- : BFD_RELOC_SPARC_10 - -- : BFD_RELOC_SPARC_11 - -- : BFD_RELOC_SPARC_OLO10 - -- : BFD_RELOC_SPARC_HH22 - -- : BFD_RELOC_SPARC_HM10 - -- : BFD_RELOC_SPARC_LM22 - -- : BFD_RELOC_SPARC_PC_HH22 - -- : BFD_RELOC_SPARC_PC_HM10 - -- : BFD_RELOC_SPARC_PC_LM22 - -- : BFD_RELOC_SPARC_WDISP16 - -- : BFD_RELOC_SPARC_WDISP19 - -- : BFD_RELOC_SPARC_7 - -- : BFD_RELOC_SPARC_6 - -- : BFD_RELOC_SPARC_5 - -- : BFD_RELOC_SPARC_DISP64 - -- : BFD_RELOC_SPARC_PLT32 - -- : BFD_RELOC_SPARC_PLT64 - -- : BFD_RELOC_SPARC_HIX22 - -- : BFD_RELOC_SPARC_LOX10 - -- : BFD_RELOC_SPARC_H44 - -- : BFD_RELOC_SPARC_M44 - -- : BFD_RELOC_SPARC_L44 - -- : BFD_RELOC_SPARC_REGISTER + - : BFD_RELOC_SPARC_64 + - : BFD_RELOC_SPARC_10 + - : BFD_RELOC_SPARC_11 + - : BFD_RELOC_SPARC_OLO10 + - : BFD_RELOC_SPARC_HH22 + - : BFD_RELOC_SPARC_HM10 + - : BFD_RELOC_SPARC_LM22 + - : BFD_RELOC_SPARC_PC_HH22 + - : BFD_RELOC_SPARC_PC_HM10 + - : BFD_RELOC_SPARC_PC_LM22 + - : BFD_RELOC_SPARC_WDISP16 + - : BFD_RELOC_SPARC_WDISP19 + - : BFD_RELOC_SPARC_7 + - : BFD_RELOC_SPARC_6 + - : BFD_RELOC_SPARC_5 + - : BFD_RELOC_SPARC_DISP64 + - : BFD_RELOC_SPARC_PLT32 + - : BFD_RELOC_SPARC_PLT64 + - : BFD_RELOC_SPARC_HIX22 + - : BFD_RELOC_SPARC_LOX10 + - : BFD_RELOC_SPARC_H44 + - : BFD_RELOC_SPARC_M44 + - : BFD_RELOC_SPARC_L44 + - : BFD_RELOC_SPARC_REGISTER SPARC64 relocations - -- : BFD_RELOC_SPARC_REV32 + - : BFD_RELOC_SPARC_REV32 SPARC little endian relocation - -- : BFD_RELOC_SPARC_TLS_GD_HI22 - -- : BFD_RELOC_SPARC_TLS_GD_LO10 - -- : BFD_RELOC_SPARC_TLS_GD_ADD - -- : BFD_RELOC_SPARC_TLS_GD_CALL - -- : BFD_RELOC_SPARC_TLS_LDM_HI22 - -- : BFD_RELOC_SPARC_TLS_LDM_LO10 - -- : BFD_RELOC_SPARC_TLS_LDM_ADD - -- : BFD_RELOC_SPARC_TLS_LDM_CALL - -- : BFD_RELOC_SPARC_TLS_LDO_HIX22 - -- : BFD_RELOC_SPARC_TLS_LDO_LOX10 - -- : BFD_RELOC_SPARC_TLS_LDO_ADD - -- : BFD_RELOC_SPARC_TLS_IE_HI22 - -- : BFD_RELOC_SPARC_TLS_IE_LO10 - -- : BFD_RELOC_SPARC_TLS_IE_LD - -- : BFD_RELOC_SPARC_TLS_IE_LDX - -- : BFD_RELOC_SPARC_TLS_IE_ADD - -- : BFD_RELOC_SPARC_TLS_LE_HIX22 - -- : BFD_RELOC_SPARC_TLS_LE_LOX10 - -- : BFD_RELOC_SPARC_TLS_DTPMOD32 - -- : BFD_RELOC_SPARC_TLS_DTPMOD64 - -- : BFD_RELOC_SPARC_TLS_DTPOFF32 - -- : BFD_RELOC_SPARC_TLS_DTPOFF64 - -- : BFD_RELOC_SPARC_TLS_TPOFF32 - -- : BFD_RELOC_SPARC_TLS_TPOFF64 + - : BFD_RELOC_SPARC_TLS_GD_HI22 + - : BFD_RELOC_SPARC_TLS_GD_LO10 + - : BFD_RELOC_SPARC_TLS_GD_ADD + - : BFD_RELOC_SPARC_TLS_GD_CALL + - : BFD_RELOC_SPARC_TLS_LDM_HI22 + - : BFD_RELOC_SPARC_TLS_LDM_LO10 + - : BFD_RELOC_SPARC_TLS_LDM_ADD + - : BFD_RELOC_SPARC_TLS_LDM_CALL + - : BFD_RELOC_SPARC_TLS_LDO_HIX22 + - : BFD_RELOC_SPARC_TLS_LDO_LOX10 + - : BFD_RELOC_SPARC_TLS_LDO_ADD + - : BFD_RELOC_SPARC_TLS_IE_HI22 + - : BFD_RELOC_SPARC_TLS_IE_LO10 + - : BFD_RELOC_SPARC_TLS_IE_LD + - : BFD_RELOC_SPARC_TLS_IE_LDX + - : BFD_RELOC_SPARC_TLS_IE_ADD + - : BFD_RELOC_SPARC_TLS_LE_HIX22 + - : BFD_RELOC_SPARC_TLS_LE_LOX10 + - : BFD_RELOC_SPARC_TLS_DTPMOD32 + - : BFD_RELOC_SPARC_TLS_DTPMOD64 + - : BFD_RELOC_SPARC_TLS_DTPOFF32 + - : BFD_RELOC_SPARC_TLS_DTPOFF64 + - : BFD_RELOC_SPARC_TLS_TPOFF32 + - : BFD_RELOC_SPARC_TLS_TPOFF64 SPARC TLS relocations - -- : BFD_RELOC_ALPHA_GPDISP_HI16 + - : BFD_RELOC_ALPHA_GPDISP_HI16 Alpha ECOFF and ELF relocations. Some of these treat the symbol or "addend" in some special way. For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when writing; when reading, it @@ -3101,20 +3102,20 @@ displacement in bytes of the "lda" instruction from the "ldah" instruction (which is at the address of this reloc). - -- : BFD_RELOC_ALPHA_GPDISP_LO16 + - : BFD_RELOC_ALPHA_GPDISP_LO16 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as with GPDISP_HI16 relocs. The addend is ignored when writing the relocations out, and is filled in with the file's GP value on reading, for convenience. - -- : BFD_RELOC_ALPHA_GPDISP + - : BFD_RELOC_ALPHA_GPDISP The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 relocation except that there is no accompanying GPDISP_LO16 relocation. - -- : BFD_RELOC_ALPHA_LITERAL - -- : BFD_RELOC_ALPHA_ELF_LITERAL - -- : BFD_RELOC_ALPHA_LITUSE + - : BFD_RELOC_ALPHA_LITERAL + - : BFD_RELOC_ALPHA_ELF_LITERAL + - : BFD_RELOC_ALPHA_LITUSE The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; the assembler turns it into a LDQ instruction to load the address of the symbol, and then fills in a register in the real @@ -3139,1062 +3140,1062 @@ fmt insn 2 - byte-manipulation (byte offset reg) 3 - jsr (target of branch) - -- : BFD_RELOC_ALPHA_HINT + - : BFD_RELOC_ALPHA_HINT The HINT relocation indicates a value that should be filled into the "hint" field of a jmp/jsr/ret instruction, for possible branch- prediction logic which may be provided on some processors. - -- : BFD_RELOC_ALPHA_LINKAGE + - : BFD_RELOC_ALPHA_LINKAGE The LINKAGE relocation outputs a linkage pair in the object file, which is filled by the linker. - -- : BFD_RELOC_ALPHA_CODEADDR + - : BFD_RELOC_ALPHA_CODEADDR The CODEADDR relocation outputs a STO_CA in the object file, which is filled by the linker. - -- : BFD_RELOC_ALPHA_GPREL_HI16 - -- : BFD_RELOC_ALPHA_GPREL_LO16 + - : BFD_RELOC_ALPHA_GPREL_HI16 + - : BFD_RELOC_ALPHA_GPREL_LO16 The GPREL_HI/LO relocations together form a 32-bit offset from the GP register. - -- : BFD_RELOC_ALPHA_BRSGP + - : BFD_RELOC_ALPHA_BRSGP Like BFD_RELOC_23_PCREL_S2, except that the source and target must share a common GP, and the target address is adjusted for STO_ALPHA_STD_GPLOAD. - -- : BFD_RELOC_ALPHA_TLSGD - -- : BFD_RELOC_ALPHA_TLSLDM - -- : BFD_RELOC_ALPHA_DTPMOD64 - -- : BFD_RELOC_ALPHA_GOTDTPREL16 - -- : BFD_RELOC_ALPHA_DTPREL64 - -- : BFD_RELOC_ALPHA_DTPREL_HI16 - -- : BFD_RELOC_ALPHA_DTPREL_LO16 - -- : BFD_RELOC_ALPHA_DTPREL16 - -- : BFD_RELOC_ALPHA_GOTTPREL16 - -- : BFD_RELOC_ALPHA_TPREL64 - -- : BFD_RELOC_ALPHA_TPREL_HI16 - -- : BFD_RELOC_ALPHA_TPREL_LO16 - -- : BFD_RELOC_ALPHA_TPREL16 + - : BFD_RELOC_ALPHA_TLSGD + - : BFD_RELOC_ALPHA_TLSLDM + - : BFD_RELOC_ALPHA_DTPMOD64 + - : BFD_RELOC_ALPHA_GOTDTPREL16 + - : BFD_RELOC_ALPHA_DTPREL64 + - : BFD_RELOC_ALPHA_DTPREL_HI16 + - : BFD_RELOC_ALPHA_DTPREL_LO16 + - : BFD_RELOC_ALPHA_DTPREL16 + - : BFD_RELOC_ALPHA_GOTTPREL16 + - : BFD_RELOC_ALPHA_TPREL64 + - : BFD_RELOC_ALPHA_TPREL_HI16 + - : BFD_RELOC_ALPHA_TPREL_LO16 + - : BFD_RELOC_ALPHA_TPREL16 Alpha thread-local storage relocations. - -- : BFD_RELOC_MIPS_JMP + - : BFD_RELOC_MIPS_JMP Bits 27..2 of the relocation address shifted right 2 bits; simple reloc otherwise. - -- : BFD_RELOC_MIPS16_JMP + - : BFD_RELOC_MIPS16_JMP The MIPS16 jump instruction. - -- : BFD_RELOC_MIPS16_GPREL + - : BFD_RELOC_MIPS16_GPREL MIPS16 GP relative reloc. - -- : BFD_RELOC_HI16 + - : BFD_RELOC_HI16 High 16 bits of 32-bit value; simple reloc. - -- : BFD_RELOC_HI16_S + - : BFD_RELOC_HI16_S High 16 bits of 32-bit value but the low 16 bits will be sign extended and added to form the final result. If the low 16 bits form a negative number, we need to add one to the high value to compensate for the borrow when the low bits are added. - -- : BFD_RELOC_LO16 + - : BFD_RELOC_LO16 Low 16 bits. - -- : BFD_RELOC_MIPS16_HI16 + - : BFD_RELOC_MIPS16_HI16 MIPS16 high 16 bits of 32-bit value. - -- : BFD_RELOC_MIPS16_HI16_S + - : BFD_RELOC_MIPS16_HI16_S MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign extended and added to form the final result. If the low 16 bits form a negative number, we need to add one to the high value to compensate for the borrow when the low bits are added. - -- : BFD_RELOC_MIPS16_LO16 + - : BFD_RELOC_MIPS16_LO16 MIPS16 low 16 bits. - -- : BFD_RELOC_MIPS_LITERAL + - : BFD_RELOC_MIPS_LITERAL Relocation against a MIPS literal section. - -- : BFD_RELOC_MIPS_GOT16 - -- : BFD_RELOC_MIPS_CALL16 - -- : BFD_RELOC_MIPS_GOT_HI16 - -- : BFD_RELOC_MIPS_GOT_LO16 - -- : BFD_RELOC_MIPS_CALL_HI16 - -- : BFD_RELOC_MIPS_CALL_LO16 - -- : BFD_RELOC_MIPS_SUB - -- : BFD_RELOC_MIPS_GOT_PAGE - -- : BFD_RELOC_MIPS_GOT_OFST - -- : BFD_RELOC_MIPS_GOT_DISP - -- : BFD_RELOC_MIPS_SHIFT5 - -- : BFD_RELOC_MIPS_SHIFT6 - -- : BFD_RELOC_MIPS_INSERT_A - -- : BFD_RELOC_MIPS_INSERT_B - -- : BFD_RELOC_MIPS_DELETE - -- : BFD_RELOC_MIPS_HIGHEST - -- : BFD_RELOC_MIPS_HIGHER - -- : BFD_RELOC_MIPS_SCN_DISP - -- : BFD_RELOC_MIPS_REL16 - -- : BFD_RELOC_MIPS_RELGOT - -- : BFD_RELOC_MIPS_JALR - -- : BFD_RELOC_MIPS_TLS_DTPMOD32 - -- : BFD_RELOC_MIPS_TLS_DTPREL32 - -- : BFD_RELOC_MIPS_TLS_DTPMOD64 - -- : BFD_RELOC_MIPS_TLS_DTPREL64 - -- : BFD_RELOC_MIPS_TLS_GD - -- : BFD_RELOC_MIPS_TLS_LDM - -- : BFD_RELOC_MIPS_TLS_DTPREL_HI16 - -- : BFD_RELOC_MIPS_TLS_DTPREL_LO16 - -- : BFD_RELOC_MIPS_TLS_GOTTPREL - -- : BFD_RELOC_MIPS_TLS_TPREL32 - -- : BFD_RELOC_MIPS_TLS_TPREL64 - -- : BFD_RELOC_MIPS_TLS_TPREL_HI16 - -- : BFD_RELOC_MIPS_TLS_TPREL_LO16 + - : BFD_RELOC_MIPS_GOT16 + - : BFD_RELOC_MIPS_CALL16 + - : BFD_RELOC_MIPS_GOT_HI16 + - : BFD_RELOC_MIPS_GOT_LO16 + - : BFD_RELOC_MIPS_CALL_HI16 + - : BFD_RELOC_MIPS_CALL_LO16 + - : BFD_RELOC_MIPS_SUB + - : BFD_RELOC_MIPS_GOT_PAGE + - : BFD_RELOC_MIPS_GOT_OFST + - : BFD_RELOC_MIPS_GOT_DISP + - : BFD_RELOC_MIPS_SHIFT5 + - : BFD_RELOC_MIPS_SHIFT6 + - : BFD_RELOC_MIPS_INSERT_A + - : BFD_RELOC_MIPS_INSERT_B + - : BFD_RELOC_MIPS_DELETE + - : BFD_RELOC_MIPS_HIGHEST + - : BFD_RELOC_MIPS_HIGHER + - : BFD_RELOC_MIPS_SCN_DISP + - : BFD_RELOC_MIPS_REL16 + - : BFD_RELOC_MIPS_RELGOT + - : BFD_RELOC_MIPS_JALR + - : BFD_RELOC_MIPS_TLS_DTPMOD32 + - : BFD_RELOC_MIPS_TLS_DTPREL32 + - : BFD_RELOC_MIPS_TLS_DTPMOD64 + - : BFD_RELOC_MIPS_TLS_DTPREL64 + - : BFD_RELOC_MIPS_TLS_GD + - : BFD_RELOC_MIPS_TLS_LDM + - : BFD_RELOC_MIPS_TLS_DTPREL_HI16 + - : BFD_RELOC_MIPS_TLS_DTPREL_LO16 + - : BFD_RELOC_MIPS_TLS_GOTTPREL + - : BFD_RELOC_MIPS_TLS_TPREL32 + - : BFD_RELOC_MIPS_TLS_TPREL64 + - : BFD_RELOC_MIPS_TLS_TPREL_HI16 + - : BFD_RELOC_MIPS_TLS_TPREL_LO16 MIPS ELF relocations. - -- : BFD_RELOC_FRV_LABEL16 - -- : BFD_RELOC_FRV_LABEL24 - -- : BFD_RELOC_FRV_LO16 - -- : BFD_RELOC_FRV_HI16 - -- : BFD_RELOC_FRV_GPREL12 - -- : BFD_RELOC_FRV_GPRELU12 - -- : BFD_RELOC_FRV_GPREL32 - -- : BFD_RELOC_FRV_GPRELHI - -- : BFD_RELOC_FRV_GPRELLO - -- : BFD_RELOC_FRV_GOT12 - -- : BFD_RELOC_FRV_GOTHI - -- : BFD_RELOC_FRV_GOTLO - -- : BFD_RELOC_FRV_FUNCDESC - -- : BFD_RELOC_FRV_FUNCDESC_GOT12 - -- : BFD_RELOC_FRV_FUNCDESC_GOTHI - -- : BFD_RELOC_FRV_FUNCDESC_GOTLO - -- : BFD_RELOC_FRV_FUNCDESC_VALUE - -- : BFD_RELOC_FRV_FUNCDESC_GOTOFF12 - -- : BFD_RELOC_FRV_FUNCDESC_GOTOFFHI - -- : BFD_RELOC_FRV_FUNCDESC_GOTOFFLO - -- : BFD_RELOC_FRV_GOTOFF12 - -- : BFD_RELOC_FRV_GOTOFFHI - -- : BFD_RELOC_FRV_GOTOFFLO - -- : BFD_RELOC_FRV_GETTLSOFF - -- : BFD_RELOC_FRV_TLSDESC_VALUE - -- : BFD_RELOC_FRV_GOTTLSDESC12 - -- : BFD_RELOC_FRV_GOTTLSDESCHI - -- : BFD_RELOC_FRV_GOTTLSDESCLO - -- : BFD_RELOC_FRV_TLSMOFF12 - -- : BFD_RELOC_FRV_TLSMOFFHI - -- : BFD_RELOC_FRV_TLSMOFFLO - -- : BFD_RELOC_FRV_GOTTLSOFF12 - -- : BFD_RELOC_FRV_GOTTLSOFFHI - -- : BFD_RELOC_FRV_GOTTLSOFFLO - -- : BFD_RELOC_FRV_TLSOFF - -- : BFD_RELOC_FRV_TLSDESC_RELAX - -- : BFD_RELOC_FRV_GETTLSOFF_RELAX - -- : BFD_RELOC_FRV_TLSOFF_RELAX - -- : BFD_RELOC_FRV_TLSMOFF + - : BFD_RELOC_FRV_LABEL16 + - : BFD_RELOC_FRV_LABEL24 + - : BFD_RELOC_FRV_LO16 + - : BFD_RELOC_FRV_HI16 + - : BFD_RELOC_FRV_GPREL12 + - : BFD_RELOC_FRV_GPRELU12 + - : BFD_RELOC_FRV_GPREL32 + - : BFD_RELOC_FRV_GPRELHI + - : BFD_RELOC_FRV_GPRELLO + - : BFD_RELOC_FRV_GOT12 + - : BFD_RELOC_FRV_GOTHI + - : BFD_RELOC_FRV_GOTLO + - : BFD_RELOC_FRV_FUNCDESC + - : BFD_RELOC_FRV_FUNCDESC_GOT12 + - : BFD_RELOC_FRV_FUNCDESC_GOTHI + - : BFD_RELOC_FRV_FUNCDESC_GOTLO + - : BFD_RELOC_FRV_FUNCDESC_VALUE + - : BFD_RELOC_FRV_FUNCDESC_GOTOFF12 + - : BFD_RELOC_FRV_FUNCDESC_GOTOFFHI + - : BFD_RELOC_FRV_FUNCDESC_GOTOFFLO + - : BFD_RELOC_FRV_GOTOFF12 + - : BFD_RELOC_FRV_GOTOFFHI + - : BFD_RELOC_FRV_GOTOFFLO + - : BFD_RELOC_FRV_GETTLSOFF + - : BFD_RELOC_FRV_TLSDESC_VALUE + - : BFD_RELOC_FRV_GOTTLSDESC12 + - : BFD_RELOC_FRV_GOTTLSDESCHI + - : BFD_RELOC_FRV_GOTTLSDESCLO + - : BFD_RELOC_FRV_TLSMOFF12 + - : BFD_RELOC_FRV_TLSMOFFHI + - : BFD_RELOC_FRV_TLSMOFFLO + - : BFD_RELOC_FRV_GOTTLSOFF12 + - : BFD_RELOC_FRV_GOTTLSOFFHI + - : BFD_RELOC_FRV_GOTTLSOFFLO + - : BFD_RELOC_FRV_TLSOFF + - : BFD_RELOC_FRV_TLSDESC_RELAX + - : BFD_RELOC_FRV_GETTLSOFF_RELAX + - : BFD_RELOC_FRV_TLSOFF_RELAX + - : BFD_RELOC_FRV_TLSMOFF Fujitsu Frv Relocations. - -- : BFD_RELOC_MN10300_GOTOFF24 + - : BFD_RELOC_MN10300_GOTOFF24 This is a 24bit GOT-relative reloc for the mn10300. - -- : BFD_RELOC_MN10300_GOT32 + - : BFD_RELOC_MN10300_GOT32 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes in the instruction. - -- : BFD_RELOC_MN10300_GOT24 + - : BFD_RELOC_MN10300_GOT24 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes in the instruction. - -- : BFD_RELOC_MN10300_GOT16 + - : BFD_RELOC_MN10300_GOT16 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes in the instruction. - -- : BFD_RELOC_MN10300_COPY + - : BFD_RELOC_MN10300_COPY Copy symbol at runtime. - -- : BFD_RELOC_MN10300_GLOB_DAT + - : BFD_RELOC_MN10300_GLOB_DAT Create GOT entry. - -- : BFD_RELOC_MN10300_JMP_SLOT + - : BFD_RELOC_MN10300_JMP_SLOT Create PLT entry. - -- : BFD_RELOC_MN10300_RELATIVE + - : BFD_RELOC_MN10300_RELATIVE Adjust by program base. - -- : BFD_RELOC_386_GOT32 - -- : BFD_RELOC_386_PLT32 - -- : BFD_RELOC_386_COPY - -- : BFD_RELOC_386_GLOB_DAT - -- : BFD_RELOC_386_JUMP_SLOT - -- : BFD_RELOC_386_RELATIVE - -- : BFD_RELOC_386_GOTOFF - -- : BFD_RELOC_386_GOTPC - -- : BFD_RELOC_386_TLS_TPOFF - -- : BFD_RELOC_386_TLS_IE - -- : BFD_RELOC_386_TLS_GOTIE - -- : BFD_RELOC_386_TLS_LE - -- : BFD_RELOC_386_TLS_GD - -- : BFD_RELOC_386_TLS_LDM - -- : BFD_RELOC_386_TLS_LDO_32 - -- : BFD_RELOC_386_TLS_IE_32 - -- : BFD_RELOC_386_TLS_LE_32 - -- : BFD_RELOC_386_TLS_DTPMOD32 - -- : BFD_RELOC_386_TLS_DTPOFF32 - -- : BFD_RELOC_386_TLS_TPOFF32 + - : BFD_RELOC_386_GOT32 + - : BFD_RELOC_386_PLT32 + - : BFD_RELOC_386_COPY + - : BFD_RELOC_386_GLOB_DAT + - : BFD_RELOC_386_JUMP_SLOT + - : BFD_RELOC_386_RELATIVE + - : BFD_RELOC_386_GOTOFF + - : BFD_RELOC_386_GOTPC + - : BFD_RELOC_386_TLS_TPOFF + - : BFD_RELOC_386_TLS_IE + - : BFD_RELOC_386_TLS_GOTIE + - : BFD_RELOC_386_TLS_LE + - : BFD_RELOC_386_TLS_GD + - : BFD_RELOC_386_TLS_LDM + - : BFD_RELOC_386_TLS_LDO_32 + - : BFD_RELOC_386_TLS_IE_32 + - : BFD_RELOC_386_TLS_LE_32 + - : BFD_RELOC_386_TLS_DTPMOD32 + - : BFD_RELOC_386_TLS_DTPOFF32 + - : BFD_RELOC_386_TLS_TPOFF32 i386/elf relocations - -- : BFD_RELOC_X86_64_GOT32 - -- : BFD_RELOC_X86_64_PLT32 - -- : BFD_RELOC_X86_64_COPY - -- : BFD_RELOC_X86_64_GLOB_DAT - -- : BFD_RELOC_X86_64_JUMP_SLOT - -- : BFD_RELOC_X86_64_RELATIVE - -- : BFD_RELOC_X86_64_GOTPCREL - -- : BFD_RELOC_X86_64_32S - -- : BFD_RELOC_X86_64_DTPMOD64 - -- : BFD_RELOC_X86_64_DTPOFF64 - -- : BFD_RELOC_X86_64_TPOFF64 - -- : BFD_RELOC_X86_64_TLSGD - -- : BFD_RELOC_X86_64_TLSLD - -- : BFD_RELOC_X86_64_DTPOFF32 - -- : BFD_RELOC_X86_64_GOTTPOFF - -- : BFD_RELOC_X86_64_TPOFF32 + - : BFD_RELOC_X86_64_GOT32 + - : BFD_RELOC_X86_64_PLT32 + - : BFD_RELOC_X86_64_COPY + - : BFD_RELOC_X86_64_GLOB_DAT + - : BFD_RELOC_X86_64_JUMP_SLOT + - : BFD_RELOC_X86_64_RELATIVE + - : BFD_RELOC_X86_64_GOTPCREL + - : BFD_RELOC_X86_64_32S + - : BFD_RELOC_X86_64_DTPMOD64 + - : BFD_RELOC_X86_64_DTPOFF64 + - : BFD_RELOC_X86_64_TPOFF64 + - : BFD_RELOC_X86_64_TLSGD + - : BFD_RELOC_X86_64_TLSLD + - : BFD_RELOC_X86_64_DTPOFF32 + - : BFD_RELOC_X86_64_GOTTPOFF + - : BFD_RELOC_X86_64_TPOFF32 x86-64/elf relocations - -- : BFD_RELOC_NS32K_IMM_8 - -- : BFD_RELOC_NS32K_IMM_16 - -- : BFD_RELOC_NS32K_IMM_32 - -- : BFD_RELOC_NS32K_IMM_8_PCREL - -- : BFD_RELOC_NS32K_IMM_16_PCREL - -- : BFD_RELOC_NS32K_IMM_32_PCREL - -- : BFD_RELOC_NS32K_DISP_8 - -- : BFD_RELOC_NS32K_DISP_16 - -- : BFD_RELOC_NS32K_DISP_32 - -- : BFD_RELOC_NS32K_DISP_8_PCREL - -- : BFD_RELOC_NS32K_DISP_16_PCREL - -- : BFD_RELOC_NS32K_DISP_32_PCREL + - : BFD_RELOC_NS32K_IMM_8 + - : BFD_RELOC_NS32K_IMM_16 + - : BFD_RELOC_NS32K_IMM_32 + - : BFD_RELOC_NS32K_IMM_8_PCREL + - : BFD_RELOC_NS32K_IMM_16_PCREL + - : BFD_RELOC_NS32K_IMM_32_PCREL + - : BFD_RELOC_NS32K_DISP_8 + - : BFD_RELOC_NS32K_DISP_16 + - : BFD_RELOC_NS32K_DISP_32 + - : BFD_RELOC_NS32K_DISP_8_PCREL + - : BFD_RELOC_NS32K_DISP_16_PCREL + - : BFD_RELOC_NS32K_DISP_32_PCREL ns32k relocations - -- : BFD_RELOC_PDP11_DISP_8_PCREL - -- : BFD_RELOC_PDP11_DISP_6_PCREL + - : BFD_RELOC_PDP11_DISP_8_PCREL + - : BFD_RELOC_PDP11_DISP_6_PCREL PDP11 relocations - -- : BFD_RELOC_PJ_CODE_HI16 - -- : BFD_RELOC_PJ_CODE_LO16 - -- : BFD_RELOC_PJ_CODE_DIR16 - -- : BFD_RELOC_PJ_CODE_DIR32 - -- : BFD_RELOC_PJ_CODE_REL16 - -- : BFD_RELOC_PJ_CODE_REL32 + - : BFD_RELOC_PJ_CODE_HI16 + - : BFD_RELOC_PJ_CODE_LO16 + - : BFD_RELOC_PJ_CODE_DIR16 + - : BFD_RELOC_PJ_CODE_DIR32 + - : BFD_RELOC_PJ_CODE_REL16 + - : BFD_RELOC_PJ_CODE_REL32 Picojava relocs. Not all of these appear in object files. - -- : BFD_RELOC_PPC_B26 - -- : BFD_RELOC_PPC_BA26 - -- : BFD_RELOC_PPC_TOC16 - -- : BFD_RELOC_PPC_B16 - -- : BFD_RELOC_PPC_B16_BRTAKEN - -- : BFD_RELOC_PPC_B16_BRNTAKEN - -- : BFD_RELOC_PPC_BA16 - -- : BFD_RELOC_PPC_BA16_BRTAKEN - -- : BFD_RELOC_PPC_BA16_BRNTAKEN - -- : BFD_RELOC_PPC_COPY - -- : BFD_RELOC_PPC_GLOB_DAT - -- : BFD_RELOC_PPC_JMP_SLOT - -- : BFD_RELOC_PPC_RELATIVE - -- : BFD_RELOC_PPC_LOCAL24PC - -- : BFD_RELOC_PPC_EMB_NADDR32 - -- : BFD_RELOC_PPC_EMB_NADDR16 - -- : BFD_RELOC_PPC_EMB_NADDR16_LO - -- : BFD_RELOC_PPC_EMB_NADDR16_HI - -- : BFD_RELOC_PPC_EMB_NADDR16_HA - -- : BFD_RELOC_PPC_EMB_SDAI16 - -- : BFD_RELOC_PPC_EMB_SDA2I16 - -- : BFD_RELOC_PPC_EMB_SDA2REL - -- : BFD_RELOC_PPC_EMB_SDA21 - -- : BFD_RELOC_PPC_EMB_MRKREF - -- : BFD_RELOC_PPC_EMB_RELSEC16 - -- : BFD_RELOC_PPC_EMB_RELST_LO - -- : BFD_RELOC_PPC_EMB_RELST_HI - -- : BFD_RELOC_PPC_EMB_RELST_HA - -- : BFD_RELOC_PPC_EMB_BIT_FLD - -- : BFD_RELOC_PPC_EMB_RELSDA - -- : BFD_RELOC_PPC64_HIGHER - -- : BFD_RELOC_PPC64_HIGHER_S - -- : BFD_RELOC_PPC64_HIGHEST - -- : BFD_RELOC_PPC64_HIGHEST_S - -- : BFD_RELOC_PPC64_TOC16_LO - -- : BFD_RELOC_PPC64_TOC16_HI - -- : BFD_RELOC_PPC64_TOC16_HA - -- : BFD_RELOC_PPC64_TOC - -- : BFD_RELOC_PPC64_PLTGOT16 - -- : BFD_RELOC_PPC64_PLTGOT16_LO - -- : BFD_RELOC_PPC64_PLTGOT16_HI - -- : BFD_RELOC_PPC64_PLTGOT16_HA - -- : BFD_RELOC_PPC64_ADDR16_DS - -- : BFD_RELOC_PPC64_ADDR16_LO_DS - -- : BFD_RELOC_PPC64_GOT16_DS - -- : BFD_RELOC_PPC64_GOT16_LO_DS - -- : BFD_RELOC_PPC64_PLT16_LO_DS - -- : BFD_RELOC_PPC64_SECTOFF_DS - -- : BFD_RELOC_PPC64_SECTOFF_LO_DS - -- : BFD_RELOC_PPC64_TOC16_DS - -- : BFD_RELOC_PPC64_TOC16_LO_DS - -- : BFD_RELOC_PPC64_PLTGOT16_DS - -- : BFD_RELOC_PPC64_PLTGOT16_LO_DS + - : BFD_RELOC_PPC_B26 + - : BFD_RELOC_PPC_BA26 + - : BFD_RELOC_PPC_TOC16 + - : BFD_RELOC_PPC_B16 + - : BFD_RELOC_PPC_B16_BRTAKEN + - : BFD_RELOC_PPC_B16_BRNTAKEN + - : BFD_RELOC_PPC_BA16 + - : BFD_RELOC_PPC_BA16_BRTAKEN + - : BFD_RELOC_PPC_BA16_BRNTAKEN + - : BFD_RELOC_PPC_COPY + - : BFD_RELOC_PPC_GLOB_DAT + - : BFD_RELOC_PPC_JMP_SLOT + - : BFD_RELOC_PPC_RELATIVE + - : BFD_RELOC_PPC_LOCAL24PC + - : BFD_RELOC_PPC_EMB_NADDR32 + - : BFD_RELOC_PPC_EMB_NADDR16 + - : BFD_RELOC_PPC_EMB_NADDR16_LO + - : BFD_RELOC_PPC_EMB_NADDR16_HI + - : BFD_RELOC_PPC_EMB_NADDR16_HA + - : BFD_RELOC_PPC_EMB_SDAI16 + - : BFD_RELOC_PPC_EMB_SDA2I16 + - : BFD_RELOC_PPC_EMB_SDA2REL + - : BFD_RELOC_PPC_EMB_SDA21 + - : BFD_RELOC_PPC_EMB_MRKREF + - : BFD_RELOC_PPC_EMB_RELSEC16 + - : BFD_RELOC_PPC_EMB_RELST_LO + - : BFD_RELOC_PPC_EMB_RELST_HI + - : BFD_RELOC_PPC_EMB_RELST_HA + - : BFD_RELOC_PPC_EMB_BIT_FLD + - : BFD_RELOC_PPC_EMB_RELSDA + - : BFD_RELOC_PPC64_HIGHER + - : BFD_RELOC_PPC64_HIGHER_S + - : BFD_RELOC_PPC64_HIGHEST + - : BFD_RELOC_PPC64_HIGHEST_S + - : BFD_RELOC_PPC64_TOC16_LO + - : BFD_RELOC_PPC64_TOC16_HI + - : BFD_RELOC_PPC64_TOC16_HA + - : BFD_RELOC_PPC64_TOC + - : BFD_RELOC_PPC64_PLTGOT16 + - : BFD_RELOC_PPC64_PLTGOT16_LO + - : BFD_RELOC_PPC64_PLTGOT16_HI + - : BFD_RELOC_PPC64_PLTGOT16_HA + - : BFD_RELOC_PPC64_ADDR16_DS + - : BFD_RELOC_PPC64_ADDR16_LO_DS + - : BFD_RELOC_PPC64_GOT16_DS + - : BFD_RELOC_PPC64_GOT16_LO_DS + - : BFD_RELOC_PPC64_PLT16_LO_DS + - : BFD_RELOC_PPC64_SECTOFF_DS + - : BFD_RELOC_PPC64_SECTOFF_LO_DS + - : BFD_RELOC_PPC64_TOC16_DS + - : BFD_RELOC_PPC64_TOC16_LO_DS + - : BFD_RELOC_PPC64_PLTGOT16_DS + - : BFD_RELOC_PPC64_PLTGOT16_LO_DS Power(rs6000) and PowerPC relocations. - -- : BFD_RELOC_PPC_TLS - -- : BFD_RELOC_PPC_DTPMOD - -- : BFD_RELOC_PPC_TPREL16 - -- : BFD_RELOC_PPC_TPREL16_LO - -- : BFD_RELOC_PPC_TPREL16_HI - -- : BFD_RELOC_PPC_TPREL16_HA - -- : BFD_RELOC_PPC_TPREL - -- : BFD_RELOC_PPC_DTPREL16 - -- : BFD_RELOC_PPC_DTPREL16_LO - -- : BFD_RELOC_PPC_DTPREL16_HI - -- : BFD_RELOC_PPC_DTPREL16_HA - -- : BFD_RELOC_PPC_DTPREL - -- : BFD_RELOC_PPC_GOT_TLSGD16 - -- : BFD_RELOC_PPC_GOT_TLSGD16_LO - -- : BFD_RELOC_PPC_GOT_TLSGD16_HI - -- : BFD_RELOC_PPC_GOT_TLSGD16_HA - -- : BFD_RELOC_PPC_GOT_TLSLD16 - -- : BFD_RELOC_PPC_GOT_TLSLD16_LO - -- : BFD_RELOC_PPC_GOT_TLSLD16_HI - -- : BFD_RELOC_PPC_GOT_TLSLD16_HA - -- : BFD_RELOC_PPC_GOT_TPREL16 - -- : BFD_RELOC_PPC_GOT_TPREL16_LO - -- : BFD_RELOC_PPC_GOT_TPREL16_HI - -- : BFD_RELOC_PPC_GOT_TPREL16_HA - -- : BFD_RELOC_PPC_GOT_DTPREL16 - -- : BFD_RELOC_PPC_GOT_DTPREL16_LO - -- : BFD_RELOC_PPC_GOT_DTPREL16_HI - -- : BFD_RELOC_PPC_GOT_DTPREL16_HA - -- : BFD_RELOC_PPC64_TPREL16_DS - -- : BFD_RELOC_PPC64_TPREL16_LO_DS - -- : BFD_RELOC_PPC64_TPREL16_HIGHER - -- : BFD_RELOC_PPC64_TPREL16_HIGHERA - -- : BFD_RELOC_PPC64_TPREL16_HIGHEST - -- : BFD_RELOC_PPC64_TPREL16_HIGHESTA - -- : BFD_RELOC_PPC64_DTPREL16_DS - -- : BFD_RELOC_PPC64_DTPREL16_LO_DS - -- : BFD_RELOC_PPC64_DTPREL16_HIGHER - -- : BFD_RELOC_PPC64_DTPREL16_HIGHERA - -- : BFD_RELOC_PPC64_DTPREL16_HIGHEST - -- : BFD_RELOC_PPC64_DTPREL16_HIGHESTA + - : BFD_RELOC_PPC_TLS + - : BFD_RELOC_PPC_DTPMOD + - : BFD_RELOC_PPC_TPREL16 + - : BFD_RELOC_PPC_TPREL16_LO + - : BFD_RELOC_PPC_TPREL16_HI + - : BFD_RELOC_PPC_TPREL16_HA + - : BFD_RELOC_PPC_TPREL + - : BFD_RELOC_PPC_DTPREL16 + - : BFD_RELOC_PPC_DTPREL16_LO + - : BFD_RELOC_PPC_DTPREL16_HI + - : BFD_RELOC_PPC_DTPREL16_HA + - : BFD_RELOC_PPC_DTPREL + - : BFD_RELOC_PPC_GOT_TLSGD16 + - : BFD_RELOC_PPC_GOT_TLSGD16_LO + - : BFD_RELOC_PPC_GOT_TLSGD16_HI + - : BFD_RELOC_PPC_GOT_TLSGD16_HA + - : BFD_RELOC_PPC_GOT_TLSLD16 + - : BFD_RELOC_PPC_GOT_TLSLD16_LO + - : BFD_RELOC_PPC_GOT_TLSLD16_HI + - : BFD_RELOC_PPC_GOT_TLSLD16_HA + - : BFD_RELOC_PPC_GOT_TPREL16 + - : BFD_RELOC_PPC_GOT_TPREL16_LO + - : BFD_RELOC_PPC_GOT_TPREL16_HI + - : BFD_RELOC_PPC_GOT_TPREL16_HA + - : BFD_RELOC_PPC_GOT_DTPREL16 + - : BFD_RELOC_PPC_GOT_DTPREL16_LO + - : BFD_RELOC_PPC_GOT_DTPREL16_HI + - : BFD_RELOC_PPC_GOT_DTPREL16_HA + - : BFD_RELOC_PPC64_TPREL16_DS + - : BFD_RELOC_PPC64_TPREL16_LO_DS + - : BFD_RELOC_PPC64_TPREL16_HIGHER + - : BFD_RELOC_PPC64_TPREL16_HIGHERA + - : BFD_RELOC_PPC64_TPREL16_HIGHEST + - : BFD_RELOC_PPC64_TPREL16_HIGHESTA + - : BFD_RELOC_PPC64_DTPREL16_DS + - : BFD_RELOC_PPC64_DTPREL16_LO_DS + - : BFD_RELOC_PPC64_DTPREL16_HIGHER + - : BFD_RELOC_PPC64_DTPREL16_HIGHERA + - : BFD_RELOC_PPC64_DTPREL16_HIGHEST + - : BFD_RELOC_PPC64_DTPREL16_HIGHESTA PowerPC and PowerPC64 thread-local storage relocations. - -- : BFD_RELOC_I370_D12 + - : BFD_RELOC_I370_D12 IBM 370/390 relocations - -- : BFD_RELOC_CTOR + - : BFD_RELOC_CTOR The type of reloc used to build a constructor table - at the moment probably a 32 bit wide absolute relocation, but the target can choose. It generally does map to one of the other relocation types. - -- : BFD_RELOC_ARM_PCREL_BRANCH + - : BFD_RELOC_ARM_PCREL_BRANCH ARM 26 bit pc-relative branch. The lowest two bits must be zero and are not stored in the instruction. - -- : BFD_RELOC_ARM_PCREL_BLX + - : BFD_RELOC_ARM_PCREL_BLX ARM 26 bit pc-relative branch. The lowest bit must be zero and is not stored in the instruction. The 2nd lowest bit comes from a 1 bit field in the instruction. - -- : BFD_RELOC_THUMB_PCREL_BLX + - : BFD_RELOC_THUMB_PCREL_BLX Thumb 22 bit pc-relative branch. The lowest bit must be zero and is not stored in the instruction. The 2nd lowest bit comes from a 1 bit field in the instruction. - -- : BFD_RELOC_ARM_IMMEDIATE - -- : BFD_RELOC_ARM_ADRL_IMMEDIATE - -- : BFD_RELOC_ARM_OFFSET_IMM - -- : BFD_RELOC_ARM_SHIFT_IMM - -- : BFD_RELOC_ARM_SMI - -- : BFD_RELOC_ARM_SWI - -- : BFD_RELOC_ARM_MULTI - -- : BFD_RELOC_ARM_CP_OFF_IMM - -- : BFD_RELOC_ARM_CP_OFF_IMM_S2 - -- : BFD_RELOC_ARM_ADR_IMM - -- : BFD_RELOC_ARM_LDR_IMM - -- : BFD_RELOC_ARM_LITERAL - -- : BFD_RELOC_ARM_IN_POOL - -- : BFD_RELOC_ARM_OFFSET_IMM8 - -- : BFD_RELOC_ARM_HWLITERAL - -- : BFD_RELOC_ARM_THUMB_ADD - -- : BFD_RELOC_ARM_THUMB_IMM - -- : BFD_RELOC_ARM_THUMB_SHIFT - -- : BFD_RELOC_ARM_THUMB_OFFSET - -- : BFD_RELOC_ARM_GOT12 - -- : BFD_RELOC_ARM_GOT32 - -- : BFD_RELOC_ARM_JUMP_SLOT - -- : BFD_RELOC_ARM_COPY - -- : BFD_RELOC_ARM_GLOB_DAT - -- : BFD_RELOC_ARM_PLT32 - -- : BFD_RELOC_ARM_RELATIVE - -- : BFD_RELOC_ARM_GOTOFF - -- : BFD_RELOC_ARM_GOTPC + - : BFD_RELOC_ARM_IMMEDIATE + - : BFD_RELOC_ARM_ADRL_IMMEDIATE + - : BFD_RELOC_ARM_OFFSET_IMM + - : BFD_RELOC_ARM_SHIFT_IMM + - : BFD_RELOC_ARM_SMI + - : BFD_RELOC_ARM_SWI + - : BFD_RELOC_ARM_MULTI + - : BFD_RELOC_ARM_CP_OFF_IMM + - : BFD_RELOC_ARM_CP_OFF_IMM_S2 + - : BFD_RELOC_ARM_ADR_IMM + - : BFD_RELOC_ARM_LDR_IMM + - : BFD_RELOC_ARM_LITERAL + - : BFD_RELOC_ARM_IN_POOL + - : BFD_RELOC_ARM_OFFSET_IMM8 + - : BFD_RELOC_ARM_HWLITERAL + - : BFD_RELOC_ARM_THUMB_ADD + - : BFD_RELOC_ARM_THUMB_IMM + - : BFD_RELOC_ARM_THUMB_SHIFT + - : BFD_RELOC_ARM_THUMB_OFFSET + - : BFD_RELOC_ARM_GOT12 + - : BFD_RELOC_ARM_GOT32 + - : BFD_RELOC_ARM_JUMP_SLOT + - : BFD_RELOC_ARM_COPY + - : BFD_RELOC_ARM_GLOB_DAT + - : BFD_RELOC_ARM_PLT32 + - : BFD_RELOC_ARM_RELATIVE + - : BFD_RELOC_ARM_GOTOFF + - : BFD_RELOC_ARM_GOTPC These relocs are only used within the ARM assembler. They are not (at present) written to any object files. - -- : BFD_RELOC_ARM_TARGET1 + - : BFD_RELOC_ARM_TARGET1 Pc-relative or absolute relocation depending on target. Used for entries in .init_array sections. - -- : BFD_RELOC_ARM_ROSEGREL32 + - : BFD_RELOC_ARM_ROSEGREL32 Read-only segment base relative address. - -- : BFD_RELOC_ARM_SBREL32 + - : BFD_RELOC_ARM_SBREL32 Data segment base relative address. - -- : BFD_RELOC_ARM_TARGET2 + - : BFD_RELOC_ARM_TARGET2 This reloc is used for References to RTTI dta from exception handling tables. The actual definition depends on the target. It may be a pc-relative or some form of GOT-indirect relocation. - -- : BFD_RELOC_ARM_PREL31 + - : BFD_RELOC_ARM_PREL31 31-bit PC relative address. - -- : BFD_RELOC_SH_PCDISP8BY2 - -- : BFD_RELOC_SH_PCDISP12BY2 - -- : BFD_RELOC_SH_IMM3 - -- : BFD_RELOC_SH_IMM3U - -- : BFD_RELOC_SH_DISP12 - -- : BFD_RELOC_SH_DISP12BY2 - -- : BFD_RELOC_SH_DISP12BY4 - -- : BFD_RELOC_SH_DISP12BY8 - -- : BFD_RELOC_SH_DISP20 - -- : BFD_RELOC_SH_DISP20BY8 - -- : BFD_RELOC_SH_IMM4 - -- : BFD_RELOC_SH_IMM4BY2 - -- : BFD_RELOC_SH_IMM4BY4 - -- : BFD_RELOC_SH_IMM8 - -- : BFD_RELOC_SH_IMM8BY2 - -- : BFD_RELOC_SH_IMM8BY4 - -- : BFD_RELOC_SH_PCRELIMM8BY2 - -- : BFD_RELOC_SH_PCRELIMM8BY4 - -- : BFD_RELOC_SH_SWITCH16 - -- : BFD_RELOC_SH_SWITCH32 - -- : BFD_RELOC_SH_USES - -- : BFD_RELOC_SH_COUNT - -- : BFD_RELOC_SH_ALIGN - -- : BFD_RELOC_SH_CODE - -- : BFD_RELOC_SH_DATA - -- : BFD_RELOC_SH_LABEL - -- : BFD_RELOC_SH_LOOP_START - -- : BFD_RELOC_SH_LOOP_END - -- : BFD_RELOC_SH_COPY - -- : BFD_RELOC_SH_GLOB_DAT - -- : BFD_RELOC_SH_JMP_SLOT - -- : BFD_RELOC_SH_RELATIVE - -- : BFD_RELOC_SH_GOTPC - -- : BFD_RELOC_SH_GOT_LOW16 - -- : BFD_RELOC_SH_GOT_MEDLOW16 - -- : BFD_RELOC_SH_GOT_MEDHI16 - -- : BFD_RELOC_SH_GOT_HI16 - -- : BFD_RELOC_SH_GOTPLT_LOW16 - -- : BFD_RELOC_SH_GOTPLT_MEDLOW16 - -- : BFD_RELOC_SH_GOTPLT_MEDHI16 - -- : BFD_RELOC_SH_GOTPLT_HI16 - -- : BFD_RELOC_SH_PLT_LOW16 - -- : BFD_RELOC_SH_PLT_MEDLOW16 - -- : BFD_RELOC_SH_PLT_MEDHI16 - -- : BFD_RELOC_SH_PLT_HI16 - -- : BFD_RELOC_SH_GOTOFF_LOW16 - -- : BFD_RELOC_SH_GOTOFF_MEDLOW16 - -- : BFD_RELOC_SH_GOTOFF_MEDHI16 - -- : BFD_RELOC_SH_GOTOFF_HI16 - -- : BFD_RELOC_SH_GOTPC_LOW16 - -- : BFD_RELOC_SH_GOTPC_MEDLOW16 - -- : BFD_RELOC_SH_GOTPC_MEDHI16 - -- : BFD_RELOC_SH_GOTPC_HI16 - -- : BFD_RELOC_SH_COPY64 - -- : BFD_RELOC_SH_GLOB_DAT64 - -- : BFD_RELOC_SH_JMP_SLOT64 - -- : BFD_RELOC_SH_RELATIVE64 - -- : BFD_RELOC_SH_GOT10BY4 - -- : BFD_RELOC_SH_GOT10BY8 - -- : BFD_RELOC_SH_GOTPLT10BY4 - -- : BFD_RELOC_SH_GOTPLT10BY8 - -- : BFD_RELOC_SH_GOTPLT32 - -- : BFD_RELOC_SH_SHMEDIA_CODE - -- : BFD_RELOC_SH_IMMU5 - -- : BFD_RELOC_SH_IMMS6 - -- : BFD_RELOC_SH_IMMS6BY32 - -- : BFD_RELOC_SH_IMMU6 - -- : BFD_RELOC_SH_IMMS10 - -- : BFD_RELOC_SH_IMMS10BY2 - -- : BFD_RELOC_SH_IMMS10BY4 - -- : BFD_RELOC_SH_IMMS10BY8 - -- : BFD_RELOC_SH_IMMS16 - -- : BFD_RELOC_SH_IMMU16 - -- : BFD_RELOC_SH_IMM_LOW16 - -- : BFD_RELOC_SH_IMM_LOW16_PCREL - -- : BFD_RELOC_SH_IMM_MEDLOW16 - -- : BFD_RELOC_SH_IMM_MEDLOW16_PCREL - -- : BFD_RELOC_SH_IMM_MEDHI16 - -- : BFD_RELOC_SH_IMM_MEDHI16_PCREL - -- : BFD_RELOC_SH_IMM_HI16 - -- : BFD_RELOC_SH_IMM_HI16_PCREL - -- : BFD_RELOC_SH_PT_16 - -- : BFD_RELOC_SH_TLS_GD_32 - -- : BFD_RELOC_SH_TLS_LD_32 - -- : BFD_RELOC_SH_TLS_LDO_32 - -- : BFD_RELOC_SH_TLS_IE_32 - -- : BFD_RELOC_SH_TLS_LE_32 - -- : BFD_RELOC_SH_TLS_DTPMOD32 - -- : BFD_RELOC_SH_TLS_DTPOFF32 - -- : BFD_RELOC_SH_TLS_TPOFF32 + - : BFD_RELOC_SH_PCDISP8BY2 + - : BFD_RELOC_SH_PCDISP12BY2 + - : BFD_RELOC_SH_IMM3 + - : BFD_RELOC_SH_IMM3U + - : BFD_RELOC_SH_DISP12 + - : BFD_RELOC_SH_DISP12BY2 + - : BFD_RELOC_SH_DISP12BY4 + - : BFD_RELOC_SH_DISP12BY8 + - : BFD_RELOC_SH_DISP20 + - : BFD_RELOC_SH_DISP20BY8 + - : BFD_RELOC_SH_IMM4 + - : BFD_RELOC_SH_IMM4BY2 + - : BFD_RELOC_SH_IMM4BY4 + - : BFD_RELOC_SH_IMM8 + - : BFD_RELOC_SH_IMM8BY2 + - : BFD_RELOC_SH_IMM8BY4 + - : BFD_RELOC_SH_PCRELIMM8BY2 + - : BFD_RELOC_SH_PCRELIMM8BY4 + - : BFD_RELOC_SH_SWITCH16 + - : BFD_RELOC_SH_SWITCH32 + - : BFD_RELOC_SH_USES + - : BFD_RELOC_SH_COUNT + - : BFD_RELOC_SH_ALIGN + - : BFD_RELOC_SH_CODE + - : BFD_RELOC_SH_DATA + - : BFD_RELOC_SH_LABEL + - : BFD_RELOC_SH_LOOP_START + - : BFD_RELOC_SH_LOOP_END + - : BFD_RELOC_SH_COPY + - : BFD_RELOC_SH_GLOB_DAT + - : BFD_RELOC_SH_JMP_SLOT + - : BFD_RELOC_SH_RELATIVE + - : BFD_RELOC_SH_GOTPC + - : BFD_RELOC_SH_GOT_LOW16 + - : BFD_RELOC_SH_GOT_MEDLOW16 + - : BFD_RELOC_SH_GOT_MEDHI16 + - : BFD_RELOC_SH_GOT_HI16 + - : BFD_RELOC_SH_GOTPLT_LOW16 + - : BFD_RELOC_SH_GOTPLT_MEDLOW16 + - : BFD_RELOC_SH_GOTPLT_MEDHI16 + - : BFD_RELOC_SH_GOTPLT_HI16 + - : BFD_RELOC_SH_PLT_LOW16 + - : BFD_RELOC_SH_PLT_MEDLOW16 + - : BFD_RELOC_SH_PLT_MEDHI16 + - : BFD_RELOC_SH_PLT_HI16 + - : BFD_RELOC_SH_GOTOFF_LOW16 + - : BFD_RELOC_SH_GOTOFF_MEDLOW16 + - : BFD_RELOC_SH_GOTOFF_MEDHI16 + - : BFD_RELOC_SH_GOTOFF_HI16 + - : BFD_RELOC_SH_GOTPC_LOW16 + - : BFD_RELOC_SH_GOTPC_MEDLOW16 + - : BFD_RELOC_SH_GOTPC_MEDHI16 + - : BFD_RELOC_SH_GOTPC_HI16 + - : BFD_RELOC_SH_COPY64 + - : BFD_RELOC_SH_GLOB_DAT64 + - : BFD_RELOC_SH_JMP_SLOT64 + - : BFD_RELOC_SH_RELATIVE64 + - : BFD_RELOC_SH_GOT10BY4 + - : BFD_RELOC_SH_GOT10BY8 + - : BFD_RELOC_SH_GOTPLT10BY4 + - : BFD_RELOC_SH_GOTPLT10BY8 + - : BFD_RELOC_SH_GOTPLT32 + - : BFD_RELOC_SH_SHMEDIA_CODE + - : BFD_RELOC_SH_IMMU5 + - : BFD_RELOC_SH_IMMS6 + - : BFD_RELOC_SH_IMMS6BY32 + - : BFD_RELOC_SH_IMMU6 + - : BFD_RELOC_SH_IMMS10 + - : BFD_RELOC_SH_IMMS10BY2 + - : BFD_RELOC_SH_IMMS10BY4 + - : BFD_RELOC_SH_IMMS10BY8 + - : BFD_RELOC_SH_IMMS16 + - : BFD_RELOC_SH_IMMU16 + - : BFD_RELOC_SH_IMM_LOW16 + - : BFD_RELOC_SH_IMM_LOW16_PCREL + - : BFD_RELOC_SH_IMM_MEDLOW16 + - : BFD_RELOC_SH_IMM_MEDLOW16_PCREL + - : BFD_RELOC_SH_IMM_MEDHI16 + - : BFD_RELOC_SH_IMM_MEDHI16_PCREL + - : BFD_RELOC_SH_IMM_HI16 + - : BFD_RELOC_SH_IMM_HI16_PCREL + - : BFD_RELOC_SH_PT_16 + - : BFD_RELOC_SH_TLS_GD_32 + - : BFD_RELOC_SH_TLS_LD_32 + - : BFD_RELOC_SH_TLS_LDO_32 + - : BFD_RELOC_SH_TLS_IE_32 + - : BFD_RELOC_SH_TLS_LE_32 + - : BFD_RELOC_SH_TLS_DTPMOD32 + - : BFD_RELOC_SH_TLS_DTPOFF32 + - : BFD_RELOC_SH_TLS_TPOFF32 Renesas / SuperH SH relocs. Not all of these appear in object files. - -- : BFD_RELOC_THUMB_PCREL_BRANCH9 - -- : BFD_RELOC_THUMB_PCREL_BRANCH12 - -- : BFD_RELOC_THUMB_PCREL_BRANCH23 + - : BFD_RELOC_THUMB_PCREL_BRANCH9 + - : BFD_RELOC_THUMB_PCREL_BRANCH12 + - : BFD_RELOC_THUMB_PCREL_BRANCH23 Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must be zero and is not stored in the instruction. - -- : BFD_RELOC_ARC_B22_PCREL + - : BFD_RELOC_ARC_B22_PCREL ARC Cores relocs. ARC 22 bit pc-relative branch. The lowest two bits must be zero and are not stored in the instruction. The high 20 bits are installed in bits 26 through 7 of the instruction. - -- : BFD_RELOC_ARC_B26 + - : BFD_RELOC_ARC_B26 ARC 26 bit absolute branch. The lowest two bits must be zero and are not stored in the instruction. The high 24 bits are installed in bits 23 through 0. - -- : BFD_RELOC_D10V_10_PCREL_R + - : BFD_RELOC_D10V_10_PCREL_R Mitsubishi D10V relocs. This is a 10-bit reloc with the right 2 bits assumed to be 0. - -- : BFD_RELOC_D10V_10_PCREL_L + - : BFD_RELOC_D10V_10_PCREL_L Mitsubishi D10V relocs. This is a 10-bit reloc with the right 2 bits assumed to be 0. This is the same as the previous reloc except it is in the left container, i.e., shifted left 15 bits. - -- : BFD_RELOC_D10V_18 + - : BFD_RELOC_D10V_18 This is an 18-bit reloc with the right 2 bits assumed to be 0. - -- : BFD_RELOC_D10V_18_PCREL + - : BFD_RELOC_D10V_18_PCREL This is an 18-bit reloc with the right 2 bits assumed to be 0. - -- : BFD_RELOC_D30V_6 + - : BFD_RELOC_D30V_6 Mitsubishi D30V relocs. This is a 6-bit absolute reloc. - -- : BFD_RELOC_D30V_9_PCREL + - : BFD_RELOC_D30V_9_PCREL This is a 6-bit pc-relative reloc with the right 3 bits assumed to be 0. - -- : BFD_RELOC_D30V_9_PCREL_R + - : BFD_RELOC_D30V_9_PCREL_R This is a 6-bit pc-relative reloc with the right 3 bits assumed to be 0. Same as the previous reloc but on the right side of the container. - -- : BFD_RELOC_D30V_15 + - : BFD_RELOC_D30V_15 This is a 12-bit absolute reloc with the right 3 bitsassumed to be 0. - -- : BFD_RELOC_D30V_15_PCREL + - : BFD_RELOC_D30V_15_PCREL This is a 12-bit pc-relative reloc with the right 3 bits assumed to be 0. - -- : BFD_RELOC_D30V_15_PCREL_R + - : BFD_RELOC_D30V_15_PCREL_R This is a 12-bit pc-relative reloc with the right 3 bits assumed to be 0. Same as the previous reloc but on the right side of the container. - -- : BFD_RELOC_D30V_21 + - : BFD_RELOC_D30V_21 This is an 18-bit absolute reloc with the right 3 bits assumed to be 0. - -- : BFD_RELOC_D30V_21_PCREL + - : BFD_RELOC_D30V_21_PCREL This is an 18-bit pc-relative reloc with the right 3 bits assumed to be 0. - -- : BFD_RELOC_D30V_21_PCREL_R + - : BFD_RELOC_D30V_21_PCREL_R This is an 18-bit pc-relative reloc with the right 3 bits assumed to be 0. Same as the previous reloc but on the right side of the container. - -- : BFD_RELOC_D30V_32 + - : BFD_RELOC_D30V_32 This is a 32-bit absolute reloc. - -- : BFD_RELOC_D30V_32_PCREL + - : BFD_RELOC_D30V_32_PCREL This is a 32-bit pc-relative reloc. - -- : BFD_RELOC_DLX_HI16_S + - : BFD_RELOC_DLX_HI16_S DLX relocs - -- : BFD_RELOC_DLX_LO16 + - : BFD_RELOC_DLX_LO16 DLX relocs - -- : BFD_RELOC_DLX_JMP26 + - : BFD_RELOC_DLX_JMP26 DLX relocs - -- : BFD_RELOC_M32R_24 + - : BFD_RELOC_M32R_24 Renesas M32R (formerly Mitsubishi M32R) relocs. This is a 24 bit absolute address. - -- : BFD_RELOC_M32R_10_PCREL + - : BFD_RELOC_M32R_10_PCREL This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. - -- : BFD_RELOC_M32R_18_PCREL + - : BFD_RELOC_M32R_18_PCREL This is an 18-bit reloc with the right 2 bits assumed to be 0. - -- : BFD_RELOC_M32R_26_PCREL + - : BFD_RELOC_M32R_26_PCREL This is a 26-bit reloc with the right 2 bits assumed to be 0. - -- : BFD_RELOC_M32R_HI16_ULO + - : BFD_RELOC_M32R_HI16_ULO This is a 16-bit reloc containing the high 16 bits of an address used when the lower 16 bits are treated as unsigned. - -- : BFD_RELOC_M32R_HI16_SLO + - : BFD_RELOC_M32R_HI16_SLO This is a 16-bit reloc containing the high 16 bits of an address used when the lower 16 bits are treated as signed. - -- : BFD_RELOC_M32R_LO16 + - : BFD_RELOC_M32R_LO16 This is a 16-bit reloc containing the lower 16 bits of an address. - -- : BFD_RELOC_M32R_SDA16 + - : BFD_RELOC_M32R_SDA16 This is a 16-bit reloc containing the small data area offset for use in add3, load, and store instructions. - -- : BFD_RELOC_M32R_GOT24 - -- : BFD_RELOC_M32R_26_PLTREL - -- : BFD_RELOC_M32R_COPY - -- : BFD_RELOC_M32R_GLOB_DAT - -- : BFD_RELOC_M32R_JMP_SLOT - -- : BFD_RELOC_M32R_RELATIVE - -- : BFD_RELOC_M32R_GOTOFF - -- : BFD_RELOC_M32R_GOTOFF_HI_ULO - -- : BFD_RELOC_M32R_GOTOFF_HI_SLO - -- : BFD_RELOC_M32R_GOTOFF_LO - -- : BFD_RELOC_M32R_GOTPC24 - -- : BFD_RELOC_M32R_GOT16_HI_ULO - -- : BFD_RELOC_M32R_GOT16_HI_SLO - -- : BFD_RELOC_M32R_GOT16_LO - -- : BFD_RELOC_M32R_GOTPC_HI_ULO - -- : BFD_RELOC_M32R_GOTPC_HI_SLO - -- : BFD_RELOC_M32R_GOTPC_LO + - : BFD_RELOC_M32R_GOT24 + - : BFD_RELOC_M32R_26_PLTREL + - : BFD_RELOC_M32R_COPY + - : BFD_RELOC_M32R_GLOB_DAT + - : BFD_RELOC_M32R_JMP_SLOT + - : BFD_RELOC_M32R_RELATIVE + - : BFD_RELOC_M32R_GOTOFF + - : BFD_RELOC_M32R_GOTOFF_HI_ULO + - : BFD_RELOC_M32R_GOTOFF_HI_SLO + - : BFD_RELOC_M32R_GOTOFF_LO + - : BFD_RELOC_M32R_GOTPC24 + - : BFD_RELOC_M32R_GOT16_HI_ULO + - : BFD_RELOC_M32R_GOT16_HI_SLO + - : BFD_RELOC_M32R_GOT16_LO + - : BFD_RELOC_M32R_GOTPC_HI_ULO + - : BFD_RELOC_M32R_GOTPC_HI_SLO + - : BFD_RELOC_M32R_GOTPC_LO For PIC. - -- : BFD_RELOC_V850_9_PCREL + - : BFD_RELOC_V850_9_PCREL This is a 9-bit reloc - -- : BFD_RELOC_V850_22_PCREL + - : BFD_RELOC_V850_22_PCREL This is a 22-bit reloc - -- : BFD_RELOC_V850_SDA_16_16_OFFSET + - : BFD_RELOC_V850_SDA_16_16_OFFSET This is a 16 bit offset from the short data area pointer. - -- : BFD_RELOC_V850_SDA_15_16_OFFSET + - : BFD_RELOC_V850_SDA_15_16_OFFSET This is a 16 bit offset (of which only 15 bits are used) from the short data area pointer. - -- : BFD_RELOC_V850_ZDA_16_16_OFFSET + - : BFD_RELOC_V850_ZDA_16_16_OFFSET This is a 16 bit offset from the zero data area pointer. - -- : BFD_RELOC_V850_ZDA_15_16_OFFSET + - : BFD_RELOC_V850_ZDA_15_16_OFFSET This is a 16 bit offset (of which only 15 bits are used) from the zero data area pointer. - -- : BFD_RELOC_V850_TDA_6_8_OFFSET + - : BFD_RELOC_V850_TDA_6_8_OFFSET This is an 8 bit offset (of which only 6 bits are used) from the tiny data area pointer. - -- : BFD_RELOC_V850_TDA_7_8_OFFSET + - : BFD_RELOC_V850_TDA_7_8_OFFSET This is an 8bit offset (of which only 7 bits are used) from the tiny data area pointer. - -- : BFD_RELOC_V850_TDA_7_7_OFFSET + - : BFD_RELOC_V850_TDA_7_7_OFFSET This is a 7 bit offset from the tiny data area pointer. - -- : BFD_RELOC_V850_TDA_16_16_OFFSET + - : BFD_RELOC_V850_TDA_16_16_OFFSET This is a 16 bit offset from the tiny data area pointer. - -- : BFD_RELOC_V850_TDA_4_5_OFFSET + - : BFD_RELOC_V850_TDA_4_5_OFFSET This is a 5 bit offset (of which only 4 bits are used) from the tiny data area pointer. - -- : BFD_RELOC_V850_TDA_4_4_OFFSET + - : BFD_RELOC_V850_TDA_4_4_OFFSET This is a 4 bit offset from the tiny data area pointer. - -- : BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET + - : BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET This is a 16 bit offset from the short data area pointer, with the bits placed non-contiguously in the instruction. - -- : BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET + - : BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET This is a 16 bit offset from the zero data area pointer, with the bits placed non-contiguously in the instruction. - -- : BFD_RELOC_V850_CALLT_6_7_OFFSET + - : BFD_RELOC_V850_CALLT_6_7_OFFSET This is a 6 bit offset from the call table base pointer. - -- : BFD_RELOC_V850_CALLT_16_16_OFFSET + - : BFD_RELOC_V850_CALLT_16_16_OFFSET This is a 16 bit offset from the call table base pointer. - -- : BFD_RELOC_V850_LONGCALL + - : BFD_RELOC_V850_LONGCALL Used for relaxing indirect function calls. - -- : BFD_RELOC_V850_LONGJUMP + - : BFD_RELOC_V850_LONGJUMP Used for relaxing indirect jumps. - -- : BFD_RELOC_V850_ALIGN + - : BFD_RELOC_V850_ALIGN Used to maintain alignment whilst relaxing. - -- : BFD_RELOC_V850_LO16_SPLIT_OFFSET + - : BFD_RELOC_V850_LO16_SPLIT_OFFSET This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu instructions. - -- : BFD_RELOC_MN10300_32_PCREL + - : BFD_RELOC_MN10300_32_PCREL This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the instruction. - -- : BFD_RELOC_MN10300_16_PCREL + - : BFD_RELOC_MN10300_16_PCREL This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the instruction. - -- : BFD_RELOC_TIC30_LDP + - : BFD_RELOC_TIC30_LDP This is a 8bit DP reloc for the tms320c30, where the most significant 8 bits of a 24 bit word are placed into the least significant 8 bits of the opcode. - -- : BFD_RELOC_TIC54X_PARTLS7 + - : BFD_RELOC_TIC54X_PARTLS7 This is a 7bit reloc for the tms320c54x, where the least significant 7 bits of a 16 bit word are placed into the least significant 7 bits of the opcode. - -- : BFD_RELOC_TIC54X_PARTMS9 + - : BFD_RELOC_TIC54X_PARTMS9 This is a 9bit DP reloc for the tms320c54x, where the most significant 9 bits of a 16 bit word are placed into the least significant 9 bits of the opcode. - -- : BFD_RELOC_TIC54X_23 + - : BFD_RELOC_TIC54X_23 This is an extended address 23-bit reloc for the tms320c54x. - -- : BFD_RELOC_TIC54X_16_OF_23 + - : BFD_RELOC_TIC54X_16_OF_23 This is a 16-bit reloc for the tms320c54x, where the least significant 16 bits of a 23-bit extended address are placed into the opcode. - -- : BFD_RELOC_TIC54X_MS7_OF_23 + - : BFD_RELOC_TIC54X_MS7_OF_23 This is a reloc for the tms320c54x, where the most significant 7 bits of a 23-bit extended address are placed into the opcode. - -- : BFD_RELOC_FR30_48 + - : BFD_RELOC_FR30_48 This is a 48 bit reloc for the FR30 that stores 32 bits. - -- : BFD_RELOC_FR30_20 + - : BFD_RELOC_FR30_20 This is a 32 bit reloc for the FR30 that stores 20 bits split up into two sections. - -- : BFD_RELOC_FR30_6_IN_4 + - : BFD_RELOC_FR30_6_IN_4 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 4 bits. - -- : BFD_RELOC_FR30_8_IN_8 + - : BFD_RELOC_FR30_8_IN_8 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset into 8 bits. - -- : BFD_RELOC_FR30_9_IN_8 + - : BFD_RELOC_FR30_9_IN_8 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset into 8 bits. - -- : BFD_RELOC_FR30_10_IN_8 + - : BFD_RELOC_FR30_10_IN_8 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset into 8 bits. - -- : BFD_RELOC_FR30_9_PCREL + - : BFD_RELOC_FR30_9_PCREL This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative short offset into 8 bits. - -- : BFD_RELOC_FR30_12_PCREL + - : BFD_RELOC_FR30_12_PCREL This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative short offset into 11 bits. - -- : BFD_RELOC_MCORE_PCREL_IMM8BY4 - -- : BFD_RELOC_MCORE_PCREL_IMM11BY2 - -- : BFD_RELOC_MCORE_PCREL_IMM4BY2 - -- : BFD_RELOC_MCORE_PCREL_32 - -- : BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 - -- : BFD_RELOC_MCORE_RVA + - : BFD_RELOC_MCORE_PCREL_IMM8BY4 + - : BFD_RELOC_MCORE_PCREL_IMM11BY2 + - : BFD_RELOC_MCORE_PCREL_IMM4BY2 + - : BFD_RELOC_MCORE_PCREL_32 + - : BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 + - : BFD_RELOC_MCORE_RVA Motorola Mcore relocations. - -- : BFD_RELOC_MMIX_GETA - -- : BFD_RELOC_MMIX_GETA_1 - -- : BFD_RELOC_MMIX_GETA_2 - -- : BFD_RELOC_MMIX_GETA_3 + - : BFD_RELOC_MMIX_GETA + - : BFD_RELOC_MMIX_GETA_1 + - : BFD_RELOC_MMIX_GETA_2 + - : BFD_RELOC_MMIX_GETA_3 These are relocations for the GETA instruction. - -- : BFD_RELOC_MMIX_CBRANCH - -- : BFD_RELOC_MMIX_CBRANCH_J - -- : BFD_RELOC_MMIX_CBRANCH_1 - -- : BFD_RELOC_MMIX_CBRANCH_2 - -- : BFD_RELOC_MMIX_CBRANCH_3 + - : BFD_RELOC_MMIX_CBRANCH + - : BFD_RELOC_MMIX_CBRANCH_J + - : BFD_RELOC_MMIX_CBRANCH_1 + - : BFD_RELOC_MMIX_CBRANCH_2 + - : BFD_RELOC_MMIX_CBRANCH_3 These are relocations for a conditional branch instruction. - -- : BFD_RELOC_MMIX_PUSHJ - -- : BFD_RELOC_MMIX_PUSHJ_1 - -- : BFD_RELOC_MMIX_PUSHJ_2 - -- : BFD_RELOC_MMIX_PUSHJ_3 - -- : BFD_RELOC_MMIX_PUSHJ_STUBBABLE + - : BFD_RELOC_MMIX_PUSHJ + - : BFD_RELOC_MMIX_PUSHJ_1 + - : BFD_RELOC_MMIX_PUSHJ_2 + - : BFD_RELOC_MMIX_PUSHJ_3 + - : BFD_RELOC_MMIX_PUSHJ_STUBBABLE These are relocations for the PUSHJ instruction. - -- : BFD_RELOC_MMIX_JMP - -- : BFD_RELOC_MMIX_JMP_1 - -- : BFD_RELOC_MMIX_JMP_2 - -- : BFD_RELOC_MMIX_JMP_3 + - : BFD_RELOC_MMIX_JMP + - : BFD_RELOC_MMIX_JMP_1 + - : BFD_RELOC_MMIX_JMP_2 + - : BFD_RELOC_MMIX_JMP_3 These are relocations for the JMP instruction. - -- : BFD_RELOC_MMIX_ADDR19 + - : BFD_RELOC_MMIX_ADDR19 This is a relocation for a relative address as in a GETA instruction or a branch. - -- : BFD_RELOC_MMIX_ADDR27 + - : BFD_RELOC_MMIX_ADDR27 This is a relocation for a relative address as in a JMP instruction. - -- : BFD_RELOC_MMIX_REG_OR_BYTE + - : BFD_RELOC_MMIX_REG_OR_BYTE This is a relocation for an instruction field that may be a general register or a value 0..255. - -- : BFD_RELOC_MMIX_REG + - : BFD_RELOC_MMIX_REG This is a relocation for an instruction field that may be a general register. - -- : BFD_RELOC_MMIX_BASE_PLUS_OFFSET + - : BFD_RELOC_MMIX_BASE_PLUS_OFFSET This is a relocation for two instruction fields holding a register and an offset, the equivalent of the relocation. - -- : BFD_RELOC_MMIX_LOCAL + - : BFD_RELOC_MMIX_LOCAL This relocation is an assertion that the expression is not allocated as a global register. It does not modify contents. - -- : BFD_RELOC_AVR_7_PCREL + - : BFD_RELOC_AVR_7_PCREL This is a 16 bit reloc for the AVR that stores 8 bit pc relative short offset into 7 bits. - -- : BFD_RELOC_AVR_13_PCREL + - : BFD_RELOC_AVR_13_PCREL This is a 16 bit reloc for the AVR that stores 13 bit pc relative short offset into 12 bits. - -- : BFD_RELOC_AVR_16_PM + - : BFD_RELOC_AVR_16_PM This is a 16 bit reloc for the AVR that stores 17 bit value (usually program memory address) into 16 bits. - -- : BFD_RELOC_AVR_LO8_LDI + - : BFD_RELOC_AVR_LO8_LDI This is a 16 bit reloc for the AVR that stores 8 bit value (usually data memory address) into 8 bit immediate value of LDI insn. - -- : BFD_RELOC_AVR_HI8_LDI + - : BFD_RELOC_AVR_HI8_LDI This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit of data memory address) into 8 bit immediate value of LDI insn. - -- : BFD_RELOC_AVR_HH8_LDI + - : BFD_RELOC_AVR_HH8_LDI This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit of program memory address) into 8 bit immediate value of LDI insn. - -- : BFD_RELOC_AVR_LO8_LDI_NEG + - : BFD_RELOC_AVR_LO8_LDI_NEG This is a 16 bit reloc for the AVR that stores negated 8 bit value (usually data memory address) into 8 bit immediate value of SUBI insn. - -- : BFD_RELOC_AVR_HI8_LDI_NEG + - : BFD_RELOC_AVR_HI8_LDI_NEG This is a 16 bit reloc for the AVR that stores negated 8 bit value (high 8 bit of data memory address) into 8 bit immediate value of SUBI insn. - -- : BFD_RELOC_AVR_HH8_LDI_NEG + - : BFD_RELOC_AVR_HH8_LDI_NEG This is a 16 bit reloc for the AVR that stores negated 8 bit value (most high 8 bit of program memory address) into 8 bit immediate value of LDI or SUBI insn. - -- : BFD_RELOC_AVR_LO8_LDI_PM + - : BFD_RELOC_AVR_LO8_LDI_PM This is a 16 bit reloc for the AVR that stores 8 bit value (usually command address) into 8 bit immediate value of LDI insn. - -- : BFD_RELOC_AVR_HI8_LDI_PM + - : BFD_RELOC_AVR_HI8_LDI_PM This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit of command address) into 8 bit immediate value of LDI insn. - -- : BFD_RELOC_AVR_HH8_LDI_PM + - : BFD_RELOC_AVR_HH8_LDI_PM This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit of command address) into 8 bit immediate value of LDI insn. - -- : BFD_RELOC_AVR_LO8_LDI_PM_NEG + - : BFD_RELOC_AVR_LO8_LDI_PM_NEG This is a 16 bit reloc for the AVR that stores negated 8 bit value (usually command address) into 8 bit immediate value of SUBI insn. - -- : BFD_RELOC_AVR_HI8_LDI_PM_NEG + - : BFD_RELOC_AVR_HI8_LDI_PM_NEG This is a 16 bit reloc for the AVR that stores negated 8 bit value (high 8 bit of 16 bit command address) into 8 bit immediate value of SUBI insn. - -- : BFD_RELOC_AVR_HH8_LDI_PM_NEG + - : BFD_RELOC_AVR_HH8_LDI_PM_NEG This is a 16 bit reloc for the AVR that stores negated 8 bit value (high 6 bit of 22 bit command address) into 8 bit immediate value of SUBI insn. - -- : BFD_RELOC_AVR_CALL + - : BFD_RELOC_AVR_CALL This is a 32 bit reloc for the AVR that stores 23 bit value into 22 bits. - -- : BFD_RELOC_AVR_LDI + - : BFD_RELOC_AVR_LDI This is a 16 bit reloc for the AVR that stores all needed bits for absolute addressing with ldi with overflow check to linktime - -- : BFD_RELOC_AVR_6 + - : BFD_RELOC_AVR_6 This is a 6 bit reloc for the AVR that stores offset for ldd/std instructions - -- : BFD_RELOC_AVR_6_ADIW + - : BFD_RELOC_AVR_6_ADIW This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw instructions - -- : BFD_RELOC_390_12 + - : BFD_RELOC_390_12 Direct 12 bit. - -- : BFD_RELOC_390_GOT12 + - : BFD_RELOC_390_GOT12 12 bit GOT offset. - -- : BFD_RELOC_390_PLT32 + - : BFD_RELOC_390_PLT32 32 bit PC relative PLT address. - -- : BFD_RELOC_390_COPY + - : BFD_RELOC_390_COPY Copy symbol at runtime. - -- : BFD_RELOC_390_GLOB_DAT + - : BFD_RELOC_390_GLOB_DAT Create GOT entry. - -- : BFD_RELOC_390_JMP_SLOT + - : BFD_RELOC_390_JMP_SLOT Create PLT entry. - -- : BFD_RELOC_390_RELATIVE + - : BFD_RELOC_390_RELATIVE Adjust by program base. - -- : BFD_RELOC_390_GOTPC + - : BFD_RELOC_390_GOTPC 32 bit PC relative offset to GOT. - -- : BFD_RELOC_390_GOT16 + - : BFD_RELOC_390_GOT16 16 bit GOT offset. - -- : BFD_RELOC_390_PC16DBL + - : BFD_RELOC_390_PC16DBL PC relative 16 bit shifted by 1. - -- : BFD_RELOC_390_PLT16DBL + - : BFD_RELOC_390_PLT16DBL 16 bit PC rel. PLT shifted by 1. - -- : BFD_RELOC_390_PC32DBL + - : BFD_RELOC_390_PC32DBL PC relative 32 bit shifted by 1. - -- : BFD_RELOC_390_PLT32DBL + - : BFD_RELOC_390_PLT32DBL 32 bit PC rel. PLT shifted by 1. - -- : BFD_RELOC_390_GOTPCDBL + - : BFD_RELOC_390_GOTPCDBL 32 bit PC rel. GOT shifted by 1. - -- : BFD_RELOC_390_GOT64 + - : BFD_RELOC_390_GOT64 64 bit GOT offset. - -- : BFD_RELOC_390_PLT64 + - : BFD_RELOC_390_PLT64 64 bit PC relative PLT address. - -- : BFD_RELOC_390_GOTENT + - : BFD_RELOC_390_GOTENT 32 bit rel. offset to GOT entry. - -- : BFD_RELOC_390_GOTOFF64 + - : BFD_RELOC_390_GOTOFF64 64 bit offset to GOT. - -- : BFD_RELOC_390_GOTPLT12 + - : BFD_RELOC_390_GOTPLT12 12-bit offset to symbol-entry within GOT, with PLT handling. - -- : BFD_RELOC_390_GOTPLT16 + - : BFD_RELOC_390_GOTPLT16 16-bit offset to symbol-entry within GOT, with PLT handling. - -- : BFD_RELOC_390_GOTPLT32 + - : BFD_RELOC_390_GOTPLT32 32-bit offset to symbol-entry within GOT, with PLT handling. - -- : BFD_RELOC_390_GOTPLT64 + - : BFD_RELOC_390_GOTPLT64 64-bit offset to symbol-entry within GOT, with PLT handling. - -- : BFD_RELOC_390_GOTPLTENT + - : BFD_RELOC_390_GOTPLTENT 32-bit rel. offset to symbol-entry within GOT, with PLT handling. - -- : BFD_RELOC_390_PLTOFF16 + - : BFD_RELOC_390_PLTOFF16 16-bit rel. offset from the GOT to a PLT entry. - -- : BFD_RELOC_390_PLTOFF32 + - : BFD_RELOC_390_PLTOFF32 32-bit rel. offset from the GOT to a PLT entry. - -- : BFD_RELOC_390_PLTOFF64 + - : BFD_RELOC_390_PLTOFF64 64-bit rel. offset from the GOT to a PLT entry. - -- : BFD_RELOC_390_TLS_LOAD - -- : BFD_RELOC_390_TLS_GDCALL - -- : BFD_RELOC_390_TLS_LDCALL - -- : BFD_RELOC_390_TLS_GD32 - -- : BFD_RELOC_390_TLS_GD64 - -- : BFD_RELOC_390_TLS_GOTIE12 - -- : BFD_RELOC_390_TLS_GOTIE32 - -- : BFD_RELOC_390_TLS_GOTIE64 - -- : BFD_RELOC_390_TLS_LDM32 - -- : BFD_RELOC_390_TLS_LDM64 - -- : BFD_RELOC_390_TLS_IE32 - -- : BFD_RELOC_390_TLS_IE64 - -- : BFD_RELOC_390_TLS_IEENT - -- : BFD_RELOC_390_TLS_LE32 - -- : BFD_RELOC_390_TLS_LE64 - -- : BFD_RELOC_390_TLS_LDO32 - -- : BFD_RELOC_390_TLS_LDO64 - -- : BFD_RELOC_390_TLS_DTPMOD - -- : BFD_RELOC_390_TLS_DTPOFF - -- : BFD_RELOC_390_TLS_TPOFF + - : BFD_RELOC_390_TLS_LOAD + - : BFD_RELOC_390_TLS_GDCALL + - : BFD_RELOC_390_TLS_LDCALL + - : BFD_RELOC_390_TLS_GD32 + - : BFD_RELOC_390_TLS_GD64 + - : BFD_RELOC_390_TLS_GOTIE12 + - : BFD_RELOC_390_TLS_GOTIE32 + - : BFD_RELOC_390_TLS_GOTIE64 + - : BFD_RELOC_390_TLS_LDM32 + - : BFD_RELOC_390_TLS_LDM64 + - : BFD_RELOC_390_TLS_IE32 + - : BFD_RELOC_390_TLS_IE64 + - : BFD_RELOC_390_TLS_IEENT + - : BFD_RELOC_390_TLS_LE32 + - : BFD_RELOC_390_TLS_LE64 + - : BFD_RELOC_390_TLS_LDO32 + - : BFD_RELOC_390_TLS_LDO64 + - : BFD_RELOC_390_TLS_DTPMOD + - : BFD_RELOC_390_TLS_DTPOFF + - : BFD_RELOC_390_TLS_TPOFF s390 tls relocations. - -- : BFD_RELOC_390_20 - -- : BFD_RELOC_390_GOT20 - -- : BFD_RELOC_390_GOTPLT20 - -- : BFD_RELOC_390_TLS_GOTIE20 + - : BFD_RELOC_390_20 + - : BFD_RELOC_390_GOT20 + - : BFD_RELOC_390_GOTPLT20 + - : BFD_RELOC_390_TLS_GOTIE20 Long displacement extension. - -- : BFD_RELOC_IP2K_FR9 + - : BFD_RELOC_IP2K_FR9 Scenix IP2K - 9-bit register number / data address - -- : BFD_RELOC_IP2K_BANK + - : BFD_RELOC_IP2K_BANK Scenix IP2K - 4-bit register/data bank number - -- : BFD_RELOC_IP2K_ADDR16CJP + - : BFD_RELOC_IP2K_ADDR16CJP Scenix IP2K - low 13 bits of instruction word address - -- : BFD_RELOC_IP2K_PAGE3 + - : BFD_RELOC_IP2K_PAGE3 Scenix IP2K - high 3 bits of instruction word address - -- : BFD_RELOC_IP2K_LO8DATA - -- : BFD_RELOC_IP2K_HI8DATA - -- : BFD_RELOC_IP2K_EX8DATA + - : BFD_RELOC_IP2K_LO8DATA + - : BFD_RELOC_IP2K_HI8DATA + - : BFD_RELOC_IP2K_EX8DATA Scenix IP2K - ext/low/high 8 bits of data address - -- : BFD_RELOC_IP2K_LO8INSN - -- : BFD_RELOC_IP2K_HI8INSN + - : BFD_RELOC_IP2K_LO8INSN + - : BFD_RELOC_IP2K_HI8INSN Scenix IP2K - low/high 8 bits of instruction word address - -- : BFD_RELOC_IP2K_PC_SKIP + - : BFD_RELOC_IP2K_PC_SKIP Scenix IP2K - even/odd PC modifier to modify snb pcl.0 - -- : BFD_RELOC_IP2K_TEXT + - : BFD_RELOC_IP2K_TEXT Scenix IP2K - 16 bit word address in text section. - -- : BFD_RELOC_IP2K_FR_OFFSET + - : BFD_RELOC_IP2K_FR_OFFSET Scenix IP2K - 7-bit sp or dp offset - -- : BFD_RELOC_VPE4KMATH_DATA - -- : BFD_RELOC_VPE4KMATH_INSN + - : BFD_RELOC_VPE4KMATH_DATA + - : BFD_RELOC_VPE4KMATH_INSN Scenix VPE4K coprocessor - data/insn-space addressing - -- : BFD_RELOC_VTABLE_INHERIT - -- : BFD_RELOC_VTABLE_ENTRY + - : BFD_RELOC_VTABLE_INHERIT + - : BFD_RELOC_VTABLE_ENTRY These two relocations are used by the linker to determine which of the entries in a C++ virtual function table are actually used. When the -gc-sections option is given, the linker will zero out @@ -4213,322 +4214,336 @@ this offset is stored in the reloc's addend. For Rel hosts, we are forced to put this offset in the reloc's section offset. - -- : BFD_RELOC_IA64_IMM14 - -- : BFD_RELOC_IA64_IMM22 - -- : BFD_RELOC_IA64_IMM64 - -- : BFD_RELOC_IA64_DIR32MSB - -- : BFD_RELOC_IA64_DIR32LSB - -- : BFD_RELOC_IA64_DIR64MSB - -- : BFD_RELOC_IA64_DIR64LSB - -- : BFD_RELOC_IA64_GPREL22 - -- : BFD_RELOC_IA64_GPREL64I - -- : BFD_RELOC_IA64_GPREL32MSB - -- : BFD_RELOC_IA64_GPREL32LSB - -- : BFD_RELOC_IA64_GPREL64MSB - -- : BFD_RELOC_IA64_GPREL64LSB - -- : BFD_RELOC_IA64_LTOFF22 - -- : BFD_RELOC_IA64_LTOFF64I - -- : BFD_RELOC_IA64_PLTOFF22 - -- : BFD_RELOC_IA64_PLTOFF64I - -- : BFD_RELOC_IA64_PLTOFF64MSB - -- : BFD_RELOC_IA64_PLTOFF64LSB - -- : BFD_RELOC_IA64_FPTR64I - -- : BFD_RELOC_IA64_FPTR32MSB - -- : BFD_RELOC_IA64_FPTR32LSB - -- : BFD_RELOC_IA64_FPTR64MSB - -- : BFD_RELOC_IA64_FPTR64LSB - -- : BFD_RELOC_IA64_PCREL21B - -- : BFD_RELOC_IA64_PCREL21BI - -- : BFD_RELOC_IA64_PCREL21M - -- : BFD_RELOC_IA64_PCREL21F - -- : BFD_RELOC_IA64_PCREL22 - -- : BFD_RELOC_IA64_PCREL60B - -- : BFD_RELOC_IA64_PCREL64I - -- : BFD_RELOC_IA64_PCREL32MSB - -- : BFD_RELOC_IA64_PCREL32LSB - -- : BFD_RELOC_IA64_PCREL64MSB - -- : BFD_RELOC_IA64_PCREL64LSB - -- : BFD_RELOC_IA64_LTOFF_FPTR22 - -- : BFD_RELOC_IA64_LTOFF_FPTR64I - -- : BFD_RELOC_IA64_LTOFF_FPTR32MSB - -- : BFD_RELOC_IA64_LTOFF_FPTR32LSB - -- : BFD_RELOC_IA64_LTOFF_FPTR64MSB - -- : BFD_RELOC_IA64_LTOFF_FPTR64LSB - -- : BFD_RELOC_IA64_SEGREL32MSB - -- : BFD_RELOC_IA64_SEGREL32LSB - -- : BFD_RELOC_IA64_SEGREL64MSB - -- : BFD_RELOC_IA64_SEGREL64LSB - -- : BFD_RELOC_IA64_SECREL32MSB - -- : BFD_RELOC_IA64_SECREL32LSB - -- : BFD_RELOC_IA64_SECREL64MSB - -- : BFD_RELOC_IA64_SECREL64LSB - -- : BFD_RELOC_IA64_REL32MSB - -- : BFD_RELOC_IA64_REL32LSB - -- : BFD_RELOC_IA64_REL64MSB - -- : BFD_RELOC_IA64_REL64LSB - -- : BFD_RELOC_IA64_LTV32MSB - -- : BFD_RELOC_IA64_LTV32LSB - -- : BFD_RELOC_IA64_LTV64MSB - -- : BFD_RELOC_IA64_LTV64LSB - -- : BFD_RELOC_IA64_IPLTMSB - -- : BFD_RELOC_IA64_IPLTLSB - -- : BFD_RELOC_IA64_COPY - -- : BFD_RELOC_IA64_LTOFF22X - -- : BFD_RELOC_IA64_LDXMOV - -- : BFD_RELOC_IA64_TPREL14 - -- : BFD_RELOC_IA64_TPREL22 - -- : BFD_RELOC_IA64_TPREL64I - -- : BFD_RELOC_IA64_TPREL64MSB - -- : BFD_RELOC_IA64_TPREL64LSB - -- : BFD_RELOC_IA64_LTOFF_TPREL22 - -- : BFD_RELOC_IA64_DTPMOD64MSB - -- : BFD_RELOC_IA64_DTPMOD64LSB - -- : BFD_RELOC_IA64_LTOFF_DTPMOD22 - -- : BFD_RELOC_IA64_DTPREL14 - -- : BFD_RELOC_IA64_DTPREL22 - -- : BFD_RELOC_IA64_DTPREL64I - -- : BFD_RELOC_IA64_DTPREL32MSB - -- : BFD_RELOC_IA64_DTPREL32LSB - -- : BFD_RELOC_IA64_DTPREL64MSB - -- : BFD_RELOC_IA64_DTPREL64LSB - -- : BFD_RELOC_IA64_LTOFF_DTPREL22 + - : BFD_RELOC_IA64_IMM14 + - : BFD_RELOC_IA64_IMM22 + - : BFD_RELOC_IA64_IMM64 + - : BFD_RELOC_IA64_DIR32MSB + - : BFD_RELOC_IA64_DIR32LSB + - : BFD_RELOC_IA64_DIR64MSB + - : BFD_RELOC_IA64_DIR64LSB + - : BFD_RELOC_IA64_GPREL22 + - : BFD_RELOC_IA64_GPREL64I + - : BFD_RELOC_IA64_GPREL32MSB + - : BFD_RELOC_IA64_GPREL32LSB + - : BFD_RELOC_IA64_GPREL64MSB + - : BFD_RELOC_IA64_GPREL64LSB + - : BFD_RELOC_IA64_LTOFF22 + - : BFD_RELOC_IA64_LTOFF64I + - : BFD_RELOC_IA64_PLTOFF22 + - : BFD_RELOC_IA64_PLTOFF64I + - : BFD_RELOC_IA64_PLTOFF64MSB + - : BFD_RELOC_IA64_PLTOFF64LSB + - : BFD_RELOC_IA64_FPTR64I + - : BFD_RELOC_IA64_FPTR32MSB + - : BFD_RELOC_IA64_FPTR32LSB + - : BFD_RELOC_IA64_FPTR64MSB + - : BFD_RELOC_IA64_FPTR64LSB + - : BFD_RELOC_IA64_PCREL21B + - : BFD_RELOC_IA64_PCREL21BI + - : BFD_RELOC_IA64_PCREL21M + - : BFD_RELOC_IA64_PCREL21F + - : BFD_RELOC_IA64_PCREL22 + - : BFD_RELOC_IA64_PCREL60B + - : BFD_RELOC_IA64_PCREL64I + - : BFD_RELOC_IA64_PCREL32MSB + - : BFD_RELOC_IA64_PCREL32LSB + - : BFD_RELOC_IA64_PCREL64MSB + - : BFD_RELOC_IA64_PCREL64LSB + - : BFD_RELOC_IA64_LTOFF_FPTR22 + - : BFD_RELOC_IA64_LTOFF_FPTR64I + - : BFD_RELOC_IA64_LTOFF_FPTR32MSB + - : BFD_RELOC_IA64_LTOFF_FPTR32LSB + - : BFD_RELOC_IA64_LTOFF_FPTR64MSB + - : BFD_RELOC_IA64_LTOFF_FPTR64LSB + - : BFD_RELOC_IA64_SEGREL32MSB + - : BFD_RELOC_IA64_SEGREL32LSB + - : BFD_RELOC_IA64_SEGREL64MSB + - : BFD_RELOC_IA64_SEGREL64LSB + - : BFD_RELOC_IA64_SECREL32MSB + - : BFD_RELOC_IA64_SECREL32LSB + - : BFD_RELOC_IA64_SECREL64MSB + - : BFD_RELOC_IA64_SECREL64LSB + - : BFD_RELOC_IA64_REL32MSB + - : BFD_RELOC_IA64_REL32LSB + - : BFD_RELOC_IA64_REL64MSB + - : BFD_RELOC_IA64_REL64LSB + - : BFD_RELOC_IA64_LTV32MSB + - : BFD_RELOC_IA64_LTV32LSB + - : BFD_RELOC_IA64_LTV64MSB + - : BFD_RELOC_IA64_LTV64LSB + - : BFD_RELOC_IA64_IPLTMSB + - : BFD_RELOC_IA64_IPLTLSB + - : BFD_RELOC_IA64_COPY + - : BFD_RELOC_IA64_LTOFF22X + - : BFD_RELOC_IA64_LDXMOV + - : BFD_RELOC_IA64_TPREL14 + - : BFD_RELOC_IA64_TPREL22 + - : BFD_RELOC_IA64_TPREL64I + - : BFD_RELOC_IA64_TPREL64MSB + - : BFD_RELOC_IA64_TPREL64LSB + - : BFD_RELOC_IA64_LTOFF_TPREL22 + - : BFD_RELOC_IA64_DTPMOD64MSB + - : BFD_RELOC_IA64_DTPMOD64LSB + - : BFD_RELOC_IA64_LTOFF_DTPMOD22 + - : BFD_RELOC_IA64_DTPREL14 + - : BFD_RELOC_IA64_DTPREL22 + - : BFD_RELOC_IA64_DTPREL64I + - : BFD_RELOC_IA64_DTPREL32MSB + - : BFD_RELOC_IA64_DTPREL32LSB + - : BFD_RELOC_IA64_DTPREL64MSB + - : BFD_RELOC_IA64_DTPREL64LSB + - : BFD_RELOC_IA64_LTOFF_DTPREL22 Intel IA64 Relocations. - -- : BFD_RELOC_M68HC11_HI8 + - : BFD_RELOC_M68HC11_HI8 Motorola 68HC11 reloc. This is the 8 bit high part of an absolute address. - -- : BFD_RELOC_M68HC11_LO8 + - : BFD_RELOC_M68HC11_LO8 Motorola 68HC11 reloc. This is the 8 bit low part of an absolute address. - -- : BFD_RELOC_M68HC11_3B + - : BFD_RELOC_M68HC11_3B Motorola 68HC11 reloc. This is the 3 bit of a value. - -- : BFD_RELOC_M68HC11_RL_JUMP + - : BFD_RELOC_M68HC11_RL_JUMP Motorola 68HC11 reloc. This reloc marks the beginning of a jump/call instruction. It is used for linker relaxation to correctly identify beginning of instruction and change some branches to use PC-relative addressing mode. - -- : BFD_RELOC_M68HC11_RL_GROUP + - : BFD_RELOC_M68HC11_RL_GROUP Motorola 68HC11 reloc. This reloc marks a group of several instructions that gcc generates and for which the linker relaxation pass can modify and/or remove some of them. - -- : BFD_RELOC_M68HC11_LO16 + - : BFD_RELOC_M68HC11_LO16 Motorola 68HC11 reloc. This is the 16-bit lower part of an address. It is used for 'call' instruction to specify the symbol address without any special transformation (due to memory bank window). - -- : BFD_RELOC_M68HC11_PAGE + - : BFD_RELOC_M68HC11_PAGE Motorola 68HC11 reloc. This is a 8-bit reloc that specifies the page number of an address. It is used by 'call' instruction to specify the page number of the symbol. - -- : BFD_RELOC_M68HC11_24 + - : BFD_RELOC_M68HC11_24 Motorola 68HC11 reloc. This is a 24-bit reloc that represents the address with a 16-bit value and a 8-bit page number. The symbol address is transformed to follow the 16K memory bank of 68HC12 (seen as mapped in the window). - -- : BFD_RELOC_M68HC12_5B + - : BFD_RELOC_M68HC12_5B Motorola 68HC12 reloc. This is the 5 bits of a value. - -- : BFD_RELOC_16C_NUM08 - -- : BFD_RELOC_16C_NUM08_C - -- : BFD_RELOC_16C_NUM16 - -- : BFD_RELOC_16C_NUM16_C - -- : BFD_RELOC_16C_NUM32 - -- : BFD_RELOC_16C_NUM32_C - -- : BFD_RELOC_16C_DISP04 - -- : BFD_RELOC_16C_DISP04_C - -- : BFD_RELOC_16C_DISP08 - -- : BFD_RELOC_16C_DISP08_C - -- : BFD_RELOC_16C_DISP16 - -- : BFD_RELOC_16C_DISP16_C - -- : BFD_RELOC_16C_DISP24 - -- : BFD_RELOC_16C_DISP24_C - -- : BFD_RELOC_16C_DISP24a - -- : BFD_RELOC_16C_DISP24a_C - -- : BFD_RELOC_16C_REG04 - -- : BFD_RELOC_16C_REG04_C - -- : BFD_RELOC_16C_REG04a - -- : BFD_RELOC_16C_REG04a_C - -- : BFD_RELOC_16C_REG14 - -- : BFD_RELOC_16C_REG14_C - -- : BFD_RELOC_16C_REG16 - -- : BFD_RELOC_16C_REG16_C - -- : BFD_RELOC_16C_REG20 - -- : BFD_RELOC_16C_REG20_C - -- : BFD_RELOC_16C_ABS20 - -- : BFD_RELOC_16C_ABS20_C - -- : BFD_RELOC_16C_ABS24 - -- : BFD_RELOC_16C_ABS24_C - -- : BFD_RELOC_16C_IMM04 - -- : BFD_RELOC_16C_IMM04_C - -- : BFD_RELOC_16C_IMM16 - -- : BFD_RELOC_16C_IMM16_C - -- : BFD_RELOC_16C_IMM20 - -- : BFD_RELOC_16C_IMM20_C - -- : BFD_RELOC_16C_IMM24 - -- : BFD_RELOC_16C_IMM24_C - -- : BFD_RELOC_16C_IMM32 - -- : BFD_RELOC_16C_IMM32_C + - : BFD_RELOC_16C_NUM08 + - : BFD_RELOC_16C_NUM08_C + - : BFD_RELOC_16C_NUM16 + - : BFD_RELOC_16C_NUM16_C + - : BFD_RELOC_16C_NUM32 + - : BFD_RELOC_16C_NUM32_C + - : BFD_RELOC_16C_DISP04 + - : BFD_RELOC_16C_DISP04_C + - : BFD_RELOC_16C_DISP08 + - : BFD_RELOC_16C_DISP08_C + - : BFD_RELOC_16C_DISP16 + - : BFD_RELOC_16C_DISP16_C + - : BFD_RELOC_16C_DISP24 + - : BFD_RELOC_16C_DISP24_C + - : BFD_RELOC_16C_DISP24a + - : BFD_RELOC_16C_DISP24a_C + - : BFD_RELOC_16C_REG04 + - : BFD_RELOC_16C_REG04_C + - : BFD_RELOC_16C_REG04a + - : BFD_RELOC_16C_REG04a_C + - : BFD_RELOC_16C_REG14 + - : BFD_RELOC_16C_REG14_C + - : BFD_RELOC_16C_REG16 + - : BFD_RELOC_16C_REG16_C + - : BFD_RELOC_16C_REG20 + - : BFD_RELOC_16C_REG20_C + - : BFD_RELOC_16C_ABS20 + - : BFD_RELOC_16C_ABS20_C + - : BFD_RELOC_16C_ABS24 + - : BFD_RELOC_16C_ABS24_C + - : BFD_RELOC_16C_IMM04 + - : BFD_RELOC_16C_IMM04_C + - : BFD_RELOC_16C_IMM16 + - : BFD_RELOC_16C_IMM16_C + - : BFD_RELOC_16C_IMM20 + - : BFD_RELOC_16C_IMM20_C + - : BFD_RELOC_16C_IMM24 + - : BFD_RELOC_16C_IMM24_C + - : BFD_RELOC_16C_IMM32 + - : BFD_RELOC_16C_IMM32_C NS CR16C Relocations. - -- : BFD_RELOC_CRX_REL4 - -- : BFD_RELOC_CRX_REL8 - -- : BFD_RELOC_CRX_REL8_CMP - -- : BFD_RELOC_CRX_REL16 - -- : BFD_RELOC_CRX_REL24 - -- : BFD_RELOC_CRX_REL32 - -- : BFD_RELOC_CRX_REGREL12 - -- : BFD_RELOC_CRX_REGREL22 - -- : BFD_RELOC_CRX_REGREL28 - -- : BFD_RELOC_CRX_REGREL32 - -- : BFD_RELOC_CRX_ABS16 - -- : BFD_RELOC_CRX_ABS32 - -- : BFD_RELOC_CRX_NUM8 - -- : BFD_RELOC_CRX_NUM16 - -- : BFD_RELOC_CRX_NUM32 - -- : BFD_RELOC_CRX_IMM16 - -- : BFD_RELOC_CRX_IMM32 - -- : BFD_RELOC_CRX_SWITCH8 - -- : BFD_RELOC_CRX_SWITCH16 - -- : BFD_RELOC_CRX_SWITCH32 + - : BFD_RELOC_CRX_REL4 + - : BFD_RELOC_CRX_REL8 + - : BFD_RELOC_CRX_REL8_CMP + - : BFD_RELOC_CRX_REL16 + - : BFD_RELOC_CRX_REL24 + - : BFD_RELOC_CRX_REL32 + - : BFD_RELOC_CRX_REGREL12 + - : BFD_RELOC_CRX_REGREL22 + - : BFD_RELOC_CRX_REGREL28 + - : BFD_RELOC_CRX_REGREL32 + - : BFD_RELOC_CRX_ABS16 + - : BFD_RELOC_CRX_ABS32 + - : BFD_RELOC_CRX_NUM8 + - : BFD_RELOC_CRX_NUM16 + - : BFD_RELOC_CRX_NUM32 + - : BFD_RELOC_CRX_IMM16 + - : BFD_RELOC_CRX_IMM32 + - : BFD_RELOC_CRX_SWITCH8 + - : BFD_RELOC_CRX_SWITCH16 + - : BFD_RELOC_CRX_SWITCH32 NS CRX Relocations. - -- : BFD_RELOC_CRIS_BDISP8 - -- : BFD_RELOC_CRIS_UNSIGNED_5 - -- : BFD_RELOC_CRIS_SIGNED_6 - -- : BFD_RELOC_CRIS_UNSIGNED_6 - -- : BFD_RELOC_CRIS_SIGNED_8 - -- : BFD_RELOC_CRIS_UNSIGNED_8 - -- : BFD_RELOC_CRIS_SIGNED_16 - -- : BFD_RELOC_CRIS_UNSIGNED_16 - -- : BFD_RELOC_CRIS_LAPCQ_OFFSET - -- : BFD_RELOC_CRIS_UNSIGNED_4 + - : BFD_RELOC_CRIS_BDISP8 + - : BFD_RELOC_CRIS_UNSIGNED_5 + - : BFD_RELOC_CRIS_SIGNED_6 + - : BFD_RELOC_CRIS_UNSIGNED_6 + - : BFD_RELOC_CRIS_SIGNED_8 + - : BFD_RELOC_CRIS_UNSIGNED_8 + - : BFD_RELOC_CRIS_SIGNED_16 + - : BFD_RELOC_CRIS_UNSIGNED_16 + - : BFD_RELOC_CRIS_LAPCQ_OFFSET + - : BFD_RELOC_CRIS_UNSIGNED_4 These relocs are only used within the CRIS assembler. They are not (at present) written to any object files. - -- : BFD_RELOC_CRIS_COPY - -- : BFD_RELOC_CRIS_GLOB_DAT - -- : BFD_RELOC_CRIS_JUMP_SLOT - -- : BFD_RELOC_CRIS_RELATIVE + - : BFD_RELOC_CRIS_COPY + - : BFD_RELOC_CRIS_GLOB_DAT + - : BFD_RELOC_CRIS_JUMP_SLOT + - : BFD_RELOC_CRIS_RELATIVE Relocs used in ELF shared libraries for CRIS. - -- : BFD_RELOC_CRIS_32_GOT + - : BFD_RELOC_CRIS_32_GOT 32-bit offset to symbol-entry within GOT. - -- : BFD_RELOC_CRIS_16_GOT + - : BFD_RELOC_CRIS_16_GOT 16-bit offset to symbol-entry within GOT. - -- : BFD_RELOC_CRIS_32_GOTPLT + - : BFD_RELOC_CRIS_32_GOTPLT 32-bit offset to symbol-entry within GOT, with PLT handling. - -- : BFD_RELOC_CRIS_16_GOTPLT + - : BFD_RELOC_CRIS_16_GOTPLT 16-bit offset to symbol-entry within GOT, with PLT handling. - -- : BFD_RELOC_CRIS_32_GOTREL + - : BFD_RELOC_CRIS_32_GOTREL 32-bit offset to symbol, relative to GOT. - -- : BFD_RELOC_CRIS_32_PLT_GOTREL + - : BFD_RELOC_CRIS_32_PLT_GOTREL 32-bit offset to symbol with PLT entry, relative to GOT. - -- : BFD_RELOC_CRIS_32_PLT_PCREL + - : BFD_RELOC_CRIS_32_PLT_PCREL 32-bit offset to symbol with PLT entry, relative to this relocation. - -- : BFD_RELOC_860_COPY - -- : BFD_RELOC_860_GLOB_DAT - -- : BFD_RELOC_860_JUMP_SLOT - -- : BFD_RELOC_860_RELATIVE - -- : BFD_RELOC_860_PC26 - -- : BFD_RELOC_860_PLT26 - -- : BFD_RELOC_860_PC16 - -- : BFD_RELOC_860_LOW0 - -- : BFD_RELOC_860_SPLIT0 - -- : BFD_RELOC_860_LOW1 - -- : BFD_RELOC_860_SPLIT1 - -- : BFD_RELOC_860_LOW2 - -- : BFD_RELOC_860_SPLIT2 - -- : BFD_RELOC_860_LOW3 - -- : BFD_RELOC_860_LOGOT0 - -- : BFD_RELOC_860_SPGOT0 - -- : BFD_RELOC_860_LOGOT1 - -- : BFD_RELOC_860_SPGOT1 - -- : BFD_RELOC_860_LOGOTOFF0 - -- : BFD_RELOC_860_SPGOTOFF0 - -- : BFD_RELOC_860_LOGOTOFF1 - -- : BFD_RELOC_860_SPGOTOFF1 - -- : BFD_RELOC_860_LOGOTOFF2 - -- : BFD_RELOC_860_LOGOTOFF3 - -- : BFD_RELOC_860_LOPC - -- : BFD_RELOC_860_HIGHADJ - -- : BFD_RELOC_860_HAGOT - -- : BFD_RELOC_860_HAGOTOFF - -- : BFD_RELOC_860_HAPC - -- : BFD_RELOC_860_HIGH - -- : BFD_RELOC_860_HIGOT - -- : BFD_RELOC_860_HIGOTOFF + - : BFD_RELOC_860_COPY + - : BFD_RELOC_860_GLOB_DAT + - : BFD_RELOC_860_JUMP_SLOT + - : BFD_RELOC_860_RELATIVE + - : BFD_RELOC_860_PC26 + - : BFD_RELOC_860_PLT26 + - : BFD_RELOC_860_PC16 + - : BFD_RELOC_860_LOW0 + - : BFD_RELOC_860_SPLIT0 + - : BFD_RELOC_860_LOW1 + - : BFD_RELOC_860_SPLIT1 + - : BFD_RELOC_860_LOW2 + - : BFD_RELOC_860_SPLIT2 + - : BFD_RELOC_860_LOW3 + - : BFD_RELOC_860_LOGOT0 + - : BFD_RELOC_860_SPGOT0 + - : BFD_RELOC_860_LOGOT1 + - : BFD_RELOC_860_SPGOT1 + - : BFD_RELOC_860_LOGOTOFF0 + - : BFD_RELOC_860_SPGOTOFF0 + - : BFD_RELOC_860_LOGOTOFF1 + - : BFD_RELOC_860_SPGOTOFF1 + - : BFD_RELOC_860_LOGOTOFF2 + - : BFD_RELOC_860_LOGOTOFF3 + - : BFD_RELOC_860_LOPC + - : BFD_RELOC_860_HIGHADJ + - : BFD_RELOC_860_HAGOT + - : BFD_RELOC_860_HAGOTOFF + - : BFD_RELOC_860_HAPC + - : BFD_RELOC_860_HIGH + - : BFD_RELOC_860_HIGOT + - : BFD_RELOC_860_HIGOTOFF Intel i860 Relocations. - -- : BFD_RELOC_OPENRISC_ABS_26 - -- : BFD_RELOC_OPENRISC_REL_26 + - : BFD_RELOC_SPU_IMM7 + - : BFD_RELOC_SPU_IMM8 + - : BFD_RELOC_SPU_IMM10 + - : BFD_RELOC_SPU_IMM10W + - : BFD_RELOC_SPU_IMM16 + - : BFD_RELOC_SPU_IMM16W + - : BFD_RELOC_SPU_IMM18 + - : BFD_RELOC_SPU_PCREL9a + - : BFD_RELOC_SPU_PCREL9b + - : BFD_RELOC_SPU_PCREL16 + - : BFD_RELOC_SPU_LO16 + - : BFD_RELOC_SPU_HI16 + SPU Relocations. + + - : BFD_RELOC_OPENRISC_ABS_26 + - : BFD_RELOC_OPENRISC_REL_26 OpenRISC Relocations. - -- : BFD_RELOC_H8_DIR16A8 - -- : BFD_RELOC_H8_DIR16R8 - -- : BFD_RELOC_H8_DIR24A8 - -- : BFD_RELOC_H8_DIR24R8 - -- : BFD_RELOC_H8_DIR32A16 + - : BFD_RELOC_H8_DIR16A8 + - : BFD_RELOC_H8_DIR16R8 + - : BFD_RELOC_H8_DIR24A8 + - : BFD_RELOC_H8_DIR24R8 + - : BFD_RELOC_H8_DIR32A16 H8 elf Relocations. - -- : BFD_RELOC_XSTORMY16_REL_12 - -- : BFD_RELOC_XSTORMY16_12 - -- : BFD_RELOC_XSTORMY16_24 - -- : BFD_RELOC_XSTORMY16_FPTR16 + - : BFD_RELOC_XSTORMY16_REL_12 + - : BFD_RELOC_XSTORMY16_12 + - : BFD_RELOC_XSTORMY16_24 + - : BFD_RELOC_XSTORMY16_FPTR16 Sony Xstormy16 Relocations. - -- : BFD_RELOC_VAX_GLOB_DAT - -- : BFD_RELOC_VAX_JMP_SLOT - -- : BFD_RELOC_VAX_RELATIVE + - : BFD_RELOC_VAX_GLOB_DAT + - : BFD_RELOC_VAX_JMP_SLOT + - : BFD_RELOC_VAX_RELATIVE Relocations used by VAX ELF. - -- : BFD_RELOC_MSP430_10_PCREL - -- : BFD_RELOC_MSP430_16_PCREL - -- : BFD_RELOC_MSP430_16 - -- : BFD_RELOC_MSP430_16_PCREL_BYTE - -- : BFD_RELOC_MSP430_16_BYTE - -- : BFD_RELOC_MSP430_2X_PCREL - -- : BFD_RELOC_MSP430_RL_PCREL + - : BFD_RELOC_MSP430_10_PCREL + - : BFD_RELOC_MSP430_16_PCREL + - : BFD_RELOC_MSP430_16 + - : BFD_RELOC_MSP430_16_PCREL_BYTE + - : BFD_RELOC_MSP430_16_BYTE + - : BFD_RELOC_MSP430_2X_PCREL + - : BFD_RELOC_MSP430_RL_PCREL msp430 specific relocation codes - -- : BFD_RELOC_IQ2000_OFFSET_16 - -- : BFD_RELOC_IQ2000_OFFSET_21 - -- : BFD_RELOC_IQ2000_UHI16 + - : BFD_RELOC_IQ2000_OFFSET_16 + - : BFD_RELOC_IQ2000_OFFSET_21 + - : BFD_RELOC_IQ2000_UHI16 IQ2000 Relocations. - -- : BFD_RELOC_XTENSA_RTLD + - : BFD_RELOC_XTENSA_RTLD Special Xtensa relocation used only by PLT entries in ELF shared objects to indicate that the runtime linker should set the value to one of its own internal functions or data structures. - -- : BFD_RELOC_XTENSA_GLOB_DAT - -- : BFD_RELOC_XTENSA_JMP_SLOT - -- : BFD_RELOC_XTENSA_RELATIVE + - : BFD_RELOC_XTENSA_GLOB_DAT + - : BFD_RELOC_XTENSA_JMP_SLOT + - : BFD_RELOC_XTENSA_RELATIVE Xtensa relocations for ELF shared objects. - -- : BFD_RELOC_XTENSA_PLT + - : BFD_RELOC_XTENSA_PLT Xtensa relocation used in ELF object files for symbols that may require PLT entries. Otherwise, this is just a generic 32-bit relocation. - -- : BFD_RELOC_XTENSA_DIFF8 - -- : BFD_RELOC_XTENSA_DIFF16 - -- : BFD_RELOC_XTENSA_DIFF32 + - : BFD_RELOC_XTENSA_DIFF8 + - : BFD_RELOC_XTENSA_DIFF16 + - : BFD_RELOC_XTENSA_DIFF32 Xtensa relocations to mark the difference of two local symbols. These are only needed to support linker relaxation and can be ignored when not relaxing. The field is set to the value of the @@ -4536,95 +4551,95 @@ position of the first symbol so the linker can determine whether to adjust the field value. - -- : BFD_RELOC_XTENSA_SLOT0_OP - -- : BFD_RELOC_XTENSA_SLOT1_OP - -- : BFD_RELOC_XTENSA_SLOT2_OP - -- : BFD_RELOC_XTENSA_SLOT3_OP - -- : BFD_RELOC_XTENSA_SLOT4_OP - -- : BFD_RELOC_XTENSA_SLOT5_OP - -- : BFD_RELOC_XTENSA_SLOT6_OP - -- : BFD_RELOC_XTENSA_SLOT7_OP - -- : BFD_RELOC_XTENSA_SLOT8_OP - -- : BFD_RELOC_XTENSA_SLOT9_OP - -- : BFD_RELOC_XTENSA_SLOT10_OP - -- : BFD_RELOC_XTENSA_SLOT11_OP - -- : BFD_RELOC_XTENSA_SLOT12_OP - -- : BFD_RELOC_XTENSA_SLOT13_OP - -- : BFD_RELOC_XTENSA_SLOT14_OP + - : BFD_RELOC_XTENSA_SLOT0_OP + - : BFD_RELOC_XTENSA_SLOT1_OP + - : BFD_RELOC_XTENSA_SLOT2_OP + - : BFD_RELOC_XTENSA_SLOT3_OP + - : BFD_RELOC_XTENSA_SLOT4_OP + - : BFD_RELOC_XTENSA_SLOT5_OP + - : BFD_RELOC_XTENSA_SLOT6_OP + - : BFD_RELOC_XTENSA_SLOT7_OP + - : BFD_RELOC_XTENSA_SLOT8_OP + - : BFD_RELOC_XTENSA_SLOT9_OP + - : BFD_RELOC_XTENSA_SLOT10_OP + - : BFD_RELOC_XTENSA_SLOT11_OP + - : BFD_RELOC_XTENSA_SLOT12_OP + - : BFD_RELOC_XTENSA_SLOT13_OP + - : BFD_RELOC_XTENSA_SLOT14_OP Generic Xtensa relocations for instruction operands. Only the slot number is encoded in the relocation. The relocation applies to the last PC-relative immediate operand, or if there are no PC-relative immediates, to the last immediate operand. - -- : BFD_RELOC_XTENSA_SLOT0_ALT - -- : BFD_RELOC_XTENSA_SLOT1_ALT - -- : BFD_RELOC_XTENSA_SLOT2_ALT - -- : BFD_RELOC_XTENSA_SLOT3_ALT - -- : BFD_RELOC_XTENSA_SLOT4_ALT - -- : BFD_RELOC_XTENSA_SLOT5_ALT - -- : BFD_RELOC_XTENSA_SLOT6_ALT - -- : BFD_RELOC_XTENSA_SLOT7_ALT - -- : BFD_RELOC_XTENSA_SLOT8_ALT - -- : BFD_RELOC_XTENSA_SLOT9_ALT - -- : BFD_RELOC_XTENSA_SLOT10_ALT - -- : BFD_RELOC_XTENSA_SLOT11_ALT - -- : BFD_RELOC_XTENSA_SLOT12_ALT - -- : BFD_RELOC_XTENSA_SLOT13_ALT - -- : BFD_RELOC_XTENSA_SLOT14_ALT + - : BFD_RELOC_XTENSA_SLOT0_ALT + - : BFD_RELOC_XTENSA_SLOT1_ALT + - : BFD_RELOC_XTENSA_SLOT2_ALT + - : BFD_RELOC_XTENSA_SLOT3_ALT + - : BFD_RELOC_XTENSA_SLOT4_ALT + - : BFD_RELOC_XTENSA_SLOT5_ALT + - : BFD_RELOC_XTENSA_SLOT6_ALT + - : BFD_RELOC_XTENSA_SLOT7_ALT + - : BFD_RELOC_XTENSA_SLOT8_ALT + - : BFD_RELOC_XTENSA_SLOT9_ALT + - : BFD_RELOC_XTENSA_SLOT10_ALT + - : BFD_RELOC_XTENSA_SLOT11_ALT + - : BFD_RELOC_XTENSA_SLOT12_ALT + - : BFD_RELOC_XTENSA_SLOT13_ALT + - : BFD_RELOC_XTENSA_SLOT14_ALT Alternate Xtensa relocations. Only the slot is encoded in the relocation. The meaning of these relocations is opcode-specific. - -- : BFD_RELOC_XTENSA_OP0 - -- : BFD_RELOC_XTENSA_OP1 - -- : BFD_RELOC_XTENSA_OP2 + - : BFD_RELOC_XTENSA_OP0 + - : BFD_RELOC_XTENSA_OP1 + - : BFD_RELOC_XTENSA_OP2 Xtensa relocations for backward compatibility. These have all been replaced by BFD_RELOC_XTENSA_SLOT0_OP. - -- : BFD_RELOC_XTENSA_ASM_EXPAND + - : BFD_RELOC_XTENSA_ASM_EXPAND Xtensa relocation to mark that the assembler expanded the instructions from an original target. The expansion size is encoded in the reloc size. - -- : BFD_RELOC_XTENSA_ASM_SIMPLIFY + - : BFD_RELOC_XTENSA_ASM_SIMPLIFY Xtensa relocation to mark that the linker should simplify assembler-expanded instructions. This is commonly used internally by the linker after analysis of a BFD_RELOC_XTENSA_ASM_EXPAND. typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; - -2.11.0.2 `bfd_reloc_type_lookup' -................................ -*Synopsis* +`bfd_reloc_type_lookup' +....................... + + *Synopsis* reloc_howto_type *bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); *Description* Return a pointer to a howto structure which, when invoked, will perform the relocation CODE on data from the architecture noted. -2.11.0.3 `bfd_default_reloc_type_lookup' -........................................ +`bfd_default_reloc_type_lookup' +............................... -*Synopsis* + *Synopsis* reloc_howto_type *bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); *Description* Provides a default relocation lookup routine for any architecture. -2.11.0.4 `bfd_get_reloc_code_name' -.................................. +`bfd_get_reloc_code_name' +......................... -*Synopsis* + *Synopsis* const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); *Description* Provides a printable name for the supplied relocation code. Useful mainly for printing error messages. -2.11.0.5 `bfd_generic_relax_section' -.................................... +`bfd_generic_relax_section' +........................... -*Synopsis* + *Synopsis* bfd_boolean bfd_generic_relax_section (bfd *abfd, asection *section, @@ -4634,30 +4649,30 @@ Provides default handling for relaxing for back ends which don't do relaxing. -2.11.0.6 `bfd_generic_gc_sections' -.................................. +`bfd_generic_gc_sections' +......................... -*Synopsis* + *Synopsis* bfd_boolean bfd_generic_gc_sections (bfd *, struct bfd_link_info *); *Description* Provides default handling for relaxing for back ends which don't do section gc - i.e., does nothing. -2.11.0.7 `bfd_generic_merge_sections' -..................................... +`bfd_generic_merge_sections' +............................ -*Synopsis* + *Synopsis* bfd_boolean bfd_generic_merge_sections (bfd *, struct bfd_link_info *); *Description* Provides default handling for SEC_MERGE section merging for back ends which don't have SEC_MERGE support - i.e., does nothing. -2.11.0.8 `bfd_generic_get_relocated_section_contents' -..................................................... +`bfd_generic_get_relocated_section_contents' +............................................ -*Synopsis* + *Synopsis* bfd_byte *bfd_generic_get_relocated_section_contents (bfd *abfd, struct bfd_link_info *link_info, @@ -4672,34 +4687,34 @@  File: bfd.info, Node: Core Files, Next: Targets, Prev: Relocations, Up: BFD front end -2.12 Core files -=============== +Core files +========== -*Description* + *Description* These are functions pertaining to core files. -2.12.0.1 `bfd_core_file_failing_command' -........................................ +`bfd_core_file_failing_command' +............................... -*Synopsis* + *Synopsis* const char *bfd_core_file_failing_command (bfd *abfd); *Description* Return a read-only string explaining which program was running when it failed and produced the core file ABFD. -2.12.0.2 `bfd_core_file_failing_signal' -....................................... +`bfd_core_file_failing_signal' +.............................. -*Synopsis* + *Synopsis* int bfd_core_file_failing_signal (bfd *abfd); *Description* Returns the signal number which caused the core dump which generated the file the BFD ABFD is attached to. -2.12.0.3 `core_file_matches_executable_p' -......................................... +`core_file_matches_executable_p' +................................ -*Synopsis* + *Synopsis* bfd_boolean core_file_matches_executable_p (bfd *core_bfd, bfd *exec_bfd); *Description* @@ -4709,10 +4724,10 @@  File: bfd.info, Node: Targets, Next: Architectures, Prev: Core Files, Up: BFD front end -2.13 Targets -============ +Targets +======= -*Description* + *Description* Each port of BFD to a different machine requires the creation of a target back end. All the back end provides to the root part of BFD is a structure containing pointers to functions which perform certain low @@ -4759,10 +4774,10 @@  File: bfd.info, Node: bfd_target, Prev: Targets, Up: Targets -2.13.1 bfd_target ------------------ +bfd_target +---------- -*Description* + *Description* This structure contains everything that BFD knows about a target. It includes things like its byte order, name, and which routines to call to do various operations. @@ -4779,7 +4794,7 @@ wants to fix this and not break the above, please do. #define BFD_SEND(bfd, message, arglist) \ ((*((bfd)->xvec->message)) arglist) - + #ifdef DEBUG_BFD_SEND #undef BFD_SEND #define BFD_SEND(bfd, message, arglist) \ @@ -4790,7 +4805,7 @@ For operations which index on the BFD format: #define BFD_SEND_FMT(bfd, message, arglist) \ (((bfd)->xvec->message[(int) ((bfd)->format)]) arglist) - + #ifdef DEBUG_BFD_SEND #undef BFD_SEND_FMT #define BFD_SEND_FMT(bfd, message, arglist) \ @@ -4831,45 +4846,45 @@ bfd_target_pef_xlib_flavour, bfd_target_sym_flavour }; - + enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN }; - + /* Forward declaration. */ typedef struct bfd_link_info _bfd_link_info; - + typedef struct bfd_target { /* Identifies the kind of target, e.g., SunOS4, Ultrix, etc. */ char *name; - + /* The "flavour" of a back end is a general indication about the contents of a file. */ enum bfd_flavour flavour; - + /* The order of bytes within the data area of a file. */ enum bfd_endian byteorder; - + /* The order of bytes within the header parts of a file. */ enum bfd_endian header_byteorder; - + /* A mask of all the flags which an executable may have set - from the set `BFD_NO_FLAGS', `HAS_RELOC', ...`D_PAGED'. */ flagword object_flags; - + /* A mask of all the flags which a section may have set - from the set `SEC_NO_FLAGS', `SEC_ALLOC', ...`SET_NEVER_LOAD'. */ flagword section_flags; - + /* The character normally found at the front of a symbol. (if any), perhaps `_'. */ char symbol_leading_char; - + /* The pad character for file names within an archive header. */ char ar_pad_char; - + /* The maximum number of characters in an archive header. */ unsigned short ar_max_namelen; - + /* Entries for byte swapping for data. These are different from the other entry points, since they don't take a BFD as the first argument. Certain other handlers could do the same. */ @@ -4882,7 +4897,7 @@ bfd_vma (*bfd_getx16) (const void *); bfd_signed_vma (*bfd_getx_signed_16) (const void *); void (*bfd_putx16) (bfd_vma, void *); - + /* Byte swapping for the headers. */ bfd_uint64_t (*bfd_h_getx64) (const void *); bfd_int64_t (*bfd_h_getx_signed_64) (const void *); @@ -4893,16 +4908,16 @@ bfd_vma (*bfd_h_getx16) (const void *); bfd_signed_vma (*bfd_h_getx_signed_16) (const void *); void (*bfd_h_putx16) (bfd_vma, void *); - + /* Format dependent routines: these are vectors of entry points within the target vector structure, one for each format to check. */ - + /* Check the format of a file being read. Return a `bfd_target *' or zero. */ const struct bfd_target *(*_bfd_check_format[bfd_type_end]) (bfd *); - + /* Set the format of a file being written. */ bfd_boolean (*_bfd_set_format[bfd_type_end]) (bfd *); - + /* Write cached information into a file being written, at `bfd_close'. */ bfd_boolean (*_bfd_write_contents[bfd_type_end]) (bfd *); The general target vector. These vectors are initialized using the @@ -4915,7 +4930,7 @@ NAME##_new_section_hook, \ NAME##_get_section_contents, \ NAME##_get_section_contents_in_window - + /* Called when the BFD is being closed to do any necessary cleanup. */ bfd_boolean (*_close_and_cleanup) (bfd *); /* Ask the BFD to free all cached information. */ @@ -4927,7 +4942,7 @@ (bfd *, sec_ptr, void *, file_ptr, bfd_size_type); bfd_boolean (*_bfd_get_section_contents_in_window) (bfd *, sec_ptr, bfd_window *, file_ptr, bfd_size_type); - + /* Entry points to copy private data. */ #define BFD_JUMP_TABLE_COPY(NAME) \ NAME##_bfd_copy_private_bfd_data, \ @@ -4937,7 +4952,7 @@ NAME##_bfd_copy_private_header_data, \ NAME##_bfd_set_private_flags, \ NAME##_bfd_print_private_bfd_data - + /* Called to copy BFD general private data from one object file to another. */ bfd_boolean (*_bfd_copy_private_bfd_data) (bfd *, bfd *); @@ -4958,20 +4973,20 @@ (bfd *, bfd *); /* Called to set private backend flags. */ bfd_boolean (*_bfd_set_private_flags) (bfd *, flagword); - + /* Called to print private BFD data. */ bfd_boolean (*_bfd_print_private_bfd_data) (bfd *, void *); - + /* Core file entry points. */ #define BFD_JUMP_TABLE_CORE(NAME) \ NAME##_core_file_failing_command, \ NAME##_core_file_failing_signal, \ NAME##_core_file_matches_executable_p - + char * (*_core_file_failing_command) (bfd *); int (*_core_file_failing_signal) (bfd *); bfd_boolean (*_core_file_matches_executable_p) (bfd *, bfd *); - + /* Archive entry points. */ #define BFD_JUMP_TABLE_ARCHIVE(NAME) \ NAME##_slurp_armap, \ @@ -4984,7 +4999,7 @@ NAME##_get_elt_at_index, \ NAME##_generic_stat_arch_elt, \ NAME##_update_armap_timestamp - + bfd_boolean (*_bfd_slurp_armap) (bfd *); bfd_boolean (*_bfd_slurp_extended_name_table) (bfd *); bfd_boolean (*_bfd_construct_extended_name_table) @@ -4998,7 +5013,7 @@ bfd * (*_bfd_get_elt_at_index) (bfd *, symindex); int (*_bfd_stat_arch_elt) (bfd *, struct stat *); bfd_boolean (*_bfd_update_armap_timestamp) (bfd *); - + /* Entry points used for symbols. */ #define BFD_JUMP_TABLE_SYMBOLS(NAME) \ NAME##_get_symtab_upper_bound, \ @@ -5013,7 +5028,7 @@ NAME##_bfd_make_debug_symbol, \ NAME##_read_minisymbols, \ NAME##_minisymbol_to_symbol - + long (*_bfd_get_symtab_upper_bound) (bfd *); long (*_bfd_canonicalize_symtab) (bfd *, struct bfd_symbol **); @@ -5044,30 +5059,30 @@ BFD_SEND (b, _minisymbol_to_symbol, (b, d, m, f)) asymbol * (*_minisymbol_to_symbol) (bfd *, bfd_boolean, const void *, asymbol *); - + /* Routines for relocs. */ #define BFD_JUMP_TABLE_RELOCS(NAME) \ NAME##_get_reloc_upper_bound, \ NAME##_canonicalize_reloc, \ NAME##_bfd_reloc_type_lookup - + long (*_get_reloc_upper_bound) (bfd *, sec_ptr); long (*_bfd_canonicalize_reloc) (bfd *, sec_ptr, arelent **, struct bfd_symbol **); /* See documentation on reloc types. */ reloc_howto_type * (*reloc_type_lookup) (bfd *, bfd_reloc_code_real_type); - + /* Routines used when writing an object file. */ #define BFD_JUMP_TABLE_WRITE(NAME) \ NAME##_set_arch_mach, \ NAME##_set_section_contents - + bfd_boolean (*_bfd_set_arch_mach) (bfd *, enum bfd_architecture, unsigned long); bfd_boolean (*_bfd_set_section_contents) (bfd *, sec_ptr, const void *, file_ptr, bfd_size_type); - + /* Routines used by the linker. */ #define BFD_JUMP_TABLE_LINK(NAME) \ NAME##_sizeof_headers, \ @@ -5084,52 +5099,52 @@ NAME##_bfd_is_group_section, \ NAME##_bfd_discard_group, \ NAME##_section_already_linked \ - + int (*_bfd_sizeof_headers) (bfd *, bfd_boolean); bfd_byte * (*_bfd_get_relocated_section_contents) (bfd *, struct bfd_link_info *, struct bfd_link_order *, bfd_byte *, bfd_boolean, struct bfd_symbol **); - + bfd_boolean (*_bfd_relax_section) (bfd *, struct bfd_section *, struct bfd_link_info *, bfd_boolean *); - + /* Create a hash table for the linker. Different backends store different information in this table. */ struct bfd_link_hash_table * (*_bfd_link_hash_table_create) (bfd *); - + /* Release the memory associated with the linker hash table. */ void (*_bfd_link_hash_table_free) (struct bfd_link_hash_table *); - + /* Add symbols from this object file into the hash table. */ bfd_boolean (*_bfd_link_add_symbols) (bfd *, struct bfd_link_info *); - + /* Indicate that we are only retrieving symbol values from this section. */ void (*_bfd_link_just_syms) (asection *, struct bfd_link_info *); - + /* Do a link based on the link_order structures attached to each section of the BFD. */ bfd_boolean (*_bfd_final_link) (bfd *, struct bfd_link_info *); - + /* Should this section be split up into smaller pieces during linking. */ bfd_boolean (*_bfd_link_split_section) (bfd *, struct bfd_section *); - + /* Remove sections that are not referenced from the output. */ bfd_boolean (*_bfd_gc_sections) (bfd *, struct bfd_link_info *); - + /* Attempt to merge SEC_MERGE sections. */ bfd_boolean (*_bfd_merge_sections) (bfd *, struct bfd_link_info *); - + /* Is this section a member of a group? */ bfd_boolean (*_bfd_is_group_section) (bfd *, const struct bfd_section *); - + /* Discard members of a group. */ bfd_boolean (*_bfd_discard_group) (bfd *, struct bfd_section *); - + /* Check if SEC has been already linked during a reloceatable or final link. */ void (*_section_already_linked) (bfd *, struct bfd_section *); - + /* Routines to handle dynamic symbols and relocs. */ #define BFD_JUMP_TABLE_DYNAMIC(NAME) \ NAME##_get_dynamic_symtab_upper_bound, \ @@ -5137,7 +5152,7 @@ NAME##_get_synthetic_symtab, \ NAME##_get_dynamic_reloc_upper_bound, \ NAME##_canonicalize_dynamic_reloc - + /* Get the amount of memory required to hold the dynamic symbols. */ long (*_bfd_get_dynamic_symtab_upper_bound) (bfd *); /* Read in the dynamic symbols. */ @@ -5159,27 +5174,27 @@ to find an alternative output format that is suitable. /* Opposite endian version of this target. */ const struct bfd_target * alternative_target; - + /* Data for use by back-end routines, which isn't generic enough to belong in this structure. */ const void *backend_data; - + } bfd_target; -2.13.1.1 `bfd_set_default_target' -................................. +`bfd_set_default_target' +........................ -*Synopsis* + *Synopsis* bfd_boolean bfd_set_default_target (const char *name); *Description* Set the default target vector to use when recognizing a BFD. This takes the name of the target, which may be a BFD target name or a configuration triplet. -2.13.1.2 `bfd_find_target' -.......................... +`bfd_find_target' +................. -*Synopsis* + *Synopsis* const bfd_target *bfd_find_target (const char *target_name, bfd *abfd); *Description* Return a pointer to the transfer vector for the object target named @@ -5192,19 +5207,19 @@ `bfd_check_format' to loop over all the targets to find the one that matches the file being read. -2.13.1.3 `bfd_target_list' -.......................... +`bfd_target_list' +................. -*Synopsis* + *Synopsis* const char ** bfd_target_list (void); *Description* Return a freshly malloced NULL-terminated vector of the names of all the valid BFD targets. Do not modify the names. -2.13.1.4 `bfd_seach_for_target' -............................... +`bfd_seach_for_target' +...................... -*Synopsis* + *Synopsis* const bfd_target *bfd_search_for_target (int (*search_func) (const bfd_target *, void *), void *); @@ -5217,10 +5232,10 @@  File: bfd.info, Node: Architectures, Next: Opening and Closing, Prev: Targets, Up: BFD front end -2.14 Architectures -================== +Architectures +============= -BFD keeps one atom in a BFD describing the architecture of the data + BFD keeps one atom in a BFD describing the architecture of the data attached to the BFD: a pointer to a `bfd_arch_info_type'. Pointers to structures can be requested independently of a BFD so @@ -5241,10 +5256,10 @@ BFD's idea of an architecture is implemented in `archures.c'. -2.14.1 bfd_architecture ------------------------ +bfd_architecture +---------------- -*Description* + *Description* This enum gives the object file's CPU architecture, in a global sense--i.e., what processor family does it belong to? Another field indicates which processor within the family is in use. The machine @@ -5283,7 +5298,7 @@ The exception is the "ca", which is incompatible with all other machines except "core". */ - + #define bfd_mach_i960_core 1 #define bfd_mach_i960_ka_sa 2 #define bfd_mach_i960_kb_sb 3 @@ -5292,9 +5307,9 @@ #define bfd_mach_i960_ca 6 #define bfd_mach_i960_jx 7 #define bfd_mach_i960_hx 8 - + bfd_arch_or32, /* OpenRISC 32 */ - + bfd_arch_a29k, /* AMD 29000 */ bfd_arch_sparc, /* SPARC */ #define bfd_mach_sparc 1 @@ -5388,11 +5403,14 @@ #define bfd_mach_ppc_rs64iii 643 #define bfd_mach_ppc_7400 7400 #define bfd_mach_ppc_e500 500 + #define bfd_mach_cell_ppu 501 bfd_arch_rs6000, /* IBM RS/6000 */ #define bfd_mach_rs6k 6000 #define bfd_mach_rs6k_rs1 6001 #define bfd_mach_rs6k_rsc 6003 #define bfd_mach_rs6k_rs2 6002 + bfd_arch_spu, /* PowerPC SPU */ + #define bfd_mach_spu 256 bfd_arch_hppa, /* HP PA RISC */ #define bfd_mach_hppa10 10 #define bfd_mach_hppa11 11 @@ -5545,10 +5563,10 @@ bfd_arch_last }; -2.14.2 bfd_arch_info --------------------- +bfd_arch_info +------------- -*Description* + *Description* This structure contains information on architectures for use within BFD. typedef struct bfd_arch_info @@ -5567,45 +5585,45 @@ bfd_boolean the_default; const struct bfd_arch_info * (*compatible) (const struct bfd_arch_info *a, const struct bfd_arch_info *b); - + bfd_boolean (*scan) (const struct bfd_arch_info *, const char *); - + const struct bfd_arch_info *next; } bfd_arch_info_type; -2.14.2.1 `bfd_printable_name' -............................. +`bfd_printable_name' +.................... -*Synopsis* + *Synopsis* const char *bfd_printable_name (bfd *abfd); *Description* Return a printable string representing the architecture and machine from the pointer to the architecture info structure. -2.14.2.2 `bfd_scan_arch' -........................ +`bfd_scan_arch' +............... -*Synopsis* + *Synopsis* const bfd_arch_info_type *bfd_scan_arch (const char *string); *Description* Figure out if BFD supports any cpu which could be described with the name STRING. Return a pointer to an `arch_info' structure if a machine is found, otherwise NULL. -2.14.2.3 `bfd_arch_list' -........................ +`bfd_arch_list' +............... -*Synopsis* + *Synopsis* const char **bfd_arch_list (void); *Description* Return a freshly malloced NULL-terminated vector of the names of all the valid BFD architectures. Do not modify the names. -2.14.2.4 `bfd_arch_get_compatible' -.................................. +`bfd_arch_get_compatible' +......................... -*Synopsis* + *Synopsis* const bfd_arch_info_type *bfd_arch_get_compatible (const bfd *abfd, const bfd *bbfd, bfd_boolean accept_unknowns); *Description* @@ -5614,28 +5632,28 @@ architectures and machine types implied by the BFDs and returns a pointer to an `arch_info' structure describing the compatible machine. -2.14.2.5 `bfd_default_arch_struct' -.................................. +`bfd_default_arch_struct' +......................... -*Description* + *Description* The `bfd_default_arch_struct' is an item of `bfd_arch_info_type' which has been initialized to a fairly generic state. A BFD starts life by pointing to this structure, until the correct back end has determined the real architecture of the file. extern const bfd_arch_info_type bfd_default_arch_struct; -2.14.2.6 `bfd_set_arch_info' -............................ +`bfd_set_arch_info' +................... -*Synopsis* + *Synopsis* void bfd_set_arch_info (bfd *abfd, const bfd_arch_info_type *arg); *Description* Set the architecture info of ABFD to ARG. -2.14.2.7 `bfd_default_set_arch_mach' -.................................... +`bfd_default_set_arch_mach' +........................... -*Synopsis* + *Synopsis* bfd_boolean bfd_default_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach); *Description* @@ -5643,70 +5661,70 @@ Find the correct pointer to a structure and insert it into the `arch_info' pointer. -2.14.2.8 `bfd_get_arch' -....................... +`bfd_get_arch' +.............. -*Synopsis* + *Synopsis* enum bfd_architecture bfd_get_arch (bfd *abfd); *Description* Return the enumerated type which describes the BFD ABFD's architecture. -2.14.2.9 `bfd_get_mach' -....................... +`bfd_get_mach' +.............. -*Synopsis* + *Synopsis* unsigned long bfd_get_mach (bfd *abfd); *Description* Return the long type which describes the BFD ABFD's machine. -2.14.2.10 `bfd_arch_bits_per_byte' -.................................. +`bfd_arch_bits_per_byte' +........................ -*Synopsis* + *Synopsis* unsigned int bfd_arch_bits_per_byte (bfd *abfd); *Description* Return the number of bits in one of the BFD ABFD's architecture's bytes. -2.14.2.11 `bfd_arch_bits_per_address' -..................................... +`bfd_arch_bits_per_address' +........................... -*Synopsis* + *Synopsis* unsigned int bfd_arch_bits_per_address (bfd *abfd); *Description* Return the number of bits in one of the BFD ABFD's architecture's addresses. -2.14.2.12 `bfd_default_compatible' -.................................. +`bfd_default_compatible' +........................ -*Synopsis* + *Synopsis* const bfd_arch_info_type *bfd_default_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b); *Description* The default function for testing for compatibility. -2.14.2.13 `bfd_default_scan' -............................ +`bfd_default_scan' +.................. -*Synopsis* + *Synopsis* bfd_boolean bfd_default_scan (const struct bfd_arch_info *info, const char *string); *Description* The default function for working out whether this is an architecture hit and a machine hit. -2.14.2.14 `bfd_get_arch_info' -............................. +`bfd_get_arch_info' +................... -*Synopsis* + *Synopsis* const bfd_arch_info_type *bfd_get_arch_info (bfd *abfd); *Description* Return the architecture info struct in ABFD. -2.14.2.15 `bfd_lookup_arch' -........................... +`bfd_lookup_arch' +................. -*Synopsis* + *Synopsis* const bfd_arch_info_type *bfd_lookup_arch (enum bfd_architecture arch, unsigned long machine); *Description* @@ -5714,10 +5732,10 @@ ARCH and MACHINE. A machine of 0 matches the machine/architecture structure which marks itself as the default. -2.14.2.16 `bfd_printable_arch_mach' -................................... +`bfd_printable_arch_mach' +......................... -*Synopsis* + *Synopsis* const char *bfd_printable_arch_mach (enum bfd_architecture arch, unsigned long machine); *Description* @@ -5726,20 +5744,20 @@ This routine is depreciated. -2.14.2.17 `bfd_octets_per_byte' -............................... +`bfd_octets_per_byte' +..................... -*Synopsis* + *Synopsis* unsigned int bfd_octets_per_byte (bfd *abfd); *Description* Return the number of octets (8-bit quantities) per target byte (minimum addressable unit). In most cases, this will be one, but some DSP targets have 16, 32, or even 48 bits per byte. -2.14.2.18 `bfd_arch_mach_octets_per_byte' -......................................... +`bfd_arch_mach_octets_per_byte' +............................... -*Synopsis* + *Synopsis* unsigned int bfd_arch_mach_octets_per_byte (enum bfd_architecture arch, unsigned long machine); *Description* @@ -5751,13 +5769,13 @@  File: bfd.info, Node: Opening and Closing, Next: Internal, Prev: Architectures, Up: BFD front end -2.15 Opening and closing BFDs -============================= +Opening and closing BFDs +======================== -2.15.0.1 `bfd_openr' -.................... +`bfd_openr' +........... -*Synopsis* + *Synopsis* bfd *bfd_openr (const char *filename, const char *target); *Description* Open the file FILENAME (using `fopen') with the target TARGET. Return @@ -5770,10 +5788,10 @@ are `bfd_error_no_memory', `bfd_error_invalid_target' or `system_call' error. -2.15.0.2 `bfd_fdopenr' -...................... +`bfd_fdopenr' +............. -*Synopsis* + *Synopsis* bfd *bfd_fdopenr (const char *filename, const char *target, int fd); *Description* `bfd_fdopenr' is to `bfd_fopenr' much like `fdopen' is to `fopen'. It @@ -5791,19 +5809,19 @@ Possible errors are `bfd_error_no_memory', `bfd_error_invalid_target' and `bfd_error_system_call'. -2.15.0.3 `bfd_openstreamr' -.......................... +`bfd_openstreamr' +................. -*Synopsis* + *Synopsis* bfd *bfd_openstreamr (const char *, const char *, void *); *Description* Open a BFD for read access on an existing stdio stream. When the BFD is passed to `bfd_close', the stream will be closed. -2.15.0.4 `bfd_openr_iovec' -.......................... +`bfd_openr_iovec' +................. -*Synopsis* + *Synopsis* bfd *bfd_openr_iovec (const char *filename, const char *target, void *(*open) (struct bfd *nbfd, void *open_closure), @@ -5840,10 +5858,10 @@ Possible errors are `bfd_error_no_memory', `bfd_error_invalid_target' and `bfd_error_system_call'. -2.15.0.5 `bfd_openw' -.................... +`bfd_openw' +........... -*Synopsis* + *Synopsis* bfd *bfd_openw (const char *filename, const char *target); *Description* Create a BFD, associated with file FILENAME, using the file format @@ -5852,10 +5870,10 @@ Possible errors are `bfd_error_system_call', `bfd_error_no_memory', `bfd_error_invalid_target'. -2.15.0.6 `bfd_close' -.................... +`bfd_close' +........... -*Synopsis* + *Synopsis* bfd_boolean bfd_close (bfd *abfd); *Description* Close a BFD. If the BFD was open for writing, then pending operations @@ -5870,10 +5888,10 @@ *Returns* `TRUE' is returned if all is ok, otherwise `FALSE'. -2.15.0.7 `bfd_close_all_done' -............................. +`bfd_close_all_done' +.................... -*Synopsis* + *Synopsis* bfd_boolean bfd_close_all_done (bfd *); *Description* Close a BFD. Differs from `bfd_close' since it does not complete any @@ -5889,20 +5907,20 @@ *Returns* `TRUE' is returned if all is ok, otherwise `FALSE'. -2.15.0.8 `bfd_create' -..................... +`bfd_create' +............ -*Synopsis* + *Synopsis* bfd *bfd_create (const char *filename, bfd *templ); *Description* Create a new BFD in the manner of `bfd_openw', but without opening a file. The new BFD takes the target from the target used by TEMPLATE. The format is always set to `bfd_object'. -2.15.0.9 `bfd_make_writable' -............................ +`bfd_make_writable' +................... -*Synopsis* + *Synopsis* bfd_boolean bfd_make_writable (bfd *abfd); *Description* Takes a BFD as created by `bfd_create' and converts it into one like as @@ -5913,10 +5931,10 @@ *Returns* `TRUE' is returned if all is ok, otherwise `FALSE'. -2.15.0.10 `bfd_make_readable' -............................. +`bfd_make_readable' +................... -*Synopsis* + *Synopsis* bfd_boolean bfd_make_readable (bfd *abfd); *Description* Takes a BFD as created by `bfd_create' and `bfd_make_writable' and @@ -5927,28 +5945,28 @@ *Returns* `TRUE' is returned if all is ok, otherwise `FALSE'. -2.15.0.11 `bfd_alloc' -..................... +`bfd_alloc' +........... -*Synopsis* + *Synopsis* void *bfd_alloc (bfd *abfd, bfd_size_type wanted); *Description* Allocate a block of WANTED bytes of memory attached to `abfd' and return a pointer to it. -2.15.0.12 `bfd_zalloc' -...................... +`bfd_zalloc' +............ -*Synopsis* + *Synopsis* void *bfd_zalloc (bfd *abfd, bfd_size_type wanted); *Description* Allocate a block of WANTED bytes of zeroed memory attached to `abfd' and return a pointer to it. -2.15.0.13 `bfd_calc_gnu_debuglink_crc32' -........................................ +`bfd_calc_gnu_debuglink_crc32' +.............................. -*Synopsis* + *Synopsis* unsigned long bfd_calc_gnu_debuglink_crc32 (unsigned long crc, const unsigned char *buf, bfd_size_type len); *Description* @@ -5959,29 +5977,29 @@ *Returns* Return the updated CRC32 value. -2.15.0.14 `get_debug_link_info' -............................... +`get_debug_link_info' +..................... -*Synopsis* + *Synopsis* char *get_debug_link_info (bfd *abfd, unsigned long *crc32_out); *Description* fetch the filename and CRC32 value for any separate debuginfo associated with ABFD. Return NULL if no such info found, otherwise return filename and update CRC32_OUT. -2.15.0.15 `separate_debug_file_exists' -...................................... +`separate_debug_file_exists' +............................ -*Synopsis* + *Synopsis* bfd_boolean separate_debug_file_exists (char *name, unsigned long crc32); *Description* Checks to see if NAME is a file and if its contents match CRC32. -2.15.0.16 `find_separate_debug_file' -.................................... +`find_separate_debug_file' +.......................... -*Synopsis* + *Synopsis* char *find_separate_debug_file (bfd *abfd); *Description* Searches ABFD for a reference to separate debugging information, scans @@ -5990,10 +6008,10 @@ information if the file is found and has matching CRC32. Returns NULL if no reference to debugging file exists, or file cannot be found. -2.15.0.17 `bfd_follow_gnu_debuglink' -.................................... +`bfd_follow_gnu_debuglink' +.......................... -*Synopsis* + *Synopsis* char *bfd_follow_gnu_debuglink (bfd *abfd, const char *dir); *Description* Takes a BFD and searches it for a .gnu_debuglink section. If this @@ -6011,10 +6029,10 @@ pointer to a heap-allocated string containing the filename. The caller is responsible for freeing this string. -2.15.0.18 `bfd_create_gnu_debuglink_section' -............................................ +`bfd_create_gnu_debuglink_section' +.................................. -*Synopsis* + *Synopsis* struct bfd_section *bfd_create_gnu_debuglink_section (bfd *abfd, const char *filename); *Description* @@ -6025,10 +6043,10 @@ A pointer to the new section is returned if all is ok. Otherwise `NULL' is returned and bfd_error is set. -2.15.0.19 `bfd_fill_in_gnu_debuglink_section' -............................................. +`bfd_fill_in_gnu_debuglink_section' +................................... -*Synopsis* + *Synopsis* bfd_boolean bfd_fill_in_gnu_debuglink_section (bfd *abfd, struct bfd_section *sect, const char *filename); *Description* @@ -6043,29 +6061,29 @@  File: bfd.info, Node: Internal, Next: File Caching, Prev: Opening and Closing, Up: BFD front end -2.16 Internal functions -======================= +Internal functions +================== -*Description* + *Description* These routines are used within BFD. They are not intended for export, but are documented here for completeness. -2.16.0.1 `bfd_write_bigendian_4byte_int' -........................................ +`bfd_write_bigendian_4byte_int' +............................... -*Synopsis* + *Synopsis* bfd_boolean bfd_write_bigendian_4byte_int (bfd *, unsigned int); *Description* Write a 4 byte integer I to the output BFD ABFD, in big endian order regardless of what else is going on. This is useful in archives. -2.16.0.2 `bfd_put_size' -....................... +`bfd_put_size' +.............. -2.16.0.3 `bfd_get_size' -....................... +`bfd_get_size' +.............. -*Description* + *Description* These macros as used for reading and writing raw data in sections; each access (except for bytes) is vectored through the target format of the BFD and mangled accordingly. The mangling performs any necessary endian @@ -6083,7 +6101,7 @@ `bfd_vma''s. /* Byte swapping macros for user section data. */ - + #define bfd_put_8(abfd, val, ptr) \ ((void) (*((unsigned char *) (ptr)) = (val) & 0xff)) #define bfd_put_signed_8 \ @@ -6092,7 +6110,7 @@ (*(unsigned char *) (ptr) & 0xff) #define bfd_get_signed_8(abfd, ptr) \ (((*(unsigned char *) (ptr) & 0xff) ^ 0x80) - 0x80) - + #define bfd_put_16(abfd, val, ptr) \ BFD_SEND (abfd, bfd_putx16, ((val),(ptr))) #define bfd_put_signed_16 \ @@ -6101,7 +6119,7 @@ BFD_SEND (abfd, bfd_getx16, (ptr)) #define bfd_get_signed_16(abfd, ptr) \ BFD_SEND (abfd, bfd_getx_signed_16, (ptr)) - + #define bfd_put_32(abfd, val, ptr) \ BFD_SEND (abfd, bfd_putx32, ((val),(ptr))) #define bfd_put_signed_32 \ @@ -6110,7 +6128,7 @@ BFD_SEND (abfd, bfd_getx32, (ptr)) #define bfd_get_signed_32(abfd, ptr) \ BFD_SEND (abfd, bfd_getx_signed_32, (ptr)) - + #define bfd_put_64(abfd, val, ptr) \ BFD_SEND (abfd, bfd_putx64, ((val), (ptr))) #define bfd_put_signed_64 \ @@ -6119,14 +6137,14 @@ BFD_SEND (abfd, bfd_getx64, (ptr)) #define bfd_get_signed_64(abfd, ptr) \ BFD_SEND (abfd, bfd_getx_signed_64, (ptr)) - + #define bfd_get(bits, abfd, ptr) \ ((bits) == 8 ? (bfd_vma) bfd_get_8 (abfd, ptr) \ : (bits) == 16 ? bfd_get_16 (abfd, ptr) \ : (bits) == 32 ? bfd_get_32 (abfd, ptr) \ : (bits) == 64 ? bfd_get_64 (abfd, ptr) \ : (abort (), (bfd_vma) - 1)) - + #define bfd_put(bits, abfd, val, ptr) \ ((bits) == 8 ? bfd_put_8 (abfd, val, ptr) \ : (bits) == 16 ? bfd_put_16 (abfd, val, ptr) \ @@ -6134,10 +6152,10 @@ : (bits) == 64 ? bfd_put_64 (abfd, val, ptr) \ : (abort (), (void) 0)) -2.16.0.4 `bfd_h_put_size' -......................... +`bfd_h_put_size' +................ -*Description* + *Description* These macros have the same function as their `bfd_get_x' brethren, except that they are used for removing information for the header records of object files. Believe it or not, some object files keep @@ -6145,7 +6163,7 @@ endian order. /* Byte swapping macros for file header data. */ - + #define bfd_h_put_8(abfd, val, ptr) \ bfd_put_8 (abfd, val, ptr) #define bfd_h_put_signed_8(abfd, val, ptr) \ @@ -6154,7 +6172,7 @@ bfd_get_8 (abfd, ptr) #define bfd_h_get_signed_8(abfd, ptr) \ bfd_get_signed_8 (abfd, ptr) - + #define bfd_h_put_16(abfd, val, ptr) \ BFD_SEND (abfd, bfd_h_putx16, (val, ptr)) #define bfd_h_put_signed_16 \ @@ -6163,7 +6181,7 @@ BFD_SEND (abfd, bfd_h_getx16, (ptr)) #define bfd_h_get_signed_16(abfd, ptr) \ BFD_SEND (abfd, bfd_h_getx_signed_16, (ptr)) - + #define bfd_h_put_32(abfd, val, ptr) \ BFD_SEND (abfd, bfd_h_putx32, (val, ptr)) #define bfd_h_put_signed_32 \ @@ -6172,7 +6190,7 @@ BFD_SEND (abfd, bfd_h_getx32, (ptr)) #define bfd_h_get_signed_32(abfd, ptr) \ BFD_SEND (abfd, bfd_h_getx_signed_32, (ptr)) - + #define bfd_h_put_64(abfd, val, ptr) \ BFD_SEND (abfd, bfd_h_putx64, (val, ptr)) #define bfd_h_put_signed_64 \ @@ -6181,9 +6199,9 @@ BFD_SEND (abfd, bfd_h_getx64, (ptr)) #define bfd_h_get_signed_64(abfd, ptr) \ BFD_SEND (abfd, bfd_h_getx_signed_64, (ptr)) - + /* Aliases for the above, which should eventually go away. */ - + #define H_PUT_64 bfd_h_put_64 #define H_PUT_32 bfd_h_put_32 #define H_PUT_16 bfd_h_put_16 @@ -6201,10 +6219,10 @@ #define H_GET_S16 bfd_h_get_signed_16 #define H_GET_S8 bfd_h_get_signed_8 -2.16.0.5 `bfd_log2' -................... +`bfd_log2' +.......... -*Synopsis* + *Synopsis* unsigned int bfd_log2 (bfd_vma x); *Description* Return the log base 2 of the value supplied, rounded up. E.g., an X of @@ -6213,10 +6231,10 @@  File: bfd.info, Node: File Caching, Next: Linker Functions, Prev: Internal, Up: BFD front end -2.17 File caching -================= +File caching +============ -The file caching mechanism is embedded within BFD and allows the + The file caching mechanism is embedded within BFD and allows the application to open as many BFDs as it wants without regard to the underlying operating system's file descriptor limit (often as low as 20 open files). The module in `cache.c' maintains a least recently used @@ -6225,27 +6243,27 @@ BFD is open. If not, then it chooses a file to close, closes it and opens the one wanted, returning its file handle. -2.17.0.1 `BFD_CACHE_MAX_OPEN macro' -................................... +`BFD_CACHE_MAX_OPEN macro' +.......................... -*Description* + *Description* The maximum number of files which the cache will keep open at one time. #define BFD_CACHE_MAX_OPEN 10 -2.17.0.2 `bfd_last_cache' -......................... +`bfd_last_cache' +................ -*Synopsis* + *Synopsis* extern bfd *bfd_last_cache; *Description* Zero, or a pointer to the topmost BFD on the chain. This is used by the `bfd_cache_lookup' macro in `libbfd.h' to determine when it can avoid a function call. -2.17.0.3 `bfd_cache_lookup' -........................... +`bfd_cache_lookup' +.................. -*Description* + *Description* Check to see if the required BFD is the same as the last one looked up. If so, then it can use the stream in the BFD with impunity, since it can't have changed since the last lookup; otherwise, it has to perform @@ -6255,18 +6273,18 @@ (FILE *) (bfd_last_cache->iostream): \ bfd_cache_lookup_worker (x)) -2.17.0.4 `bfd_cache_init' -......................... +`bfd_cache_init' +................ -*Synopsis* + *Synopsis* bfd_boolean bfd_cache_init (bfd *abfd); *Description* Add a newly opened BFD to the cache. -2.17.0.5 `bfd_cache_close' -.......................... +`bfd_cache_close' +................. -*Synopsis* + *Synopsis* bfd_boolean bfd_cache_close (bfd *abfd); *Description* Remove the BFD ABFD from the cache. If the attached file is open, then @@ -6276,10 +6294,10 @@ `FALSE' is returned if closing the file fails, `TRUE' is returned if all is well. -2.17.0.6 `bfd_cache_close_all' -.............................. +`bfd_cache_close_all' +..................... -*Synopsis* + *Synopsis* bfd_boolean bfd_cache_close_all (void); *Description* Remove all BFDs from the cache. If the attached file is open, then @@ -6289,10 +6307,10 @@ `FALSE' is returned if closing one of the file fails, `TRUE' is returned if all is well. -2.17.0.7 `bfd_open_file' -........................ +`bfd_open_file' +............... -*Synopsis* + *Synopsis* FILE* bfd_open_file (bfd *abfd); *Description* Call the OS to open a file for ABFD. Return the `FILE *' (possibly @@ -6301,10 +6319,10 @@ `NULL', then it won't have been put in the cache, so it won't have to be removed from it. -2.17.0.8 `bfd_cache_lookup_worker' -.................................. +`bfd_cache_lookup_worker' +......................... -*Synopsis* + *Synopsis* FILE *bfd_cache_lookup_worker (bfd *abfd); *Description* Called when the macro `bfd_cache_lookup' fails to find a quick answer. @@ -6316,10 +6334,10 @@  File: bfd.info, Node: Linker Functions, Next: Hash Tables, Prev: File Caching, Up: BFD front end -2.18 Linker Functions -===================== +Linker Functions +================ -The linker uses three special entry points in the BFD target vector. + The linker uses three special entry points in the BFD target vector. It is not necessary to write special routines for these entry points when creating a new BFD back end, since generic versions are provided. However, writing them can speed up linking and make it use @@ -6355,10 +6373,10 @@  File: bfd.info, Node: Creating a Linker Hash Table, Next: Adding Symbols to the Hash Table, Prev: Linker Functions, Up: Linker Functions -2.18.1 Creating a linker hash table ------------------------------------ +Creating a linker hash table +---------------------------- -The linker routines must create a hash table, which must be derived + The linker routines must create a hash table, which must be derived from `struct bfd_link_hash_table' described in `bfdlink.c'. *Note Hash Tables::, for information on how to create a derived hash table. This entry point is called using the target vector of the linker output file. @@ -6388,16 +6406,16 @@  File: bfd.info, Node: Adding Symbols to the Hash Table, Next: Performing the Final Link, Prev: Creating a Linker Hash Table, Up: Linker Functions -2.18.2 Adding symbols to the hash table ---------------------------------------- +Adding symbols to the hash table +-------------------------------- -The linker proper will call the `_bfd_link_add_symbols' entry point for -each object file or archive which is to be linked (typically these are -the files named on the command line, but some may also come from the -linker script). The entry point is responsible for examining the file. -For an object file, BFD must add any relevant symbol information to -the hash table. For an archive, BFD must determine which elements of -the archive should be used and adding them to the link. + The linker proper will call the `_bfd_link_add_symbols' entry point +for each object file or archive which is to be linked (typically these +are the files named on the command line, but some may also come from +the linker script). The entry point is responsible for examining the +file. For an object file, BFD must add any relevant symbol information +to the hash table. For an archive, BFD must determine which elements +of the archive should be used and adding them to the link. The a.out version of this entry point is `NAME(aout,link_add_symbols)'. @@ -6411,18 +6429,18 @@  File: bfd.info, Node: Differing file formats, Next: Adding symbols from an object file, Prev: Adding Symbols to the Hash Table, Up: Adding Symbols to the Hash Table -2.18.2.1 Differing file formats -............................... +Differing file formats +...................... -Normally all the files involved in a link will be of the same format, -but it is also possible to link together different format object files, -and the back end must support that. The `_bfd_link_add_symbols' entry -point is called via the target vector of the file to be added. This -has an important consequence: the function may not assume that the hash -table is the type created by the corresponding -`_bfd_link_hash_table_create' vector. All the `_bfd_link_add_symbols' -function can assume about the hash table is that it is derived from -`struct bfd_link_hash_table'. + Normally all the files involved in a link will be of the same +format, but it is also possible to link together different format +object files, and the back end must support that. The +`_bfd_link_add_symbols' entry point is called via the target vector of +the file to be added. This has an important consequence: the function +may not assume that the hash table is the type created by the +corresponding `_bfd_link_hash_table_create' vector. All the +`_bfd_link_add_symbols' function can assume about the hash table is +that it is derived from `struct bfd_link_hash_table'. Sometimes the `_bfd_link_add_symbols' function must store some information in the hash table entry to be used by the `_bfd_final_link' @@ -6445,12 +6463,12 @@  File: bfd.info, Node: Adding symbols from an object file, Next: Adding symbols from an archive, Prev: Differing file formats, Up: Adding Symbols to the Hash Table -2.18.2.2 Adding symbols from an object file -........................................... +Adding symbols from an object file +.................................. -When the `_bfd_link_add_symbols' routine is passed an object file, it -must add all externally visible symbols in that object file to the hash -table. The actual work of adding the symbol to the hash table is + When the `_bfd_link_add_symbols' routine is passed an object file, +it must add all externally visible symbols in that object file to the +hash table. The actual work of adding the symbol to the hash table is normally handled by the function `_bfd_generic_link_add_one_symbol'. The `_bfd_link_add_symbols' routine is responsible for reading all the symbols from the object file and passing the correct information to @@ -6485,11 +6503,11 @@  File: bfd.info, Node: Adding symbols from an archive, Prev: Adding symbols from an object file, Up: Adding Symbols to the Hash Table -2.18.2.3 Adding symbols from an archive -....................................... +Adding symbols from an archive +.............................. -When the `_bfd_link_add_symbols' routine is passed an archive, it must -look through the symbols defined by the archive and decide which + When the `_bfd_link_add_symbols' routine is passed an archive, it +must look through the symbols defined by the archive and decide which elements of the archive should be included in the link. For each such element it must call the `add_archive_element' linker callback, and it must add the symbols from the object file to the linker hash table. @@ -6529,10 +6547,10 @@  File: bfd.info, Node: Performing the Final Link, Prev: Adding Symbols to the Hash Table, Up: Linker Functions -2.18.3 Performing the final link --------------------------------- +Performing the final link +------------------------- -When all the input files have been processed, the linker calls the + When all the input files have been processed, the linker calls the `_bfd_final_link' entry point of the output BFD. This routine is responsible for producing the final output file, which has several aspects. It must relocate the contents of the input sections and copy @@ -6559,11 +6577,11 @@  File: bfd.info, Node: Information provided by the linker, Next: Relocating the section contents, Prev: Performing the Final Link, Up: Performing the Final Link -2.18.3.1 Information provided by the linker -........................................... +Information provided by the linker +.................................. -Before the linker calls the `_bfd_final_link' entry point, it sets up -some data structures for the function to use. + Before the linker calls the `_bfd_final_link' entry point, it sets +up some data structures for the function to use. The `input_bfds' field of the `bfd_link_info' structure will point to a list of all the input files included in the link. These files are @@ -6582,10 +6600,10 @@  File: bfd.info, Node: Relocating the section contents, Next: Writing the symbol table, Prev: Information provided by the linker, Up: Performing the Final Link -2.18.3.2 Relocating the section contents -........................................ +Relocating the section contents +............................... -The `_bfd_final_link' function should look through the `link_order' + The `_bfd_final_link' function should look through the `link_order' structures attached to each section of the output file. Each `link_order' structure should either be handled specially, or it should be passed to the function `_bfd_default_link_order' which will do the @@ -6616,12 +6634,12 @@  File: bfd.info, Node: Writing the symbol table, Prev: Relocating the section contents, Up: Performing the Final Link -2.18.3.3 Writing the symbol table -................................. +Writing the symbol table +........................ -The `_bfd_final_link' function must gather all the symbols in the input -files and write them out. It must also write out all the symbols in -the global hash table. This must be controlled by the `strip' and + The `_bfd_final_link' function must gather all the symbols in the +input files and write them out. It must also write out all the symbols +in the global hash table. This must be controlled by the `strip' and `discard' fields of the `bfd_link_info' structure. The local symbols of the input files will not have been entered into @@ -6657,10 +6675,10 @@ builds a string table while writing out the symbols, which is written to the output file at the end of `NAME(aout,final_link)'. -2.18.3.4 `bfd_link_split_section' -................................. +`bfd_link_split_section' +........................ -*Synopsis* + *Synopsis* bfd_boolean bfd_link_split_section (bfd *abfd, asection *sec); *Description* Return nonzero if SEC should be split during a reloceatable or final @@ -6668,10 +6686,10 @@ #define bfd_link_split_section(abfd, sec) \ BFD_SEND (abfd, _bfd_link_split_section, (abfd, sec)) -2.18.3.5 `bfd_section_already_linked' -..................................... +`bfd_section_already_linked' +............................ -*Synopsis* + *Synopsis* void bfd_section_already_linked (bfd *abfd, asection *sec); *Description* Check if SEC has been already linked during a reloceatable or final @@ -6682,10 +6700,10 @@  File: bfd.info, Node: Hash Tables, Prev: Linker Functions, Up: BFD front end -2.19 Hash Tables -================ +Hash Tables +=========== -BFD provides a simple set of hash table functions. Routines are + BFD provides a simple set of hash table functions. Routines are provided to initialize a hash table, to free a hash table, to look up a string in a hash table and optionally create an entry for it, and to traverse a hash table. There is currently no routine to delete an @@ -6713,12 +6731,12 @@  File: bfd.info, Node: Creating and Freeing a Hash Table, Next: Looking Up or Entering a String, Prev: Hash Tables, Up: Hash Tables -2.19.1 Creating and freeing a hash table ----------------------------------------- +Creating and freeing a hash table +--------------------------------- -To create a hash table, create an instance of a `struct bfd_hash_table' -(defined in `bfd.h') and call `bfd_hash_table_init' (if you know -approximately how many entries you will need, the function + To create a hash table, create an instance of a `struct +bfd_hash_table' (defined in `bfd.h') and call `bfd_hash_table_init' (if +you know approximately how many entries you will need, the function `bfd_hash_table_init_n', which takes a SIZE argument, may be used). `bfd_hash_table_init' returns `FALSE' if some sort of error occurs. @@ -6741,11 +6759,11 @@  File: bfd.info, Node: Looking Up or Entering a String, Next: Traversing a Hash Table, Prev: Creating and Freeing a Hash Table, Up: Hash Tables -2.19.2 Looking up or entering a string --------------------------------------- +Looking up or entering a string +------------------------------- -The function `bfd_hash_lookup' is used both to look up a string in the -hash table and to create a new entry. + The function `bfd_hash_lookup' is used both to look up a string in +the hash table and to create a new entry. If the CREATE argument is `FALSE', `bfd_hash_lookup' will look up a string. If the string is found, it will returns a pointer to a `struct @@ -6768,12 +6786,12 @@  File: bfd.info, Node: Traversing a Hash Table, Next: Deriving a New Hash Table Type, Prev: Looking Up or Entering a String, Up: Hash Tables -2.19.3 Traversing a hash table ------------------------------- +Traversing a hash table +----------------------- -The function `bfd_hash_traverse' may be used to traverse a hash table, -calling a function on each element. The traversal is done in a random -order. + The function `bfd_hash_traverse' may be used to traverse a hash +table, calling a function on each element. The traversal is done in a +random order. `bfd_hash_traverse' takes as arguments a function and a generic `void *' pointer. The function is called with a hash table entry (a @@ -6786,10 +6804,10 @@  File: bfd.info, Node: Deriving a New Hash Table Type, Prev: Traversing a Hash Table, Up: Hash Tables -2.19.4 Deriving a new hash table type -------------------------------------- +Deriving a new hash table type +------------------------------ -Many uses of hash tables want to store additional information which + Many uses of hash tables want to store additional information which each entry in the hash table. Some also find it convenient to store additional information with the hash table itself. This may be done using a derived hash table. @@ -6815,10 +6833,10 @@  File: bfd.info, Node: Define the Derived Structures, Next: Write the Derived Creation Routine, Prev: Deriving a New Hash Table Type, Up: Deriving a New Hash Table Type -2.19.4.1 Define the derived structures -...................................... +Define the derived structures +............................. -You must define a structure for an entry in the hash table, and a + You must define a structure for an entry in the hash table, and a structure for the hash table itself. The first field in the structure for an entry in the hash table must @@ -6837,11 +6855,11 @@  File: bfd.info, Node: Write the Derived Creation Routine, Next: Write Other Derived Routines, Prev: Define the Derived Structures, Up: Deriving a New Hash Table Type -2.19.4.2 Write the derived creation routine -........................................... +Write the derived creation routine +.................................. -You must write a routine which will create and initialize an entry in -the hash table. This routine is passed as the function argument to + You must write a routine which will create and initialize an entry +in the hash table. This routine is passed as the function argument to `bfd_hash_table_init'. In order to permit other hash tables to be derived from the hash @@ -6872,7 +6890,7 @@ const char *string; { struct ENTRY_TYPE *ret = (ENTRY_TYPE *) entry; - + /* Allocate the structure if it has not already been allocated by a derived class. */ if (ret == (ENTRY_TYPE *) NULL) @@ -6882,13 +6900,13 @@ if (ret == (ENTRY_TYPE *) NULL) return NULL; } - + /* Call the allocation method of the base class. */ ret = ((ENTRY_TYPE *) BASE_NEWFUNC ((struct bfd_hash_entry *) ret, table, string)); - + /* Initialize the local fields here. */ - + return (struct bfd_hash_entry *) ret; } *Description* @@ -6904,10 +6922,11 @@  File: bfd.info, Node: Write Other Derived Routines, Prev: Write the Derived Creation Routine, Up: Deriving a New Hash Table Type -2.19.4.3 Write other derived routines -..................................... +Write other derived routines +............................ -You will want to write other routines for your new hash table, as well. + You will want to write other routines for your new hash table, as +well. You will want an initialization routine which calls the initialization routine of the hash table you are deriving from and @@ -6933,8 +6952,8 @@  File: bfd.info, Node: BFD back ends, Next: GNU Free Documentation License, Prev: BFD front end, Up: Top -3 BFD back ends -*************** +BFD back ends +************* * Menu: @@ -6952,10 +6971,10 @@  File: bfd.info, Node: aout, Next: coff, Prev: What to Put Where, Up: BFD back ends -3.1 a.out backends -================== +a.out backends +============== -*Description* + *Description* BFD supports a number of different flavours of a.out format, though the major differences are only the sizes of the structures on disk, and the shape of the relocation information. @@ -7031,10 +7050,10 @@ `XXX.mt' file (by setting "`bfd_target=XXX'") when your configuration is selected. -3.1.1 Relocations ------------------ +Relocations +----------- -*Description* + *Description* The file `aoutx.h' provides for both the _standard_ and _extended_ forms of a.out relocation records. @@ -7042,18 +7061,18 @@ type field. The extended records (used on 29ks and sparcs) also have a full integer for an addend. -3.1.2 Internal entry points ---------------------------- +Internal entry points +--------------------- -*Description* + *Description* `aoutx.h' exports several routines for accessing the contents of an a.out file, which are gathered and exported in turn by various format specific files (eg sunos.c). -3.1.2.1 `aout_SIZE_swap_exec_header_in' -....................................... +`aout_SIZE_swap_exec_header_in' +............................... -*Synopsis* + *Synopsis* void aout_SIZE_swap_exec_header_in, (bfd *abfd, struct external_exec *raw_bytes, @@ -7062,10 +7081,10 @@ Swap the information in an executable header RAW_BYTES taken from a raw byte stream memory image into the internal exec header structure EXECP. -3.1.2.2 `aout_SIZE_swap_exec_header_out' -........................................ +`aout_SIZE_swap_exec_header_out' +................................ -*Synopsis* + *Synopsis* void aout_SIZE_swap_exec_header_out (bfd *abfd, struct internal_exec *execp, @@ -7074,10 +7093,10 @@ Swap the information in an internal exec header structure EXECP into the buffer RAW_BYTES ready for writing to disk. -3.1.2.3 `aout_SIZE_some_aout_object_p' -...................................... +`aout_SIZE_some_aout_object_p' +.............................. -*Synopsis* + *Synopsis* const bfd_target *aout_SIZE_some_aout_object_p (bfd *abfd, const bfd_target *(*callback_to_real_object_p) ()); @@ -7087,18 +7106,18 @@ is. Call back to the calling environment's "finish up" function just before returning, to handle any last-minute setup. -3.1.2.4 `aout_SIZE_mkobject' -............................ +`aout_SIZE_mkobject' +.................... -*Synopsis* + *Synopsis* bfd_boolean aout_SIZE_mkobject, (bfd *abfd); *Description* Initialize BFD ABFD for use with a.out files. -3.1.2.5 `aout_SIZE_machine_type' -................................ +`aout_SIZE_machine_type' +........................ -*Synopsis* + *Synopsis* enum machine_type aout_SIZE_machine_type (enum bfd_architecture arch, unsigned long machine)); @@ -7111,10 +7130,10 @@ If the architecture is understood, machine type 0 (default) is always understood. -3.1.2.6 `aout_SIZE_set_arch_mach' -................................. +`aout_SIZE_set_arch_mach' +......................... -*Synopsis* + *Synopsis* bfd_boolean aout_SIZE_set_arch_mach, (bfd *, enum bfd_architecture arch, @@ -7124,10 +7143,10 @@ and MACHINE. Verify that ABFD's format can support the architecture required. -3.1.2.7 `aout_SIZE_new_section_hook' -.................................... +`aout_SIZE_new_section_hook' +............................ -*Synopsis* + *Synopsis* bfd_boolean aout_SIZE_new_section_hook, (bfd *abfd, asection *newsect)); @@ -7137,12 +7156,12 @@  File: bfd.info, Node: coff, Next: elf, Prev: aout, Up: BFD back ends -3.2 coff backends -================= +coff backends +============= -BFD supports a number of different flavours of coff format. The major -differences between formats are the sizes and alignments of fields in -structures on disk, and the occasional extra field. + BFD supports a number of different flavours of coff format. The +major differences between formats are the sizes and alignments of +fields in structures on disk, and the occasional extra field. Coff in all its varieties is implemented with a few common files and a number of implementation specific files. For example, The 88k bcs @@ -7156,19 +7175,19 @@ `coff-i960.c'. This file has the same structure as `coff-m88k.c', except that it includes `coff/i960.h' rather than `coff-m88k.h'. -3.2.1 Porting to a new version of coff --------------------------------------- +Porting to a new version of coff +-------------------------------- -The recommended method is to select from the existing implementations -the version of coff which is most like the one you want to use. For -example, we'll say that i386 coff is the one you select, and that your -coff flavour is called foo. Copy `i386coff.c' to `foocoff.c', copy -`../include/coff/i386.h' to `../include/coff/foo.h', and add the lines -to `targets.c' and `Makefile.in' so that your new back end is used. -Alter the shapes of the structures in `../include/coff/foo.h' so that -they match what you need. You will probably also have to add `#ifdef's -to the code in `coff/internal.h' and `coffcode.h' if your version of -coff is too wild. + The recommended method is to select from the existing +implementations the version of coff which is most like the one you want +to use. For example, we'll say that i386 coff is the one you select, +and that your coff flavour is called foo. Copy `i386coff.c' to +`foocoff.c', copy `../include/coff/i386.h' to `../include/coff/foo.h', +and add the lines to `targets.c' and `Makefile.in' so that your new +back end is used. Alter the shapes of the structures in +`../include/coff/foo.h' so that they match what you need. You will +probably also have to add `#ifdef's to the code in `coff/internal.h' and +`coffcode.h' if your version of coff is too wild. You can verify that your new BFD backend works quite simply by building `objdump' from the `binutils' directory, and making sure that @@ -7178,16 +7197,16 @@ you've done to Cygnus. Then your stuff will be in the next release, and you won't have to keep integrating it. -3.2.2 How the coff backend works --------------------------------- +How the coff backend works +-------------------------- -3.2.2.1 File layout -................... +File layout +........... -The Coff backend is split into generic routines that are applicable to -any Coff target and routines that are specific to a particular target. -The target-specific routines are further split into ones which are -basically the same for all Coff targets except that they use the + The Coff backend is split into generic routines that are applicable +to any Coff target and routines that are specific to a particular +target. The target-specific routines are further split into ones which +are basically the same for all Coff targets except that they use the external symbol format or use different values for certain constants. The generic routines are in `coffgen.c'. These routines work for @@ -7210,10 +7229,10 @@ This code is not in `coffcode.h' because it would not be used by any other target. -3.2.2.2 Bit twiddling -..................... +Bit twiddling +............. -Each flavour of coff supported in BFD has its own header file + Each flavour of coff supported in BFD has its own header file describing the external layout of the structures. There is also an internal description of the coff layout, in `coff/internal.h'. A major function of the coff backend is swapping the bytes and twiddling the @@ -7240,13 +7259,13 @@ use the same header files as `gas', which makes one avenue to disaster disappear. -3.2.2.3 Symbol reading -...................... +Symbol reading +.............. -The simple canonical form for symbols used by BFD is not rich enough to -keep all the information available in a coff symbol table. The back end -gets around this problem by keeping the original symbol table around, -"behind the scenes". + The simple canonical form for symbols used by BFD is not rich enough +to keep all the information available in a coff symbol table. The back +end gets around this problem by keeping the original symbol table +around, "behind the scenes". When a symbol table is requested (through a call to `bfd_canonicalize_symtab'), a request gets through to @@ -7278,13 +7297,13 @@ Any linenumbers are read from the coff file too, and attached to the symbols which own the functions the linenumbers belong to. -3.2.2.4 Symbol writing -...................... +Symbol writing +.............. -Writing a symbol to a coff file which didn't come from a coff file will -lose any debugging information. The `asymbol' structure remembers the -BFD from which the symbol was taken, and on output the back end makes -sure that the same destination target as source target is present. + Writing a symbol to a coff file which didn't come from a coff file +will lose any debugging information. The `asymbol' structure remembers +the BFD from which the symbol was taken, and on output the back end +makes sure that the same destination target as source target is present. When the symbols have come from a coff file then all the debugging information is preserved. @@ -7320,10 +7339,10 @@ symbols from their internal form into the coff way, calls the bit twiddlers, and writes out the table to the file. -3.2.2.5 `coff_symbol_type' -.......................... +`coff_symbol_type' +.................. -*Description* + *Description* The hidden information for an `asymbol' is described in a `combined_entry_type': @@ -7333,27 +7352,27 @@ /* Remembers the offset from the first symbol in the file for this symbol. Generated by coff_renumber_symbols. */ unsigned int offset; - + /* Should the value of this symbol be renumbered. Used for XCOFF C_BSTAT symbols. Set by coff_slurp_symbol_table. */ unsigned int fix_value : 1; - + /* Should the tag field of this symbol be renumbered. Created by coff_pointerize_aux. */ unsigned int fix_tag : 1; - + /* Should the endidx field of this symbol be renumbered. Created by coff_pointerize_aux. */ unsigned int fix_end : 1; - + /* Should the x_csect.x_scnlen field be renumbered. Created by coff_pointerize_aux. */ unsigned int fix_scnlen : 1; - + /* Fix up an XCOFF C_BINCL/C_EINCL symbol. The value is the index into the line number entries. Set by coff_slurp_symbol_table. */ unsigned int fix_line : 1; - + /* The container for the symbol structure as read and translated from the file. */ union @@ -7362,30 +7381,30 @@ struct internal_syment syment; } u; } combined_entry_type; - - + + /* Each canonical asymbol really looks like this: */ - + typedef struct coff_symbol_struct { /* The actual symbol which the rest of BFD works with */ asymbol symbol; - + /* A pointer to the hidden information for this symbol */ combined_entry_type *native; - + /* A pointer to the linenumber information for this symbol */ struct lineno_cache_entry *lineno; - + /* Have the line numbers been relocated yet ? */ bfd_boolean done_lineno; } coff_symbol_type; - -3.2.2.6 `bfd_coff_backend_data' -............................... - /* COFF symbol classifications. */ +`bfd_coff_backend_data' +....................... + /* COFF symbol classifications. */ + enum coff_symbol_classification { /* Global symbol. */ @@ -7399,39 +7418,39 @@ /* PE section symbol. */ COFF_SYMBOL_PE_SECTION }; -Special entry points for gdb to swap in coff symbol table parts: + Special entry points for gdb to swap in coff symbol table parts: typedef struct { void (*_bfd_coff_swap_aux_in) PARAMS ((bfd *, PTR, int, int, int, int, PTR)); - + void (*_bfd_coff_swap_sym_in) PARAMS ((bfd *, PTR, PTR)); - + void (*_bfd_coff_swap_lineno_in) PARAMS ((bfd *, PTR, PTR)); - + unsigned int (*_bfd_coff_swap_aux_out) PARAMS ((bfd *, PTR, int, int, int, int, PTR)); - + unsigned int (*_bfd_coff_swap_sym_out) PARAMS ((bfd *, PTR, PTR)); - + unsigned int (*_bfd_coff_swap_lineno_out) PARAMS ((bfd *, PTR, PTR)); - + unsigned int (*_bfd_coff_swap_reloc_out) PARAMS ((bfd *, PTR, PTR)); - + unsigned int (*_bfd_coff_swap_filehdr_out) PARAMS ((bfd *, PTR, PTR)); - + unsigned int (*_bfd_coff_swap_aouthdr_out) PARAMS ((bfd *, PTR, PTR)); - + unsigned int (*_bfd_coff_swap_scnhdr_out) PARAMS ((bfd *, PTR, PTR)); - + unsigned int _bfd_filhsz; unsigned int _bfd_aoutsz; unsigned int _bfd_scnhsz; @@ -7445,124 +7464,124 @@ unsigned int _bfd_coff_default_section_alignment_power; bfd_boolean _bfd_coff_force_symnames_in_strings; unsigned int _bfd_coff_debug_string_prefix_length; - + void (*_bfd_coff_swap_filehdr_in) PARAMS ((bfd *, PTR, PTR)); - + void (*_bfd_coff_swap_aouthdr_in) PARAMS ((bfd *, PTR, PTR)); - + void (*_bfd_coff_swap_scnhdr_in) PARAMS ((bfd *, PTR, PTR)); - + void (*_bfd_coff_swap_reloc_in) PARAMS ((bfd *abfd, PTR, PTR)); - + bfd_boolean (*_bfd_coff_bad_format_hook) PARAMS ((bfd *, PTR)); - + bfd_boolean (*_bfd_coff_set_arch_mach_hook) PARAMS ((bfd *, PTR)); - + PTR (*_bfd_coff_mkobject_hook) PARAMS ((bfd *, PTR, PTR)); - + bfd_boolean (*_bfd_styp_to_sec_flags_hook) PARAMS ((bfd *, PTR, const char *, asection *, flagword *)); - + void (*_bfd_set_alignment_hook) PARAMS ((bfd *, asection *, PTR)); - + bfd_boolean (*_bfd_coff_slurp_symbol_table) PARAMS ((bfd *)); - + bfd_boolean (*_bfd_coff_symname_in_debug) PARAMS ((bfd *, struct internal_syment *)); - + bfd_boolean (*_bfd_coff_pointerize_aux_hook) PARAMS ((bfd *, combined_entry_type *, combined_entry_type *, unsigned int, combined_entry_type *)); - + bfd_boolean (*_bfd_coff_print_aux) PARAMS ((bfd *, FILE *, combined_entry_type *, combined_entry_type *, combined_entry_type *, unsigned int)); - + void (*_bfd_coff_reloc16_extra_cases) PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *, arelent *, bfd_byte *, unsigned int *, unsigned int *)); - + int (*_bfd_coff_reloc16_estimate) PARAMS ((bfd *, asection *, arelent *, unsigned int, struct bfd_link_info *)); - + enum coff_symbol_classification (*_bfd_coff_classify_symbol) PARAMS ((bfd *, struct internal_syment *)); - + bfd_boolean (*_bfd_coff_compute_section_file_positions) PARAMS ((bfd *)); - + bfd_boolean (*_bfd_coff_start_final_link) PARAMS ((bfd *, struct bfd_link_info *)); - + bfd_boolean (*_bfd_coff_relocate_section) PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, struct internal_reloc *, struct internal_syment *, asection **)); - + reloc_howto_type *(*_bfd_coff_rtype_to_howto) PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *)); - + bfd_boolean (*_bfd_coff_adjust_symndx) PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, struct internal_reloc *, bfd_boolean *)); - + bfd_boolean (*_bfd_coff_link_add_one_symbol) PARAMS ((struct bfd_link_info *, bfd *, const char *, flagword, asection *, bfd_vma, const char *, bfd_boolean, bfd_boolean, struct bfd_link_hash_entry **)); - + bfd_boolean (*_bfd_coff_link_output_has_begun) PARAMS ((bfd *, struct coff_final_link_info *)); - + bfd_boolean (*_bfd_coff_final_link_postscript) PARAMS ((bfd *, struct coff_final_link_info *)); - + } bfd_coff_backend_data; - + #define coff_backend_info(abfd) \ ((bfd_coff_backend_data *) (abfd)->xvec->backend_data) - + #define bfd_coff_swap_aux_in(a,e,t,c,ind,num,i) \ ((coff_backend_info (a)->_bfd_coff_swap_aux_in) (a,e,t,c,ind,num,i)) - + #define bfd_coff_swap_sym_in(a,e,i) \ ((coff_backend_info (a)->_bfd_coff_swap_sym_in) (a,e,i)) - + #define bfd_coff_swap_lineno_in(a,e,i) \ ((coff_backend_info ( a)->_bfd_coff_swap_lineno_in) (a,e,i)) - + #define bfd_coff_swap_reloc_out(abfd, i, o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_reloc_out) (abfd, i, o)) - + #define bfd_coff_swap_lineno_out(abfd, i, o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_lineno_out) (abfd, i, o)) - + #define bfd_coff_swap_aux_out(a,i,t,c,ind,num,o) \ ((coff_backend_info (a)->_bfd_coff_swap_aux_out) (a,i,t,c,ind,num,o)) - + #define bfd_coff_swap_sym_out(abfd, i,o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_sym_out) (abfd, i, o)) - + #define bfd_coff_swap_scnhdr_out(abfd, i,o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_scnhdr_out) (abfd, i, o)) - + #define bfd_coff_swap_filehdr_out(abfd, i,o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_filehdr_out) (abfd, i, o)) - + #define bfd_coff_swap_aouthdr_out(abfd, i,o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_aouthdr_out) (abfd, i, o)) - + #define bfd_coff_filhsz(abfd) (coff_backend_info (abfd)->_bfd_filhsz) #define bfd_coff_aoutsz(abfd) (coff_backend_info (abfd)->_bfd_aoutsz) #define bfd_coff_scnhsz(abfd) (coff_backend_info (abfd)->_bfd_scnhsz) @@ -7579,65 +7598,65 @@ (coff_backend_info (abfd)->_bfd_coff_default_section_alignment_power) #define bfd_coff_swap_filehdr_in(abfd, i,o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_filehdr_in) (abfd, i, o)) - + #define bfd_coff_swap_aouthdr_in(abfd, i,o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_aouthdr_in) (abfd, i, o)) - + #define bfd_coff_swap_scnhdr_in(abfd, i,o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_scnhdr_in) (abfd, i, o)) - + #define bfd_coff_swap_reloc_in(abfd, i, o) \ ((coff_backend_info (abfd)->_bfd_coff_swap_reloc_in) (abfd, i, o)) - + #define bfd_coff_bad_format_hook(abfd, filehdr) \ ((coff_backend_info (abfd)->_bfd_coff_bad_format_hook) (abfd, filehdr)) - + #define bfd_coff_set_arch_mach_hook(abfd, filehdr)\ ((coff_backend_info (abfd)->_bfd_coff_set_arch_mach_hook) (abfd, filehdr)) #define bfd_coff_mkobject_hook(abfd, filehdr, aouthdr)\ ((coff_backend_info (abfd)->_bfd_coff_mkobject_hook)\ (abfd, filehdr, aouthdr)) - + #define bfd_coff_styp_to_sec_flags_hook(abfd, scnhdr, name, section, flags_ptr)\ ((coff_backend_info (abfd)->_bfd_styp_to_sec_flags_hook)\ (abfd, scnhdr, name, section, flags_ptr)) - + #define bfd_coff_set_alignment_hook(abfd, sec, scnhdr)\ ((coff_backend_info (abfd)->_bfd_set_alignment_hook) (abfd, sec, scnhdr)) - + #define bfd_coff_slurp_symbol_table(abfd)\ ((coff_backend_info (abfd)->_bfd_coff_slurp_symbol_table) (abfd)) - + #define bfd_coff_symname_in_debug(abfd, sym)\ ((coff_backend_info (abfd)->_bfd_coff_symname_in_debug) (abfd, sym)) - + #define bfd_coff_force_symnames_in_strings(abfd)\ (coff_backend_info (abfd)->_bfd_coff_force_symnames_in_strings) - + #define bfd_coff_debug_string_prefix_length(abfd)\ (coff_backend_info (abfd)->_bfd_coff_debug_string_prefix_length) - + #define bfd_coff_print_aux(abfd, file, base, symbol, aux, indaux)\ ((coff_backend_info (abfd)->_bfd_coff_print_aux)\ (abfd, file, base, symbol, aux, indaux)) - + #define bfd_coff_reloc16_extra_cases(abfd, link_info, link_order,\ reloc, data, src_ptr, dst_ptr)\ ((coff_backend_info (abfd)->_bfd_coff_reloc16_extra_cases)\ (abfd, link_info, link_order, reloc, data, src_ptr, dst_ptr)) - + #define bfd_coff_reloc16_estimate(abfd, section, reloc, shrink, link_info)\ ((coff_backend_info (abfd)->_bfd_coff_reloc16_estimate)\ (abfd, section, reloc, shrink, link_info)) - + #define bfd_coff_classify_symbol(abfd, sym)\ ((coff_backend_info (abfd)->_bfd_coff_classify_symbol)\ (abfd, sym)) - + #define bfd_coff_compute_section_file_positions(abfd)\ ((coff_backend_info (abfd)->_bfd_coff_compute_section_file_positions)\ (abfd)) - + #define bfd_coff_start_final_link(obfd, info)\ ((coff_backend_info (obfd)->_bfd_coff_start_final_link)\ (obfd, info)) @@ -7654,16 +7673,16 @@ value, string, cp, coll, hashp)\ ((coff_backend_info (abfd)->_bfd_coff_link_add_one_symbol)\ (info, abfd, name, flags, section, value, string, cp, coll, hashp)) - + #define bfd_coff_link_output_has_begun(a,p) \ ((coff_backend_info (a)->_bfd_coff_link_output_has_begun) (a,p)) #define bfd_coff_final_link_postscript(a,p) \ ((coff_backend_info (a)->_bfd_coff_final_link_postscript) (a,p)) -3.2.2.7 Writing relocations -........................... +Writing relocations +................... -To write relocations, the back end steps though the canonical + To write relocations, the back end steps though the canonical relocation table and create an `internal_reloc'. The symbol index to use is removed from the `offset' field in the symbol table supplied. The address comes directly from the sum of the section base address and @@ -7671,10 +7690,10 @@ Then the `internal_reloc' is swapped into the shape of an `external_reloc' and written out to disk. -3.2.2.8 Reading linenumbers -........................... +Reading linenumbers +................... -Creating the linenumber table is done by reading in the entire coff + Creating the linenumber table is done by reading in the entire coff linenumber table, and creating another table for internal use. A coff linenumber table is structured so that each function is @@ -7691,10 +7710,10 @@ How does this work ? -3.2.2.9 Reading relocations -........................... +Reading relocations +................... -Coff relocations are easily transformed into the internal BFD form + Coff relocations are easily transformed into the internal BFD form (`arelent'). Reading a coff relocation table is done in the following stages: @@ -7719,10 +7738,9 @@  File: bfd.info, Node: elf, Next: mmo, Prev: coff, Up: BFD back ends -3.3 -=== -ELF backends + + ELF backends BFD support for ELF formats is being worked on. Currently, the best supported back ends are for sparc and i386 (running svr4 or Solaris 2). @@ -7731,10 +7749,10 @@ written. The code is changing quickly enough that we haven't bothered yet. -3.3.0.1 `bfd_elf_find_section' -.............................. +`bfd_elf_find_section' +...................... -*Synopsis* + *Synopsis* struct elf_internal_shdr *bfd_elf_find_section (bfd *abfd, char *name); *Description* Helper functions for GDB to locate the string tables. Since BFD hides @@ -7746,20 +7764,20 @@  File: bfd.info, Node: mmo, Prev: elf, Up: BFD back ends -3.4 mmo backend -=============== +mmo backend +=========== -The mmo object format is used exclusively together with Professor + The mmo object format is used exclusively together with Professor Donald E. Knuth's educational 64-bit processor MMIX. The simulator `mmix' which is available at -`http://www-cs-faculty.stanford.edu/~knuth/programs/mmix.tar.gz' + understands this format. That package also includes a combined assembler and linker called `mmixal'. The mmo format has no advantages feature-wise compared to e.g. ELF. It is a simple non-relocatable object format with no support for archives or debugging information, except for symbol value information and line numbers (which is not yet implemented in BFD). See -`http://www-cs-faculty.stanford.edu/~knuth/mmix.html' for more + for more information about MMIX. The ELF format is used for intermediate object files in the BFD implementation. @@ -7772,10 +7790,10 @@  File: bfd.info, Node: File layout, Next: Symbol-table, Prev: mmo, Up: mmo -3.4.1 File layout ------------------ +File layout +----------- -The mmo file contents is not partitioned into named sections as with + The mmo file contents is not partitioned into named sections as with e.g. ELF. Memory areas is formed by specifying the location of the data that follows. Only the memory area `0x0000...00' to `0x01ff...ff' is executable, so it is used for code (and constants) and the area @@ -7793,7 +7811,7 @@ the thirteen lopcodes. The two remaining bytes, called the `Y' and `Z' fields, or the `YZ' field (a 16-bit big-endian number), are used for various purposes different for each lopcode. As documented in -`http://www-cs-faculty.stanford.edu/~knuth/mmixal-intro.ps.gz', the +, the lopcodes are: `lop_quote' @@ -7910,11 +7928,11 @@  File: bfd.info, Node: Symbol-table, Next: mmo section mapping, Prev: File layout, Up: mmo -3.4.2 Symbol table format -------------------------- +Symbol table format +------------------- -From mmixal.w (or really, the generated mmixal.tex) in -`http://www-cs-faculty.stanford.edu/~knuth/programs/mmix.tar.gz'): + From mmixal.w (or really, the generated mmixal.tex) in +): "Symbols are stored and retrieved by means of a `ternary search trie', following ideas of Bentley and Sedgewick. (See ACM-SIAM Symp. on Discrete Algorithms `8' (1997), 360-369; R.Sedgewick, `Algorithms in C' @@ -7935,22 +7953,22 @@ (MMO3_LEFT) 0x40 - Traverse left trie. (Read a new command byte and recurse.) - + (MMO3_SYMBITS) 0x2f - Read the next byte as a character and store it in the current character position; increment character position. Test the bits of `m': - + (MMO3_WCHAR) 0x80 - The character is 16-bit (so read another byte, merge into current character. - + (MMO3_TYPEBITS) 0xf - We have a complete symbol; parse the type, value and serial number and do what should be done with a symbol. The type and length information is in j = (m & 0xf). - + (MMO3_REGQUAL_BITS) j == 0xf: A register variable. The following byte tells which register. @@ -7961,18 +7979,18 @@ j > 8: As with j <= 8, but add (0x20 << 56) to the value in the following j - 8 bytes. - + Then comes the serial number, as a variant of uleb128, but better named ubeb128: Read bytes and shift the previous value left 7 (multiply by 128). Add in the new byte, repeat until a byte has bit 7 set. The serial number is the computed value minus 128. - + (MMO3_MIDDLE) 0x20 - Traverse middle trie. (Read a new command byte and recurse.) Decrement character position. - + (MMO3_RIGHT) 0x10 - Traverse right trie. (Read a new command byte and recurse.) @@ -8004,3 +8022,1644 @@ 00 The value is 0. 81 The serial number is 1. + +File: bfd.info, Node: mmo section mapping, Prev: Symbol-table, Up: mmo + +mmo section mapping +------------------- + + The implementation in BFD uses special data type 80 (decimal) to +encapsulate and describe named sections, containing e.g. debug +information. If needed, any datum in the encapsulation will be quoted +using lop_quote. First comes a 32-bit word holding the number of +32-bit words containing the zero-terminated zero-padded segment name. +After the name there's a 32-bit word holding flags describing the +section type. Then comes a 64-bit big-endian word with the section +length (in bytes), then another with the section start address. +Depending on the type of section, the contents might follow, +zero-padded to 32-bit boundary. For a loadable section (such as data +or code), the contents might follow at some later point, not +necessarily immediately, as a lop_loc with the same start address as in +the section description, followed by the contents. This in effect +forms a descriptor that must be emitted before the actual contents. +Sections described this way must not overlap. + + For areas that don't have such descriptors, synthetic sections are +formed by BFD. Consecutive contents in the two memory areas +`0x0000...00' to `0x01ff...ff' and `0x2000...00' to `0x20ff...ff' are +entered in sections named `.text' and `.data' respectively. If an area +is not otherwise described, but would together with a neighboring lower +area be less than `0x40000000' bytes long, it is joined with the lower +area and the gap is zero-filled. For other cases, a new section is +formed, named `.MMIX.sec.N'. Here, N is a number, a running count +through the mmo file, starting at 0. + + A loadable section specified as: + + .section secname,"ax" + TETRA 1,2,3,4,-1,-2009 + BYTE 80 + + and linked to address `0x4', is represented by the sequence: + + 0x98080050 - lop_spec 80 + 0x00000002 - two 32-bit words for the section name + 0x7365636e - "secn" + 0x616d6500 - "ame\0" + 0x00000033 - flags CODE, READONLY, LOAD, ALLOC + 0x00000000 - high 32 bits of section length + 0x0000001c - section length is 28 bytes; 6 * 4 + 1 + alignment to 32 bits + 0x00000000 - high 32 bits of section address + 0x00000004 - section address is 4 + 0x98010002 - 64 bits with address of following data + 0x00000000 - high 32 bits of address + 0x00000004 - low 32 bits: data starts at address 4 + 0x00000001 - 1 + 0x00000002 - 2 + 0x00000003 - 3 + 0x00000004 - 4 + 0xffffffff - -1 + 0xfffff827 - -2009 + 0x50000000 - 80 as a byte, padded with zeros. + + Note that the lop_spec wrapping does not include the section +contents. Compare this to a non-loaded section specified as: + + .section thirdsec + TETRA 200001,100002 + BYTE 38,40 + + This, when linked to address `0x200000000000001c', is represented by: + + 0x98080050 - lop_spec 80 + 0x00000002 - two 32-bit words for the section name + 0x7365636e - "thir" + 0x616d6500 - "dsec" + 0x00000010 - flag READONLY + 0x00000000 - high 32 bits of section length + 0x0000000c - section length is 12 bytes; 2 * 4 + 2 + alignment to 32 bits + 0x20000000 - high 32 bits of address + 0x0000001c - low 32 bits of address 0x200000000000001c + 0x00030d41 - 200001 + 0x000186a2 - 100002 + 0x26280000 - 38, 40 as bytes, padded with zeros + + For the latter example, the section contents must not be loaded in +memory, and is therefore specified as part of the special data. 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If you have no Front-Cover +Texts, write "no Front-Cover Texts" instead of "Front-Cover Texts being +LIST"; likewise for Back-Cover Texts. + + If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the GNU General Public License, to +permit their use in free software. + + +File: bfd.info, Node: Index, Prev: GNU Free Documentation License, Up: Top + +Index +***** + +* Menu: + +* _bfd_final_link_relocate: Relocating the section contents. +* _bfd_generic_link_add_archive_symbols: Adding symbols from an archive. +* _bfd_generic_link_add_one_symbol: Adding symbols from an object file. +* _bfd_generic_make_empty_symbol: symbol handling functions. +* _bfd_link_add_symbols in target vector: Adding Symbols to the Hash Table. +* _bfd_link_final_link in target vector: Performing the Final Link. +* _bfd_link_hash_table_create in target vector: Creating a Linker Hash Table. +* _bfd_relocate_contents: Relocating the section contents. +* _bfd_strip_section_from_output: section prototypes. +* aout_SIZE_machine_type: aout. +* aout_SIZE_mkobject: aout. +* aout_SIZE_new_section_hook: aout. +* aout_SIZE_set_arch_mach: aout. +* aout_SIZE_some_aout_object_p: aout. +* aout_SIZE_swap_exec_header_in: aout. +* aout_SIZE_swap_exec_header_out: aout. +* arelent_chain: typedef arelent. +* BFD: Overview. +* BFD canonical format: Canonical format. +* bfd_alloc: Opening and Closing. +* bfd_alt_mach_code: BFD front end. +* bfd_arch_bits_per_address: Architectures. +* bfd_arch_bits_per_byte: Architectures. +* bfd_arch_get_compatible: Architectures. +* bfd_arch_list: Architectures. +* bfd_arch_mach_octets_per_byte: Architectures. +* bfd_cache_close: File Caching. +* bfd_cache_close_all: File Caching. +* bfd_cache_init: File Caching. +* bfd_cache_lookup: File Caching. +* bfd_cache_lookup_worker: File Caching. +* BFD_CACHE_MAX_OPEN macro: File Caching. +* bfd_calc_gnu_debuglink_crc32: Opening and Closing. +* bfd_canonicalize_reloc: BFD front end. +* bfd_canonicalize_symtab: symbol handling functions. +* bfd_check_format: Formats. +* bfd_check_format_matches: Formats. +* bfd_check_overflow: typedef arelent. +* bfd_close: Opening and Closing. +* bfd_close_all_done: Opening and Closing. +* bfd_coff_backend_data: coff. +* bfd_copy_private_bfd_data: BFD front end. +* bfd_copy_private_header_data: BFD front end. +* bfd_copy_private_section_data: section prototypes. +* bfd_copy_private_symbol_data: symbol handling functions. +* bfd_core_file_failing_command: Core Files. +* bfd_core_file_failing_signal: Core Files. +* bfd_create: Opening and Closing. +* bfd_create_gnu_debuglink_section: Opening and Closing. +* bfd_decode_symclass: symbol handling functions. +* bfd_default_arch_struct: Architectures. +* bfd_default_compatible: Architectures. +* bfd_default_reloc_type_lookup: howto manager. +* bfd_default_scan: Architectures. +* bfd_default_set_arch_mach: Architectures. +* bfd_elf_find_section: elf. +* bfd_errmsg: BFD front end. +* bfd_fdopenr: Opening and Closing. +* bfd_fill_in_gnu_debuglink_section: Opening and Closing. +* bfd_find_target: bfd_target. +* bfd_follow_gnu_debuglink: Opening and Closing. +* bfd_format_string: Formats. +* bfd_generic_discard_group: section prototypes. +* bfd_generic_gc_sections: howto manager. +* bfd_generic_get_relocated_section_contents: howto manager. +* bfd_generic_is_group_section: section prototypes. +* bfd_generic_merge_sections: howto manager. +* bfd_generic_relax_section: howto manager. +* bfd_get_arch: Architectures. +* bfd_get_arch_info: Architectures. +* bfd_get_arch_size: BFD front end. +* bfd_get_error: BFD front end. +* bfd_get_error_handler: BFD front end. +* bfd_get_gp_size: BFD front end. +* bfd_get_mach: Architectures. +* bfd_get_mtime: BFD front end. +* bfd_get_next_mapent: Archives. +* bfd_get_reloc_code_name: howto manager. +* bfd_get_reloc_size: typedef arelent. +* bfd_get_reloc_upper_bound: BFD front end. +* bfd_get_section_by_name: section prototypes. +* bfd_get_section_by_name_if: section prototypes. +* bfd_get_section_contents: section prototypes. +* bfd_get_sign_extend_vma: BFD front end. +* bfd_get_size <1>: Internal. +* bfd_get_size: BFD front end. +* bfd_get_symtab_upper_bound: symbol handling functions. +* bfd_get_unique_section_name: section prototypes. +* bfd_h_put_size: Internal. +* bfd_hash_allocate: Creating and Freeing a Hash Table. +* bfd_hash_lookup: Looking Up or Entering a String. +* bfd_hash_newfunc: Creating and Freeing a Hash Table. +* bfd_hash_set_default_size: Creating and Freeing a Hash Table. +* bfd_hash_table_free: Creating and Freeing a Hash Table. +* bfd_hash_table_init: Creating and Freeing a Hash Table. +* bfd_hash_table_init_n: Creating and Freeing a Hash Table. +* bfd_hash_traverse: Traversing a Hash Table. +* bfd_init: Initialization. +* bfd_install_relocation: typedef arelent. +* bfd_is_local_label: symbol handling functions. +* bfd_is_local_label_name: symbol handling functions. +* bfd_is_target_special_symbol: symbol handling functions. +* bfd_is_undefined_symclass: symbol handling functions. +* bfd_last_cache: File Caching. +* bfd_link_split_section: Writing the symbol table. +* bfd_log2: Internal. +* bfd_lookup_arch: Architectures. +* bfd_make_debug_symbol: symbol handling functions. +* bfd_make_empty_symbol: symbol handling functions. +* bfd_make_readable: Opening and Closing. +* bfd_make_section: section prototypes. +* bfd_make_section_anyway: section prototypes. +* bfd_make_section_old_way: section prototypes. +* bfd_make_writable: Opening and Closing. +* bfd_malloc_and_get_section: section prototypes. +* bfd_map_over_sections: section prototypes. +* bfd_merge_private_bfd_data: BFD front end. +* bfd_octets_per_byte: Architectures. +* bfd_open_file: File Caching. +* bfd_openr: Opening and Closing. +* bfd_openr_iovec: Opening and Closing. +* bfd_openr_next_archived_file: Archives. +* bfd_openstreamr: Opening and Closing. +* bfd_openw: Opening and Closing. +* bfd_perform_relocation: typedef arelent. +* bfd_perror: BFD front end. +* bfd_preserve_finish: BFD front end. +* bfd_preserve_restore: BFD front end. +* bfd_preserve_save: BFD front end. +* bfd_print_symbol_vandf: symbol handling functions. +* bfd_printable_arch_mach: Architectures. +* bfd_printable_name: Architectures. +* bfd_put_size: Internal. +* BFD_RELOC_12_PCREL: howto manager. +* BFD_RELOC_14: howto manager. +* BFD_RELOC_16: howto manager. +* BFD_RELOC_16_BASEREL: howto manager. +* BFD_RELOC_16_GOT_PCREL: howto manager. +* BFD_RELOC_16_GOTOFF: howto manager. +* BFD_RELOC_16_PCREL: howto manager. +* BFD_RELOC_16_PCREL_S2: howto manager. +* BFD_RELOC_16_PLT_PCREL: howto manager. +* BFD_RELOC_16_PLTOFF: howto manager. +* BFD_RELOC_16C_ABS20: howto manager. +* BFD_RELOC_16C_ABS20_C: howto manager. +* BFD_RELOC_16C_ABS24: howto manager. +* BFD_RELOC_16C_ABS24_C: howto manager. +* BFD_RELOC_16C_DISP04: howto manager. +* BFD_RELOC_16C_DISP04_C: howto manager. +* BFD_RELOC_16C_DISP08: howto manager. +* BFD_RELOC_16C_DISP08_C: howto manager. +* BFD_RELOC_16C_DISP16: howto manager. +* BFD_RELOC_16C_DISP16_C: howto manager. +* BFD_RELOC_16C_DISP24: howto manager. +* BFD_RELOC_16C_DISP24_C: howto manager. +* BFD_RELOC_16C_DISP24a: howto manager. +* BFD_RELOC_16C_DISP24a_C: howto manager. +* BFD_RELOC_16C_IMM04: howto manager. +* BFD_RELOC_16C_IMM04_C: howto manager. +* BFD_RELOC_16C_IMM16: howto manager. +* BFD_RELOC_16C_IMM16_C: howto manager. +* BFD_RELOC_16C_IMM20: howto manager. +* BFD_RELOC_16C_IMM20_C: howto manager. +* BFD_RELOC_16C_IMM24: howto manager. +* BFD_RELOC_16C_IMM24_C: howto manager. +* BFD_RELOC_16C_IMM32: howto manager. +* BFD_RELOC_16C_IMM32_C: howto manager. +* BFD_RELOC_16C_NUM08: howto manager. +* BFD_RELOC_16C_NUM08_C: howto manager. +* BFD_RELOC_16C_NUM16: howto manager. +* BFD_RELOC_16C_NUM16_C: howto manager. +* BFD_RELOC_16C_NUM32: howto manager. +* BFD_RELOC_16C_NUM32_C: howto manager. +* BFD_RELOC_16C_REG04: howto manager. +* BFD_RELOC_16C_REG04_C: howto manager. +* BFD_RELOC_16C_REG04a: howto manager. +* BFD_RELOC_16C_REG04a_C: howto manager. +* BFD_RELOC_16C_REG14: howto manager. +* BFD_RELOC_16C_REG14_C: howto manager. +* BFD_RELOC_16C_REG16: howto manager. +* BFD_RELOC_16C_REG16_C: howto manager. +* BFD_RELOC_16C_REG20: howto manager. +* BFD_RELOC_16C_REG20_C: howto manager. +* BFD_RELOC_23_PCREL_S2: howto manager. +* BFD_RELOC_24: howto manager. +* BFD_RELOC_24_PCREL: howto manager. +* BFD_RELOC_24_PLT_PCREL: howto manager. +* BFD_RELOC_26: howto manager. +* BFD_RELOC_32: howto manager. +* BFD_RELOC_32_BASEREL: howto manager. +* BFD_RELOC_32_GOT_PCREL: howto manager. +* BFD_RELOC_32_GOTOFF: howto manager. +* BFD_RELOC_32_PCREL: howto manager. +* BFD_RELOC_32_PCREL_S2: howto manager. +* BFD_RELOC_32_PLT_PCREL: howto manager. +* BFD_RELOC_32_PLTOFF: howto manager. +* BFD_RELOC_32_SECREL: howto manager. +* BFD_RELOC_386_COPY: howto manager. +* BFD_RELOC_386_GLOB_DAT: howto manager. +* BFD_RELOC_386_GOT32: howto manager. +* BFD_RELOC_386_GOTOFF: howto manager. +* BFD_RELOC_386_GOTPC: howto manager. +* BFD_RELOC_386_JUMP_SLOT: howto manager. +* BFD_RELOC_386_PLT32: howto manager. +* BFD_RELOC_386_RELATIVE: howto manager. +* BFD_RELOC_386_TLS_DTPMOD32: howto manager. +* BFD_RELOC_386_TLS_DTPOFF32: howto manager. +* BFD_RELOC_386_TLS_GD: howto manager. +* BFD_RELOC_386_TLS_GOTIE: howto manager. +* BFD_RELOC_386_TLS_IE: howto manager. +* BFD_RELOC_386_TLS_IE_32: howto manager. +* BFD_RELOC_386_TLS_LDM: howto manager. +* BFD_RELOC_386_TLS_LDO_32: howto manager. +* BFD_RELOC_386_TLS_LE: howto manager. +* BFD_RELOC_386_TLS_LE_32: howto manager. +* BFD_RELOC_386_TLS_TPOFF: howto manager. +* BFD_RELOC_386_TLS_TPOFF32: howto manager. +* BFD_RELOC_390_12: howto manager. +* BFD_RELOC_390_20: howto manager. +* BFD_RELOC_390_COPY: howto manager. +* BFD_RELOC_390_GLOB_DAT: howto manager. +* BFD_RELOC_390_GOT12: howto manager. +* BFD_RELOC_390_GOT16: howto manager. +* BFD_RELOC_390_GOT20: howto manager. +* BFD_RELOC_390_GOT64: howto manager. +* BFD_RELOC_390_GOTENT: howto manager. +* BFD_RELOC_390_GOTOFF64: howto manager. +* BFD_RELOC_390_GOTPC: howto manager. +* BFD_RELOC_390_GOTPCDBL: howto manager. +* BFD_RELOC_390_GOTPLT12: howto manager. +* BFD_RELOC_390_GOTPLT16: howto manager. +* BFD_RELOC_390_GOTPLT20: howto manager. +* BFD_RELOC_390_GOTPLT32: howto manager. +* BFD_RELOC_390_GOTPLT64: howto manager. +* BFD_RELOC_390_GOTPLTENT: howto manager. +* BFD_RELOC_390_JMP_SLOT: howto manager. +* BFD_RELOC_390_PC16DBL: howto manager. +* BFD_RELOC_390_PC32DBL: howto manager. +* BFD_RELOC_390_PLT16DBL: howto manager. +* BFD_RELOC_390_PLT32: howto manager. +* BFD_RELOC_390_PLT32DBL: howto manager. +* BFD_RELOC_390_PLT64: howto manager. +* BFD_RELOC_390_PLTOFF16: howto manager. +* BFD_RELOC_390_PLTOFF32: howto manager. +* BFD_RELOC_390_PLTOFF64: howto manager. +* BFD_RELOC_390_RELATIVE: howto manager. +* BFD_RELOC_390_TLS_DTPMOD: howto manager. +* BFD_RELOC_390_TLS_DTPOFF: howto manager. +* BFD_RELOC_390_TLS_GD32: howto manager. +* BFD_RELOC_390_TLS_GD64: howto manager. +* BFD_RELOC_390_TLS_GDCALL: howto manager. +* BFD_RELOC_390_TLS_GOTIE12: howto manager. +* BFD_RELOC_390_TLS_GOTIE20: howto manager. +* BFD_RELOC_390_TLS_GOTIE32: howto manager. +* BFD_RELOC_390_TLS_GOTIE64: howto manager. +* BFD_RELOC_390_TLS_IE32: howto manager. +* BFD_RELOC_390_TLS_IE64: howto manager. +* BFD_RELOC_390_TLS_IEENT: howto manager. +* BFD_RELOC_390_TLS_LDCALL: howto manager. +* BFD_RELOC_390_TLS_LDM32: howto manager. +* BFD_RELOC_390_TLS_LDM64: howto manager. +* BFD_RELOC_390_TLS_LDO32: howto manager. +* BFD_RELOC_390_TLS_LDO64: howto manager. +* BFD_RELOC_390_TLS_LE32: howto manager. +* BFD_RELOC_390_TLS_LE64: howto manager. +* BFD_RELOC_390_TLS_LOAD: howto manager. +* BFD_RELOC_390_TLS_TPOFF: howto manager. +* BFD_RELOC_64: howto manager. +* BFD_RELOC_64_PCREL: howto manager. +* BFD_RELOC_64_PLT_PCREL: howto manager. +* BFD_RELOC_64_PLTOFF: howto manager. +* BFD_RELOC_68K_GLOB_DAT: howto manager. +* BFD_RELOC_68K_JMP_SLOT: howto manager. +* BFD_RELOC_68K_RELATIVE: howto manager. +* BFD_RELOC_8: howto manager. +* BFD_RELOC_860_COPY: howto manager. +* BFD_RELOC_860_GLOB_DAT: howto manager. +* BFD_RELOC_860_HAGOT: howto manager. +* BFD_RELOC_860_HAGOTOFF: howto manager. +* BFD_RELOC_860_HAPC: howto manager. +* BFD_RELOC_860_HIGH: howto manager. +* BFD_RELOC_860_HIGHADJ: howto manager. +* BFD_RELOC_860_HIGOT: howto manager. +* BFD_RELOC_860_HIGOTOFF: howto manager. +* BFD_RELOC_860_JUMP_SLOT: howto manager. +* BFD_RELOC_860_LOGOT0: howto manager. +* BFD_RELOC_860_LOGOT1: howto manager. +* BFD_RELOC_860_LOGOTOFF0: howto manager. +* BFD_RELOC_860_LOGOTOFF1: howto manager. +* BFD_RELOC_860_LOGOTOFF2: howto manager. +* BFD_RELOC_860_LOGOTOFF3: howto manager. +* BFD_RELOC_860_LOPC: howto manager. +* BFD_RELOC_860_LOW0: howto manager. +* BFD_RELOC_860_LOW1: howto manager. +* BFD_RELOC_860_LOW2: howto manager. +* BFD_RELOC_860_LOW3: howto manager. +* BFD_RELOC_860_PC16: howto manager. +* BFD_RELOC_860_PC26: howto manager. +* BFD_RELOC_860_PLT26: howto manager. +* BFD_RELOC_860_RELATIVE: howto manager. +* BFD_RELOC_860_SPGOT0: howto manager. +* BFD_RELOC_860_SPGOT1: howto manager. +* BFD_RELOC_860_SPGOTOFF0: howto manager. +* BFD_RELOC_860_SPGOTOFF1: howto manager. +* BFD_RELOC_860_SPLIT0: howto manager. +* BFD_RELOC_860_SPLIT1: howto manager. +* BFD_RELOC_860_SPLIT2: howto manager. +* BFD_RELOC_8_BASEREL: howto manager. +* BFD_RELOC_8_FFnn: howto manager. +* BFD_RELOC_8_GOT_PCREL: howto manager. +* BFD_RELOC_8_GOTOFF: howto manager. +* BFD_RELOC_8_PCREL: howto manager. +* BFD_RELOC_8_PLT_PCREL: howto manager. +* BFD_RELOC_8_PLTOFF: howto manager. +* BFD_RELOC_ALPHA_BRSGP: howto manager. +* BFD_RELOC_ALPHA_CODEADDR: howto manager. +* BFD_RELOC_ALPHA_DTPMOD64: howto manager. +* BFD_RELOC_ALPHA_DTPREL16: howto manager. +* BFD_RELOC_ALPHA_DTPREL64: howto manager. +* BFD_RELOC_ALPHA_DTPREL_HI16: howto manager. +* BFD_RELOC_ALPHA_DTPREL_LO16: howto manager. +* BFD_RELOC_ALPHA_ELF_LITERAL: howto manager. +* BFD_RELOC_ALPHA_GOTDTPREL16: howto manager. +* BFD_RELOC_ALPHA_GOTTPREL16: howto manager. +* BFD_RELOC_ALPHA_GPDISP: howto manager. +* BFD_RELOC_ALPHA_GPDISP_HI16: howto manager. +* BFD_RELOC_ALPHA_GPDISP_LO16: howto manager. +* BFD_RELOC_ALPHA_GPREL_HI16: howto manager. +* BFD_RELOC_ALPHA_GPREL_LO16: howto manager. +* BFD_RELOC_ALPHA_HINT: howto manager. +* BFD_RELOC_ALPHA_LINKAGE: howto manager. +* BFD_RELOC_ALPHA_LITERAL: howto manager. +* BFD_RELOC_ALPHA_LITUSE: howto manager. +* BFD_RELOC_ALPHA_TLSGD: howto manager. +* BFD_RELOC_ALPHA_TLSLDM: howto manager. +* BFD_RELOC_ALPHA_TPREL16: howto manager. +* BFD_RELOC_ALPHA_TPREL64: howto manager. +* BFD_RELOC_ALPHA_TPREL_HI16: howto manager. +* BFD_RELOC_ALPHA_TPREL_LO16: howto manager. +* BFD_RELOC_ARC_B22_PCREL: howto manager. +* BFD_RELOC_ARC_B26: howto manager. +* BFD_RELOC_ARM_ADR_IMM: howto manager. +* BFD_RELOC_ARM_ADRL_IMMEDIATE: howto manager. +* BFD_RELOC_ARM_COPY: howto manager. +* BFD_RELOC_ARM_CP_OFF_IMM: howto manager. +* BFD_RELOC_ARM_CP_OFF_IMM_S2: howto manager. +* BFD_RELOC_ARM_GLOB_DAT: howto manager. +* BFD_RELOC_ARM_GOT12: howto manager. +* BFD_RELOC_ARM_GOT32: howto manager. +* BFD_RELOC_ARM_GOTOFF: howto manager. +* BFD_RELOC_ARM_GOTPC: howto manager. +* BFD_RELOC_ARM_HWLITERAL: howto manager. +* BFD_RELOC_ARM_IMMEDIATE: howto manager. +* BFD_RELOC_ARM_IN_POOL: howto manager. +* BFD_RELOC_ARM_JUMP_SLOT: howto manager. +* BFD_RELOC_ARM_LDR_IMM: howto manager. +* BFD_RELOC_ARM_LITERAL: howto manager. +* BFD_RELOC_ARM_MULTI: howto manager. +* BFD_RELOC_ARM_OFFSET_IMM: howto manager. +* BFD_RELOC_ARM_OFFSET_IMM8: howto manager. +* BFD_RELOC_ARM_PCREL_BLX: howto manager. +* BFD_RELOC_ARM_PCREL_BRANCH: howto manager. +* BFD_RELOC_ARM_PLT32: howto manager. +* BFD_RELOC_ARM_PREL31: howto manager. +* BFD_RELOC_ARM_RELATIVE: howto manager. +* BFD_RELOC_ARM_ROSEGREL32: howto manager. +* BFD_RELOC_ARM_SBREL32: howto manager. +* BFD_RELOC_ARM_SHIFT_IMM: howto manager. +* BFD_RELOC_ARM_SMI: howto manager. +* BFD_RELOC_ARM_SWI: howto manager. +* BFD_RELOC_ARM_TARGET1: howto manager. +* BFD_RELOC_ARM_TARGET2: howto manager. +* BFD_RELOC_ARM_THUMB_ADD: howto manager. +* BFD_RELOC_ARM_THUMB_IMM: howto manager. +* BFD_RELOC_ARM_THUMB_OFFSET: howto manager. +* BFD_RELOC_ARM_THUMB_SHIFT: howto manager. +* BFD_RELOC_AVR_13_PCREL: howto manager. +* BFD_RELOC_AVR_16_PM: howto manager. +* BFD_RELOC_AVR_6: howto manager. +* BFD_RELOC_AVR_6_ADIW: howto manager. +* BFD_RELOC_AVR_7_PCREL: howto manager. +* BFD_RELOC_AVR_CALL: howto manager. +* BFD_RELOC_AVR_HH8_LDI: howto manager. +* BFD_RELOC_AVR_HH8_LDI_NEG: howto manager. +* BFD_RELOC_AVR_HH8_LDI_PM: howto manager. +* BFD_RELOC_AVR_HH8_LDI_PM_NEG: howto manager. +* BFD_RELOC_AVR_HI8_LDI: howto manager. +* BFD_RELOC_AVR_HI8_LDI_NEG: howto manager. +* BFD_RELOC_AVR_HI8_LDI_PM: howto manager. +* BFD_RELOC_AVR_HI8_LDI_PM_NEG: howto manager. +* BFD_RELOC_AVR_LDI: howto manager. +* BFD_RELOC_AVR_LO8_LDI: howto manager. +* BFD_RELOC_AVR_LO8_LDI_NEG: howto manager. +* BFD_RELOC_AVR_LO8_LDI_PM: howto manager. +* BFD_RELOC_AVR_LO8_LDI_PM_NEG: howto manager. +* bfd_reloc_code_type: howto manager. +* BFD_RELOC_CRIS_16_GOT: howto manager. +* BFD_RELOC_CRIS_16_GOTPLT: howto manager. +* BFD_RELOC_CRIS_32_GOT: howto manager. +* BFD_RELOC_CRIS_32_GOTPLT: howto manager. +* BFD_RELOC_CRIS_32_GOTREL: howto manager. +* BFD_RELOC_CRIS_32_PLT_GOTREL: howto manager. +* BFD_RELOC_CRIS_32_PLT_PCREL: howto manager. +* BFD_RELOC_CRIS_BDISP8: howto manager. +* BFD_RELOC_CRIS_COPY: howto manager. +* BFD_RELOC_CRIS_GLOB_DAT: howto manager. +* BFD_RELOC_CRIS_JUMP_SLOT: howto manager. +* BFD_RELOC_CRIS_LAPCQ_OFFSET: howto manager. +* BFD_RELOC_CRIS_RELATIVE: howto manager. +* BFD_RELOC_CRIS_SIGNED_16: howto manager. +* BFD_RELOC_CRIS_SIGNED_6: howto manager. +* BFD_RELOC_CRIS_SIGNED_8: howto manager. +* BFD_RELOC_CRIS_UNSIGNED_16: howto manager. +* BFD_RELOC_CRIS_UNSIGNED_4: howto manager. +* BFD_RELOC_CRIS_UNSIGNED_5: howto manager. +* BFD_RELOC_CRIS_UNSIGNED_6: howto manager. +* BFD_RELOC_CRIS_UNSIGNED_8: howto manager. +* BFD_RELOC_CRX_ABS16: howto manager. +* BFD_RELOC_CRX_ABS32: howto manager. +* BFD_RELOC_CRX_IMM16: howto manager. +* BFD_RELOC_CRX_IMM32: howto manager. +* BFD_RELOC_CRX_NUM16: howto manager. +* BFD_RELOC_CRX_NUM32: howto manager. +* BFD_RELOC_CRX_NUM8: howto manager. +* BFD_RELOC_CRX_REGREL12: howto manager. +* BFD_RELOC_CRX_REGREL22: howto manager. +* BFD_RELOC_CRX_REGREL28: howto manager. +* BFD_RELOC_CRX_REGREL32: howto manager. +* BFD_RELOC_CRX_REL16: howto manager. +* BFD_RELOC_CRX_REL24: howto manager. +* BFD_RELOC_CRX_REL32: howto manager. +* BFD_RELOC_CRX_REL4: howto manager. +* BFD_RELOC_CRX_REL8: howto manager. +* BFD_RELOC_CRX_REL8_CMP: howto manager. +* BFD_RELOC_CRX_SWITCH16: howto manager. +* BFD_RELOC_CRX_SWITCH32: howto manager. +* BFD_RELOC_CRX_SWITCH8: howto manager. +* BFD_RELOC_CTOR: howto manager. +* BFD_RELOC_D10V_10_PCREL_L: howto manager. +* BFD_RELOC_D10V_10_PCREL_R: howto manager. +* BFD_RELOC_D10V_18: howto manager. +* BFD_RELOC_D10V_18_PCREL: howto manager. +* BFD_RELOC_D30V_15: howto manager. +* BFD_RELOC_D30V_15_PCREL: howto manager. +* BFD_RELOC_D30V_15_PCREL_R: howto manager. +* BFD_RELOC_D30V_21: howto manager. +* BFD_RELOC_D30V_21_PCREL: howto manager. +* BFD_RELOC_D30V_21_PCREL_R: howto manager. +* BFD_RELOC_D30V_32: howto manager. +* BFD_RELOC_D30V_32_PCREL: howto manager. +* BFD_RELOC_D30V_6: howto manager. +* BFD_RELOC_D30V_9_PCREL: howto manager. +* BFD_RELOC_D30V_9_PCREL_R: howto manager. +* BFD_RELOC_DLX_HI16_S: howto manager. +* BFD_RELOC_DLX_JMP26: howto manager. +* BFD_RELOC_DLX_LO16: howto manager. +* BFD_RELOC_FR30_10_IN_8: howto manager. +* BFD_RELOC_FR30_12_PCREL: howto manager. +* BFD_RELOC_FR30_20: howto manager. +* BFD_RELOC_FR30_48: howto manager. +* BFD_RELOC_FR30_6_IN_4: howto manager. +* BFD_RELOC_FR30_8_IN_8: howto manager. +* BFD_RELOC_FR30_9_IN_8: howto manager. +* BFD_RELOC_FR30_9_PCREL: howto manager. +* BFD_RELOC_FRV_FUNCDESC: howto manager. +* BFD_RELOC_FRV_FUNCDESC_GOT12: howto manager. +* BFD_RELOC_FRV_FUNCDESC_GOTHI: howto manager. +* BFD_RELOC_FRV_FUNCDESC_GOTLO: howto manager. +* BFD_RELOC_FRV_FUNCDESC_GOTOFF12: howto manager. +* BFD_RELOC_FRV_FUNCDESC_GOTOFFHI: howto manager. +* BFD_RELOC_FRV_FUNCDESC_GOTOFFLO: howto manager. +* BFD_RELOC_FRV_FUNCDESC_VALUE: howto manager. +* BFD_RELOC_FRV_GETTLSOFF: howto manager. +* BFD_RELOC_FRV_GETTLSOFF_RELAX: howto manager. +* BFD_RELOC_FRV_GOT12: howto manager. +* BFD_RELOC_FRV_GOTHI: howto manager. +* BFD_RELOC_FRV_GOTLO: howto manager. +* BFD_RELOC_FRV_GOTOFF12: howto manager. +* BFD_RELOC_FRV_GOTOFFHI: howto manager. +* BFD_RELOC_FRV_GOTOFFLO: howto manager. +* BFD_RELOC_FRV_GOTTLSDESC12: howto manager. +* BFD_RELOC_FRV_GOTTLSDESCHI: howto manager. +* BFD_RELOC_FRV_GOTTLSDESCLO: howto manager. +* BFD_RELOC_FRV_GOTTLSOFF12: howto manager. +* BFD_RELOC_FRV_GOTTLSOFFHI: howto manager. +* BFD_RELOC_FRV_GOTTLSOFFLO: howto manager. +* BFD_RELOC_FRV_GPREL12: howto manager. +* BFD_RELOC_FRV_GPREL32: howto manager. +* BFD_RELOC_FRV_GPRELHI: howto manager. +* BFD_RELOC_FRV_GPRELLO: howto manager. +* BFD_RELOC_FRV_GPRELU12: howto manager. +* BFD_RELOC_FRV_HI16: howto manager. +* BFD_RELOC_FRV_LABEL16: howto manager. +* BFD_RELOC_FRV_LABEL24: howto manager. +* BFD_RELOC_FRV_LO16: howto manager. +* BFD_RELOC_FRV_TLSDESC_RELAX: howto manager. +* BFD_RELOC_FRV_TLSDESC_VALUE: howto manager. +* BFD_RELOC_FRV_TLSMOFF: howto manager. +* BFD_RELOC_FRV_TLSMOFF12: howto manager. +* BFD_RELOC_FRV_TLSMOFFHI: howto manager. +* BFD_RELOC_FRV_TLSMOFFLO: howto manager. +* BFD_RELOC_FRV_TLSOFF: howto manager. +* BFD_RELOC_FRV_TLSOFF_RELAX: howto manager. +* BFD_RELOC_GPREL16: howto manager. +* BFD_RELOC_GPREL32: howto manager. +* BFD_RELOC_H8_DIR16A8: howto manager. +* BFD_RELOC_H8_DIR16R8: howto manager. +* BFD_RELOC_H8_DIR24A8: howto manager. +* BFD_RELOC_H8_DIR24R8: howto manager. +* BFD_RELOC_H8_DIR32A16: howto manager. +* BFD_RELOC_HI16: howto manager. +* BFD_RELOC_HI16_BASEREL: howto manager. +* BFD_RELOC_HI16_GOTOFF: howto manager. +* BFD_RELOC_HI16_PLTOFF: howto manager. +* BFD_RELOC_HI16_S: howto manager. +* BFD_RELOC_HI16_S_BASEREL: howto manager. +* BFD_RELOC_HI16_S_GOTOFF: howto manager. +* BFD_RELOC_HI16_S_PLTOFF: howto manager. +* BFD_RELOC_HI22: howto manager. +* BFD_RELOC_I370_D12: howto manager. +* BFD_RELOC_I960_CALLJ: howto manager. +* BFD_RELOC_IA64_COPY: howto manager. +* BFD_RELOC_IA64_DIR32LSB: howto manager. +* BFD_RELOC_IA64_DIR32MSB: howto manager. +* BFD_RELOC_IA64_DIR64LSB: howto manager. +* BFD_RELOC_IA64_DIR64MSB: howto manager. +* BFD_RELOC_IA64_DTPMOD64LSB: howto manager. +* BFD_RELOC_IA64_DTPMOD64MSB: howto manager. +* BFD_RELOC_IA64_DTPREL14: howto manager. +* BFD_RELOC_IA64_DTPREL22: howto manager. +* BFD_RELOC_IA64_DTPREL32LSB: howto manager. +* BFD_RELOC_IA64_DTPREL32MSB: howto manager. +* BFD_RELOC_IA64_DTPREL64I: howto manager. +* BFD_RELOC_IA64_DTPREL64LSB: howto manager. +* BFD_RELOC_IA64_DTPREL64MSB: howto manager. +* BFD_RELOC_IA64_FPTR32LSB: howto manager. +* BFD_RELOC_IA64_FPTR32MSB: howto manager. +* BFD_RELOC_IA64_FPTR64I: howto manager. +* BFD_RELOC_IA64_FPTR64LSB: howto manager. +* BFD_RELOC_IA64_FPTR64MSB: howto manager. +* BFD_RELOC_IA64_GPREL22: howto manager. +* BFD_RELOC_IA64_GPREL32LSB: howto manager. +* BFD_RELOC_IA64_GPREL32MSB: howto manager. +* BFD_RELOC_IA64_GPREL64I: howto manager. +* BFD_RELOC_IA64_GPREL64LSB: howto manager. +* BFD_RELOC_IA64_GPREL64MSB: howto manager. +* BFD_RELOC_IA64_IMM14: howto manager. +* BFD_RELOC_IA64_IMM22: howto manager. +* BFD_RELOC_IA64_IMM64: howto manager. +* BFD_RELOC_IA64_IPLTLSB: howto manager. +* BFD_RELOC_IA64_IPLTMSB: howto manager. +* BFD_RELOC_IA64_LDXMOV: howto manager. +* BFD_RELOC_IA64_LTOFF22: howto manager. +* BFD_RELOC_IA64_LTOFF22X: howto manager. +* BFD_RELOC_IA64_LTOFF64I: howto manager. +* BFD_RELOC_IA64_LTOFF_DTPMOD22: howto manager. +* BFD_RELOC_IA64_LTOFF_DTPREL22: howto manager. +* BFD_RELOC_IA64_LTOFF_FPTR22: howto manager. +* BFD_RELOC_IA64_LTOFF_FPTR32LSB: howto manager. +* BFD_RELOC_IA64_LTOFF_FPTR32MSB: howto manager. +* BFD_RELOC_IA64_LTOFF_FPTR64I: howto manager. +* BFD_RELOC_IA64_LTOFF_FPTR64LSB: howto manager. +* BFD_RELOC_IA64_LTOFF_FPTR64MSB: howto manager. +* BFD_RELOC_IA64_LTOFF_TPREL22: howto manager. +* BFD_RELOC_IA64_LTV32LSB: howto manager. +* BFD_RELOC_IA64_LTV32MSB: howto manager. +* BFD_RELOC_IA64_LTV64LSB: howto manager. +* BFD_RELOC_IA64_LTV64MSB: howto manager. +* BFD_RELOC_IA64_PCREL21B: howto manager. +* BFD_RELOC_IA64_PCREL21BI: howto manager. +* BFD_RELOC_IA64_PCREL21F: howto manager. +* BFD_RELOC_IA64_PCREL21M: howto manager. +* BFD_RELOC_IA64_PCREL22: howto manager. +* BFD_RELOC_IA64_PCREL32LSB: howto manager. +* BFD_RELOC_IA64_PCREL32MSB: howto manager. +* BFD_RELOC_IA64_PCREL60B: howto manager. +* BFD_RELOC_IA64_PCREL64I: howto manager. +* BFD_RELOC_IA64_PCREL64LSB: howto manager. +* BFD_RELOC_IA64_PCREL64MSB: howto manager. +* BFD_RELOC_IA64_PLTOFF22: howto manager. +* BFD_RELOC_IA64_PLTOFF64I: howto manager. +* BFD_RELOC_IA64_PLTOFF64LSB: howto manager. +* BFD_RELOC_IA64_PLTOFF64MSB: howto manager. +* BFD_RELOC_IA64_REL32LSB: howto manager. +* BFD_RELOC_IA64_REL32MSB: howto manager. +* BFD_RELOC_IA64_REL64LSB: howto manager. +* BFD_RELOC_IA64_REL64MSB: howto manager. +* BFD_RELOC_IA64_SECREL32LSB: howto manager. +* BFD_RELOC_IA64_SECREL32MSB: howto manager. +* BFD_RELOC_IA64_SECREL64LSB: howto manager. +* BFD_RELOC_IA64_SECREL64MSB: howto manager. +* BFD_RELOC_IA64_SEGREL32LSB: howto manager. +* BFD_RELOC_IA64_SEGREL32MSB: howto manager. +* BFD_RELOC_IA64_SEGREL64LSB: howto manager. +* BFD_RELOC_IA64_SEGREL64MSB: howto manager. +* BFD_RELOC_IA64_TPREL14: howto manager. +* BFD_RELOC_IA64_TPREL22: howto manager. +* BFD_RELOC_IA64_TPREL64I: howto manager. +* BFD_RELOC_IA64_TPREL64LSB: howto manager. +* BFD_RELOC_IA64_TPREL64MSB: howto manager. +* BFD_RELOC_IP2K_ADDR16CJP: howto manager. +* BFD_RELOC_IP2K_BANK: howto manager. +* BFD_RELOC_IP2K_EX8DATA: howto manager. +* BFD_RELOC_IP2K_FR9: howto manager. +* BFD_RELOC_IP2K_FR_OFFSET: howto manager. +* BFD_RELOC_IP2K_HI8DATA: howto manager. +* BFD_RELOC_IP2K_HI8INSN: howto manager. +* BFD_RELOC_IP2K_LO8DATA: howto manager. +* BFD_RELOC_IP2K_LO8INSN: howto manager. +* BFD_RELOC_IP2K_PAGE3: howto manager. +* BFD_RELOC_IP2K_PC_SKIP: howto manager. +* BFD_RELOC_IP2K_TEXT: howto manager. +* BFD_RELOC_IQ2000_OFFSET_16: howto manager. +* BFD_RELOC_IQ2000_OFFSET_21: howto manager. +* BFD_RELOC_IQ2000_UHI16: howto manager. +* BFD_RELOC_LO10: howto manager. +* BFD_RELOC_LO16: howto manager. +* BFD_RELOC_LO16_BASEREL: howto manager. +* BFD_RELOC_LO16_GOTOFF: howto manager. +* BFD_RELOC_LO16_PLTOFF: howto manager. +* BFD_RELOC_M32R_10_PCREL: howto manager. +* BFD_RELOC_M32R_18_PCREL: howto manager. +* BFD_RELOC_M32R_24: howto manager. +* BFD_RELOC_M32R_26_PCREL: howto manager. +* BFD_RELOC_M32R_26_PLTREL: howto manager. +* BFD_RELOC_M32R_COPY: howto manager. +* BFD_RELOC_M32R_GLOB_DAT: howto manager. +* BFD_RELOC_M32R_GOT16_HI_SLO: howto manager. +* BFD_RELOC_M32R_GOT16_HI_ULO: howto manager. +* BFD_RELOC_M32R_GOT16_LO: howto manager. +* BFD_RELOC_M32R_GOT24: howto manager. +* BFD_RELOC_M32R_GOTOFF: howto manager. +* BFD_RELOC_M32R_GOTOFF_HI_SLO: howto manager. +* BFD_RELOC_M32R_GOTOFF_HI_ULO: howto manager. +* BFD_RELOC_M32R_GOTOFF_LO: howto manager. +* BFD_RELOC_M32R_GOTPC24: howto manager. +* BFD_RELOC_M32R_GOTPC_HI_SLO: howto manager. +* BFD_RELOC_M32R_GOTPC_HI_ULO: howto manager. +* BFD_RELOC_M32R_GOTPC_LO: howto manager. +* BFD_RELOC_M32R_HI16_SLO: howto manager. +* BFD_RELOC_M32R_HI16_ULO: howto manager. +* BFD_RELOC_M32R_JMP_SLOT: howto manager. +* BFD_RELOC_M32R_LO16: howto manager. +* BFD_RELOC_M32R_RELATIVE: howto manager. +* BFD_RELOC_M32R_SDA16: howto manager. +* BFD_RELOC_M68HC11_24: howto manager. +* BFD_RELOC_M68HC11_3B: howto manager. +* BFD_RELOC_M68HC11_HI8: howto manager. +* BFD_RELOC_M68HC11_LO16: howto manager. +* BFD_RELOC_M68HC11_LO8: howto manager. +* BFD_RELOC_M68HC11_PAGE: howto manager. +* BFD_RELOC_M68HC11_RL_GROUP: howto manager. +* BFD_RELOC_M68HC11_RL_JUMP: howto manager. +* BFD_RELOC_M68HC12_5B: howto manager. +* BFD_RELOC_MCORE_PCREL_32: howto manager. +* BFD_RELOC_MCORE_PCREL_IMM11BY2: howto manager. +* BFD_RELOC_MCORE_PCREL_IMM4BY2: howto manager. +* BFD_RELOC_MCORE_PCREL_IMM8BY4: howto manager. +* BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2: howto manager. +* BFD_RELOC_MCORE_RVA: howto manager. +* BFD_RELOC_MIPS16_GPREL: howto manager. +* BFD_RELOC_MIPS16_HI16: howto manager. +* BFD_RELOC_MIPS16_HI16_S: howto manager. +* BFD_RELOC_MIPS16_JMP: howto manager. +* BFD_RELOC_MIPS16_LO16: howto manager. +* BFD_RELOC_MIPS_CALL16: howto manager. +* BFD_RELOC_MIPS_CALL_HI16: howto manager. +* BFD_RELOC_MIPS_CALL_LO16: howto manager. +* BFD_RELOC_MIPS_DELETE: howto manager. +* BFD_RELOC_MIPS_GOT16: howto manager. +* BFD_RELOC_MIPS_GOT_DISP: howto manager. +* BFD_RELOC_MIPS_GOT_HI16: howto manager. +* BFD_RELOC_MIPS_GOT_LO16: howto manager. +* BFD_RELOC_MIPS_GOT_OFST: howto manager. +* BFD_RELOC_MIPS_GOT_PAGE: howto manager. +* BFD_RELOC_MIPS_HIGHER: howto manager. +* BFD_RELOC_MIPS_HIGHEST: howto manager. +* BFD_RELOC_MIPS_INSERT_A: howto manager. +* BFD_RELOC_MIPS_INSERT_B: howto manager. +* BFD_RELOC_MIPS_JALR: howto manager. +* BFD_RELOC_MIPS_JMP: howto manager. +* BFD_RELOC_MIPS_LITERAL: howto manager. +* BFD_RELOC_MIPS_REL16: howto manager. +* BFD_RELOC_MIPS_RELGOT: howto manager. +* BFD_RELOC_MIPS_SCN_DISP: howto manager. +* BFD_RELOC_MIPS_SHIFT5: howto manager. +* BFD_RELOC_MIPS_SHIFT6: howto manager. +* BFD_RELOC_MIPS_SUB: howto manager. +* BFD_RELOC_MIPS_TLS_DTPMOD32: howto manager. +* BFD_RELOC_MIPS_TLS_DTPMOD64: howto manager. +* BFD_RELOC_MIPS_TLS_DTPREL32: howto manager. +* BFD_RELOC_MIPS_TLS_DTPREL64: howto manager. +* BFD_RELOC_MIPS_TLS_DTPREL_HI16: howto manager. +* BFD_RELOC_MIPS_TLS_DTPREL_LO16: howto manager. +* BFD_RELOC_MIPS_TLS_GD: howto manager. +* BFD_RELOC_MIPS_TLS_GOTTPREL: howto manager. +* BFD_RELOC_MIPS_TLS_LDM: howto manager. +* BFD_RELOC_MIPS_TLS_TPREL32: howto manager. +* BFD_RELOC_MIPS_TLS_TPREL64: howto manager. +* BFD_RELOC_MIPS_TLS_TPREL_HI16: howto manager. +* BFD_RELOC_MIPS_TLS_TPREL_LO16: howto manager. +* BFD_RELOC_MMIX_ADDR19: howto manager. +* BFD_RELOC_MMIX_ADDR27: howto manager. +* BFD_RELOC_MMIX_BASE_PLUS_OFFSET: howto manager. +* BFD_RELOC_MMIX_CBRANCH: howto manager. +* BFD_RELOC_MMIX_CBRANCH_1: howto manager. +* BFD_RELOC_MMIX_CBRANCH_2: howto manager. +* BFD_RELOC_MMIX_CBRANCH_3: howto manager. +* BFD_RELOC_MMIX_CBRANCH_J: howto manager. +* BFD_RELOC_MMIX_GETA: howto manager. +* BFD_RELOC_MMIX_GETA_1: howto manager. +* BFD_RELOC_MMIX_GETA_2: howto manager. +* BFD_RELOC_MMIX_GETA_3: howto manager. +* BFD_RELOC_MMIX_JMP: howto manager. +* BFD_RELOC_MMIX_JMP_1: howto manager. +* BFD_RELOC_MMIX_JMP_2: howto manager. +* BFD_RELOC_MMIX_JMP_3: howto manager. +* BFD_RELOC_MMIX_LOCAL: howto manager. +* BFD_RELOC_MMIX_PUSHJ: howto manager. +* BFD_RELOC_MMIX_PUSHJ_1: howto manager. +* BFD_RELOC_MMIX_PUSHJ_2: howto manager. +* BFD_RELOC_MMIX_PUSHJ_3: howto manager. +* BFD_RELOC_MMIX_PUSHJ_STUBBABLE: howto manager. +* BFD_RELOC_MMIX_REG: howto manager. +* BFD_RELOC_MMIX_REG_OR_BYTE: howto manager. +* BFD_RELOC_MN10300_16_PCREL: howto manager. +* BFD_RELOC_MN10300_32_PCREL: howto manager. +* BFD_RELOC_MN10300_COPY: howto manager. +* BFD_RELOC_MN10300_GLOB_DAT: howto manager. +* BFD_RELOC_MN10300_GOT16: howto manager. +* BFD_RELOC_MN10300_GOT24: howto manager. +* BFD_RELOC_MN10300_GOT32: howto manager. +* BFD_RELOC_MN10300_GOTOFF24: howto manager. +* BFD_RELOC_MN10300_JMP_SLOT: howto manager. +* BFD_RELOC_MN10300_RELATIVE: howto manager. +* BFD_RELOC_MSP430_10_PCREL: howto manager. +* BFD_RELOC_MSP430_16: howto manager. +* BFD_RELOC_MSP430_16_BYTE: howto manager. +* BFD_RELOC_MSP430_16_PCREL: howto manager. +* BFD_RELOC_MSP430_16_PCREL_BYTE: howto manager. +* BFD_RELOC_MSP430_2X_PCREL: howto manager. +* BFD_RELOC_MSP430_RL_PCREL: howto manager. +* BFD_RELOC_NONE: howto manager. +* BFD_RELOC_NS32K_DISP_16: howto manager. +* BFD_RELOC_NS32K_DISP_16_PCREL: howto manager. +* BFD_RELOC_NS32K_DISP_32: howto manager. +* BFD_RELOC_NS32K_DISP_32_PCREL: howto manager. +* BFD_RELOC_NS32K_DISP_8: howto manager. +* BFD_RELOC_NS32K_DISP_8_PCREL: howto manager. +* BFD_RELOC_NS32K_IMM_16: howto manager. +* BFD_RELOC_NS32K_IMM_16_PCREL: howto manager. +* BFD_RELOC_NS32K_IMM_32: howto manager. +* BFD_RELOC_NS32K_IMM_32_PCREL: howto manager. +* BFD_RELOC_NS32K_IMM_8: howto manager. +* BFD_RELOC_NS32K_IMM_8_PCREL: howto manager. +* BFD_RELOC_OPENRISC_ABS_26: howto manager. +* BFD_RELOC_OPENRISC_REL_26: howto manager. +* BFD_RELOC_PDP11_DISP_6_PCREL: howto manager. +* BFD_RELOC_PDP11_DISP_8_PCREL: howto manager. +* BFD_RELOC_PJ_CODE_DIR16: howto manager. +* BFD_RELOC_PJ_CODE_DIR32: howto manager. +* BFD_RELOC_PJ_CODE_HI16: howto manager. +* BFD_RELOC_PJ_CODE_LO16: howto manager. +* BFD_RELOC_PJ_CODE_REL16: howto manager. +* BFD_RELOC_PJ_CODE_REL32: howto manager. +* BFD_RELOC_PPC64_ADDR16_DS: howto manager. +* BFD_RELOC_PPC64_ADDR16_LO_DS: howto manager. +* BFD_RELOC_PPC64_DTPREL16_DS: howto manager. +* BFD_RELOC_PPC64_DTPREL16_HIGHER: howto manager. +* BFD_RELOC_PPC64_DTPREL16_HIGHERA: howto manager. +* BFD_RELOC_PPC64_DTPREL16_HIGHEST: howto manager. +* BFD_RELOC_PPC64_DTPREL16_HIGHESTA: howto manager. +* BFD_RELOC_PPC64_DTPREL16_LO_DS: howto manager. +* BFD_RELOC_PPC64_GOT16_DS: howto manager. +* BFD_RELOC_PPC64_GOT16_LO_DS: howto manager. +* BFD_RELOC_PPC64_HIGHER: howto manager. +* BFD_RELOC_PPC64_HIGHER_S: howto manager. +* BFD_RELOC_PPC64_HIGHEST: howto manager. +* BFD_RELOC_PPC64_HIGHEST_S: howto manager. +* BFD_RELOC_PPC64_PLT16_LO_DS: howto manager. +* BFD_RELOC_PPC64_PLTGOT16: howto manager. +* BFD_RELOC_PPC64_PLTGOT16_DS: howto manager. +* BFD_RELOC_PPC64_PLTGOT16_HA: howto manager. +* BFD_RELOC_PPC64_PLTGOT16_HI: howto manager. +* BFD_RELOC_PPC64_PLTGOT16_LO: howto manager. +* BFD_RELOC_PPC64_PLTGOT16_LO_DS: howto manager. +* BFD_RELOC_PPC64_SECTOFF_DS: howto manager. +* BFD_RELOC_PPC64_SECTOFF_LO_DS: howto manager. +* BFD_RELOC_PPC64_TOC: howto manager. +* BFD_RELOC_PPC64_TOC16_DS: howto manager. +* BFD_RELOC_PPC64_TOC16_HA: howto manager. +* BFD_RELOC_PPC64_TOC16_HI: howto manager. +* BFD_RELOC_PPC64_TOC16_LO: howto manager. +* BFD_RELOC_PPC64_TOC16_LO_DS: howto manager. +* BFD_RELOC_PPC64_TPREL16_DS: howto manager. +* BFD_RELOC_PPC64_TPREL16_HIGHER: howto manager. +* BFD_RELOC_PPC64_TPREL16_HIGHERA: howto manager. +* BFD_RELOC_PPC64_TPREL16_HIGHEST: howto manager. +* BFD_RELOC_PPC64_TPREL16_HIGHESTA: howto manager. +* BFD_RELOC_PPC64_TPREL16_LO_DS: howto manager. +* BFD_RELOC_PPC_B16: howto manager. +* BFD_RELOC_PPC_B16_BRNTAKEN: howto manager. +* BFD_RELOC_PPC_B16_BRTAKEN: howto manager. +* BFD_RELOC_PPC_B26: howto manager. +* BFD_RELOC_PPC_BA16: howto manager. +* BFD_RELOC_PPC_BA16_BRNTAKEN: howto manager. +* BFD_RELOC_PPC_BA16_BRTAKEN: howto manager. +* BFD_RELOC_PPC_BA26: howto manager. +* BFD_RELOC_PPC_COPY: howto manager. +* BFD_RELOC_PPC_DTPMOD: howto manager. +* BFD_RELOC_PPC_DTPREL: howto manager. +* BFD_RELOC_PPC_DTPREL16: howto manager. +* BFD_RELOC_PPC_DTPREL16_HA: howto manager. +* BFD_RELOC_PPC_DTPREL16_HI: howto manager. +* BFD_RELOC_PPC_DTPREL16_LO: howto manager. +* BFD_RELOC_PPC_EMB_BIT_FLD: howto manager. +* BFD_RELOC_PPC_EMB_MRKREF: howto manager. +* BFD_RELOC_PPC_EMB_NADDR16: howto manager. +* BFD_RELOC_PPC_EMB_NADDR16_HA: howto manager. +* BFD_RELOC_PPC_EMB_NADDR16_HI: howto manager. +* BFD_RELOC_PPC_EMB_NADDR16_LO: howto manager. +* BFD_RELOC_PPC_EMB_NADDR32: howto manager. +* BFD_RELOC_PPC_EMB_RELSDA: howto manager. +* BFD_RELOC_PPC_EMB_RELSEC16: howto manager. +* BFD_RELOC_PPC_EMB_RELST_HA: howto manager. +* BFD_RELOC_PPC_EMB_RELST_HI: howto manager. +* BFD_RELOC_PPC_EMB_RELST_LO: howto manager. +* BFD_RELOC_PPC_EMB_SDA21: howto manager. +* BFD_RELOC_PPC_EMB_SDA2I16: howto manager. +* BFD_RELOC_PPC_EMB_SDA2REL: howto manager. +* BFD_RELOC_PPC_EMB_SDAI16: howto manager. +* BFD_RELOC_PPC_GLOB_DAT: howto manager. +* BFD_RELOC_PPC_GOT_DTPREL16: howto manager. +* BFD_RELOC_PPC_GOT_DTPREL16_HA: howto manager. +* BFD_RELOC_PPC_GOT_DTPREL16_HI: howto manager. +* BFD_RELOC_PPC_GOT_DTPREL16_LO: howto manager. +* BFD_RELOC_PPC_GOT_TLSGD16: howto manager. +* BFD_RELOC_PPC_GOT_TLSGD16_HA: howto manager. +* BFD_RELOC_PPC_GOT_TLSGD16_HI: howto manager. +* BFD_RELOC_PPC_GOT_TLSGD16_LO: howto manager. +* BFD_RELOC_PPC_GOT_TLSLD16: howto manager. +* BFD_RELOC_PPC_GOT_TLSLD16_HA: howto manager. +* BFD_RELOC_PPC_GOT_TLSLD16_HI: howto manager. +* BFD_RELOC_PPC_GOT_TLSLD16_LO: howto manager. +* BFD_RELOC_PPC_GOT_TPREL16: howto manager. +* BFD_RELOC_PPC_GOT_TPREL16_HA: howto manager. +* BFD_RELOC_PPC_GOT_TPREL16_HI: howto manager. +* BFD_RELOC_PPC_GOT_TPREL16_LO: howto manager. +* BFD_RELOC_PPC_JMP_SLOT: howto manager. +* BFD_RELOC_PPC_LOCAL24PC: howto manager. +* BFD_RELOC_PPC_RELATIVE: howto manager. +* BFD_RELOC_PPC_TLS: howto manager. +* BFD_RELOC_PPC_TOC16: howto manager. +* BFD_RELOC_PPC_TPREL: howto manager. +* BFD_RELOC_PPC_TPREL16: howto manager. +* BFD_RELOC_PPC_TPREL16_HA: howto manager. +* BFD_RELOC_PPC_TPREL16_HI: howto manager. +* BFD_RELOC_PPC_TPREL16_LO: howto manager. +* BFD_RELOC_RVA: howto manager. +* BFD_RELOC_SH_ALIGN: howto manager. +* BFD_RELOC_SH_CODE: howto manager. +* BFD_RELOC_SH_COPY: howto manager. +* BFD_RELOC_SH_COPY64: howto manager. +* BFD_RELOC_SH_COUNT: howto manager. +* BFD_RELOC_SH_DATA: howto manager. +* BFD_RELOC_SH_DISP12: howto manager. +* BFD_RELOC_SH_DISP12BY2: howto manager. +* BFD_RELOC_SH_DISP12BY4: howto manager. +* BFD_RELOC_SH_DISP12BY8: howto manager. +* BFD_RELOC_SH_DISP20: howto manager. +* BFD_RELOC_SH_DISP20BY8: howto manager. +* BFD_RELOC_SH_GLOB_DAT: howto manager. +* BFD_RELOC_SH_GLOB_DAT64: howto manager. +* BFD_RELOC_SH_GOT10BY4: howto manager. +* BFD_RELOC_SH_GOT10BY8: howto manager. +* BFD_RELOC_SH_GOT_HI16: howto manager. +* BFD_RELOC_SH_GOT_LOW16: howto manager. +* BFD_RELOC_SH_GOT_MEDHI16: howto manager. +* BFD_RELOC_SH_GOT_MEDLOW16: howto manager. +* BFD_RELOC_SH_GOTOFF_HI16: howto manager. +* BFD_RELOC_SH_GOTOFF_LOW16: howto manager. +* BFD_RELOC_SH_GOTOFF_MEDHI16: howto manager. +* BFD_RELOC_SH_GOTOFF_MEDLOW16: howto manager. +* BFD_RELOC_SH_GOTPC: howto manager. +* BFD_RELOC_SH_GOTPC_HI16: howto manager. +* BFD_RELOC_SH_GOTPC_LOW16: howto manager. +* BFD_RELOC_SH_GOTPC_MEDHI16: howto manager. +* BFD_RELOC_SH_GOTPC_MEDLOW16: howto manager. +* BFD_RELOC_SH_GOTPLT10BY4: howto manager. +* BFD_RELOC_SH_GOTPLT10BY8: howto manager. +* BFD_RELOC_SH_GOTPLT32: howto manager. +* BFD_RELOC_SH_GOTPLT_HI16: howto manager. +* BFD_RELOC_SH_GOTPLT_LOW16: howto manager. +* BFD_RELOC_SH_GOTPLT_MEDHI16: howto manager. +* BFD_RELOC_SH_GOTPLT_MEDLOW16: howto manager. +* BFD_RELOC_SH_IMM3: howto manager. +* BFD_RELOC_SH_IMM3U: howto manager. +* BFD_RELOC_SH_IMM4: howto manager. +* BFD_RELOC_SH_IMM4BY2: howto manager. +* BFD_RELOC_SH_IMM4BY4: howto manager. +* BFD_RELOC_SH_IMM8: howto manager. +* BFD_RELOC_SH_IMM8BY2: howto manager. +* BFD_RELOC_SH_IMM8BY4: howto manager. +* BFD_RELOC_SH_IMM_HI16: howto manager. +* BFD_RELOC_SH_IMM_HI16_PCREL: howto manager. +* BFD_RELOC_SH_IMM_LOW16: howto manager. +* BFD_RELOC_SH_IMM_LOW16_PCREL: howto manager. +* BFD_RELOC_SH_IMM_MEDHI16: howto manager. +* BFD_RELOC_SH_IMM_MEDHI16_PCREL: howto manager. +* BFD_RELOC_SH_IMM_MEDLOW16: howto manager. +* BFD_RELOC_SH_IMM_MEDLOW16_PCREL: howto manager. +* BFD_RELOC_SH_IMMS10: howto manager. +* BFD_RELOC_SH_IMMS10BY2: howto manager. +* BFD_RELOC_SH_IMMS10BY4: howto manager. +* BFD_RELOC_SH_IMMS10BY8: howto manager. +* BFD_RELOC_SH_IMMS16: howto manager. +* BFD_RELOC_SH_IMMS6: howto manager. +* BFD_RELOC_SH_IMMS6BY32: howto manager. +* BFD_RELOC_SH_IMMU16: howto manager. +* BFD_RELOC_SH_IMMU5: howto manager. +* BFD_RELOC_SH_IMMU6: howto manager. +* BFD_RELOC_SH_JMP_SLOT: howto manager. +* BFD_RELOC_SH_JMP_SLOT64: howto manager. +* BFD_RELOC_SH_LABEL: howto manager. +* BFD_RELOC_SH_LOOP_END: howto manager. +* BFD_RELOC_SH_LOOP_START: howto manager. +* BFD_RELOC_SH_PCDISP12BY2: howto manager. +* BFD_RELOC_SH_PCDISP8BY2: howto manager. +* BFD_RELOC_SH_PCRELIMM8BY2: howto manager. +* BFD_RELOC_SH_PCRELIMM8BY4: howto manager. +* BFD_RELOC_SH_PLT_HI16: howto manager. +* BFD_RELOC_SH_PLT_LOW16: howto manager. +* BFD_RELOC_SH_PLT_MEDHI16: howto manager. +* BFD_RELOC_SH_PLT_MEDLOW16: howto manager. +* BFD_RELOC_SH_PT_16: howto manager. +* BFD_RELOC_SH_RELATIVE: howto manager. +* BFD_RELOC_SH_RELATIVE64: howto manager. +* BFD_RELOC_SH_SHMEDIA_CODE: howto manager. +* BFD_RELOC_SH_SWITCH16: howto manager. +* BFD_RELOC_SH_SWITCH32: howto manager. +* BFD_RELOC_SH_TLS_DTPMOD32: howto manager. +* BFD_RELOC_SH_TLS_DTPOFF32: howto manager. +* BFD_RELOC_SH_TLS_GD_32: howto manager. +* BFD_RELOC_SH_TLS_IE_32: howto manager. +* BFD_RELOC_SH_TLS_LD_32: howto manager. +* BFD_RELOC_SH_TLS_LDO_32: howto manager. +* BFD_RELOC_SH_TLS_LE_32: howto manager. +* BFD_RELOC_SH_TLS_TPOFF32: howto manager. +* BFD_RELOC_SH_USES: howto manager. +* BFD_RELOC_SPARC13: howto manager. +* BFD_RELOC_SPARC22: howto manager. +* BFD_RELOC_SPARC_10: howto manager. +* BFD_RELOC_SPARC_11: howto manager. +* BFD_RELOC_SPARC_5: howto manager. +* BFD_RELOC_SPARC_6: howto manager. +* BFD_RELOC_SPARC_64: howto manager. +* BFD_RELOC_SPARC_7: howto manager. +* BFD_RELOC_SPARC_BASE13: howto manager. +* BFD_RELOC_SPARC_BASE22: howto manager. +* BFD_RELOC_SPARC_COPY: howto manager. +* BFD_RELOC_SPARC_DISP64: howto manager. +* BFD_RELOC_SPARC_GLOB_DAT: howto manager. +* BFD_RELOC_SPARC_GOT10: howto manager. +* BFD_RELOC_SPARC_GOT13: howto manager. +* BFD_RELOC_SPARC_GOT22: howto manager. +* BFD_RELOC_SPARC_H44: howto manager. +* BFD_RELOC_SPARC_HH22: howto manager. +* BFD_RELOC_SPARC_HIX22: howto manager. +* BFD_RELOC_SPARC_HM10: howto manager. +* BFD_RELOC_SPARC_JMP_SLOT: howto manager. +* BFD_RELOC_SPARC_L44: howto manager. +* BFD_RELOC_SPARC_LM22: howto manager. +* BFD_RELOC_SPARC_LOX10: howto manager. +* BFD_RELOC_SPARC_M44: howto manager. +* BFD_RELOC_SPARC_OLO10: howto manager. +* BFD_RELOC_SPARC_PC10: howto manager. +* BFD_RELOC_SPARC_PC22: howto manager. +* BFD_RELOC_SPARC_PC_HH22: howto manager. +* BFD_RELOC_SPARC_PC_HM10: howto manager. +* BFD_RELOC_SPARC_PC_LM22: howto manager. +* BFD_RELOC_SPARC_PLT32: howto manager. +* BFD_RELOC_SPARC_PLT64: howto manager. +* BFD_RELOC_SPARC_REGISTER: howto manager. +* BFD_RELOC_SPARC_RELATIVE: howto manager. +* BFD_RELOC_SPARC_REV32: howto manager. +* BFD_RELOC_SPARC_TLS_DTPMOD32: howto manager. +* BFD_RELOC_SPARC_TLS_DTPMOD64: howto manager. +* BFD_RELOC_SPARC_TLS_DTPOFF32: howto manager. +* BFD_RELOC_SPARC_TLS_DTPOFF64: howto manager. +* BFD_RELOC_SPARC_TLS_GD_ADD: howto manager. +* BFD_RELOC_SPARC_TLS_GD_CALL: howto manager. +* BFD_RELOC_SPARC_TLS_GD_HI22: howto manager. +* BFD_RELOC_SPARC_TLS_GD_LO10: howto manager. +* BFD_RELOC_SPARC_TLS_IE_ADD: howto manager. +* BFD_RELOC_SPARC_TLS_IE_HI22: howto manager. +* BFD_RELOC_SPARC_TLS_IE_LD: howto manager. +* BFD_RELOC_SPARC_TLS_IE_LDX: howto manager. +* BFD_RELOC_SPARC_TLS_IE_LO10: howto manager. +* BFD_RELOC_SPARC_TLS_LDM_ADD: howto manager. +* BFD_RELOC_SPARC_TLS_LDM_CALL: howto manager. +* BFD_RELOC_SPARC_TLS_LDM_HI22: howto manager. +* BFD_RELOC_SPARC_TLS_LDM_LO10: howto manager. +* BFD_RELOC_SPARC_TLS_LDO_ADD: howto manager. +* BFD_RELOC_SPARC_TLS_LDO_HIX22: howto manager. +* BFD_RELOC_SPARC_TLS_LDO_LOX10: howto manager. +* BFD_RELOC_SPARC_TLS_LE_HIX22: howto manager. +* BFD_RELOC_SPARC_TLS_LE_LOX10: howto manager. +* BFD_RELOC_SPARC_TLS_TPOFF32: howto manager. +* BFD_RELOC_SPARC_TLS_TPOFF64: howto manager. +* BFD_RELOC_SPARC_UA16: howto manager. +* BFD_RELOC_SPARC_UA32: howto manager. +* BFD_RELOC_SPARC_UA64: howto manager. +* BFD_RELOC_SPARC_WDISP16: howto manager. +* BFD_RELOC_SPARC_WDISP19: howto manager. +* BFD_RELOC_SPARC_WDISP22: howto manager. +* BFD_RELOC_SPARC_WPLT30: howto manager. +* BFD_RELOC_SPU_HI16: howto manager. +* BFD_RELOC_SPU_IMM10: howto manager. +* BFD_RELOC_SPU_IMM10W: howto manager. +* BFD_RELOC_SPU_IMM16: howto manager. +* BFD_RELOC_SPU_IMM16W: howto manager. +* BFD_RELOC_SPU_IMM18: howto manager. +* BFD_RELOC_SPU_IMM7: howto manager. +* BFD_RELOC_SPU_IMM8: howto manager. +* BFD_RELOC_SPU_LO16: howto manager. +* BFD_RELOC_SPU_PCREL16: howto manager. +* BFD_RELOC_SPU_PCREL9a: howto manager. +* BFD_RELOC_SPU_PCREL9b: howto manager. +* BFD_RELOC_THUMB_PCREL_BLX: howto manager. +* BFD_RELOC_THUMB_PCREL_BRANCH12: howto manager. +* BFD_RELOC_THUMB_PCREL_BRANCH23: howto manager. +* BFD_RELOC_THUMB_PCREL_BRANCH9: howto manager. +* BFD_RELOC_TIC30_LDP: howto manager. +* BFD_RELOC_TIC54X_16_OF_23: howto manager. +* BFD_RELOC_TIC54X_23: howto manager. +* BFD_RELOC_TIC54X_MS7_OF_23: howto manager. +* BFD_RELOC_TIC54X_PARTLS7: howto manager. +* BFD_RELOC_TIC54X_PARTMS9: howto manager. +* bfd_reloc_type_lookup: howto manager. +* BFD_RELOC_V850_22_PCREL: howto manager. +* BFD_RELOC_V850_9_PCREL: howto manager. +* BFD_RELOC_V850_ALIGN: howto manager. +* BFD_RELOC_V850_CALLT_16_16_OFFSET: howto manager. +* BFD_RELOC_V850_CALLT_6_7_OFFSET: howto manager. +* BFD_RELOC_V850_LO16_SPLIT_OFFSET: howto manager. +* BFD_RELOC_V850_LONGCALL: howto manager. +* BFD_RELOC_V850_LONGJUMP: howto manager. +* BFD_RELOC_V850_SDA_15_16_OFFSET: howto manager. +* BFD_RELOC_V850_SDA_16_16_OFFSET: howto manager. +* BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: howto manager. +* BFD_RELOC_V850_TDA_16_16_OFFSET: howto manager. +* BFD_RELOC_V850_TDA_4_4_OFFSET: howto manager. +* BFD_RELOC_V850_TDA_4_5_OFFSET: howto manager. +* BFD_RELOC_V850_TDA_6_8_OFFSET: howto manager. +* BFD_RELOC_V850_TDA_7_7_OFFSET: howto manager. +* BFD_RELOC_V850_TDA_7_8_OFFSET: howto manager. +* BFD_RELOC_V850_ZDA_15_16_OFFSET: howto manager. +* BFD_RELOC_V850_ZDA_16_16_OFFSET: howto manager. +* BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: howto manager. +* BFD_RELOC_VAX_GLOB_DAT: howto manager. +* BFD_RELOC_VAX_JMP_SLOT: howto manager. +* BFD_RELOC_VAX_RELATIVE: howto manager. +* BFD_RELOC_VPE4KMATH_DATA: howto manager. +* BFD_RELOC_VPE4KMATH_INSN: howto manager. +* BFD_RELOC_VTABLE_ENTRY: howto manager. +* BFD_RELOC_VTABLE_INHERIT: howto manager. +* BFD_RELOC_X86_64_32S: howto manager. +* BFD_RELOC_X86_64_COPY: howto manager. +* BFD_RELOC_X86_64_DTPMOD64: howto manager. +* BFD_RELOC_X86_64_DTPOFF32: howto manager. +* BFD_RELOC_X86_64_DTPOFF64: howto manager. +* BFD_RELOC_X86_64_GLOB_DAT: howto manager. +* BFD_RELOC_X86_64_GOT32: howto manager. +* BFD_RELOC_X86_64_GOTPCREL: howto manager. +* BFD_RELOC_X86_64_GOTTPOFF: howto manager. +* BFD_RELOC_X86_64_JUMP_SLOT: howto manager. +* BFD_RELOC_X86_64_PLT32: howto manager. +* BFD_RELOC_X86_64_RELATIVE: howto manager. +* BFD_RELOC_X86_64_TLSGD: howto manager. +* BFD_RELOC_X86_64_TLSLD: howto manager. +* BFD_RELOC_X86_64_TPOFF32: howto manager. +* BFD_RELOC_X86_64_TPOFF64: howto manager. +* BFD_RELOC_XSTORMY16_12: howto manager. +* BFD_RELOC_XSTORMY16_24: howto manager. +* BFD_RELOC_XSTORMY16_FPTR16: howto manager. +* BFD_RELOC_XSTORMY16_REL_12: howto manager. +* BFD_RELOC_XTENSA_ASM_EXPAND: howto manager. +* BFD_RELOC_XTENSA_ASM_SIMPLIFY: howto manager. +* BFD_RELOC_XTENSA_DIFF16: howto manager. +* BFD_RELOC_XTENSA_DIFF32: howto manager. +* BFD_RELOC_XTENSA_DIFF8: howto manager. +* BFD_RELOC_XTENSA_GLOB_DAT: howto manager. +* BFD_RELOC_XTENSA_JMP_SLOT: howto manager. +* BFD_RELOC_XTENSA_OP0: howto manager. +* BFD_RELOC_XTENSA_OP1: howto manager. +* BFD_RELOC_XTENSA_OP2: howto manager. +* BFD_RELOC_XTENSA_PLT: howto manager. +* BFD_RELOC_XTENSA_RELATIVE: howto manager. +* BFD_RELOC_XTENSA_RTLD: howto manager. +* BFD_RELOC_XTENSA_SLOT0_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT0_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT10_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT10_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT11_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT11_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT12_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT12_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT13_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT13_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT14_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT14_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT1_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT1_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT2_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT2_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT3_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT3_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT4_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT4_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT5_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT5_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT6_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT6_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT7_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT7_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT8_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT8_OP: howto manager. +* BFD_RELOC_XTENSA_SLOT9_ALT: howto manager. +* BFD_RELOC_XTENSA_SLOT9_OP: howto manager. +* bfd_scan_arch: Architectures. +* bfd_scan_vma: BFD front end. +* bfd_seach_for_target: bfd_target. +* bfd_section_already_linked: Writing the symbol table. +* bfd_section_list_clear: section prototypes. +* bfd_sections_find_if: section prototypes. +* bfd_set_arch_info: Architectures. +* bfd_set_archive_head: Archives. +* bfd_set_default_target: bfd_target. +* bfd_set_error: BFD front end. +* bfd_set_error_handler: BFD front end. +* bfd_set_error_program_name: BFD front end. +* bfd_set_file_flags: BFD front end. +* bfd_set_format: Formats. +* bfd_set_gp_size: BFD front end. +* bfd_set_private_flags: BFD front end. +* bfd_set_reloc: BFD front end. +* bfd_set_section_contents: section prototypes. +* bfd_set_section_flags: section prototypes. +* bfd_set_section_size: section prototypes. +* bfd_set_start_address: BFD front end. +* bfd_set_symtab: symbol handling functions. +* bfd_symbol_info: symbol handling functions. +* bfd_target_list: bfd_target. +* bfd_write_bigendian_4byte_int: Internal. +* bfd_zalloc: Opening and Closing. +* coff_symbol_type: coff. +* core_file_matches_executable_p: Core Files. +* find_separate_debug_file: Opening and Closing. +* get_debug_link_info: Opening and Closing. +* Hash tables: Hash Tables. +* internal object-file format: Canonical format. +* Linker: Linker Functions. +* Other functions: BFD front end. +* separate_debug_file_exists: Opening and Closing. +* struct bfd_iovec: BFD front end. +* target vector (_bfd_final_link): Performing the Final Link. +* target vector (_bfd_link_add_symbols): Adding Symbols to the Hash Table. +* target vector (_bfd_link_hash_table_create): Creating a Linker Hash Table. +* The HOWTO Macro: typedef arelent. +* what is it?: Overview. + + diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/doc/chew.c binutils/bfd/doc/chew.c --- binutils-2.16.1/bfd/doc/chew.c 2005-03-03 12:41:02.000000000 +0100 +++ binutils/bfd/doc/chew.c 2006-03-30 01:23:21.000000000 +0200 @@ -91,6 +91,12 @@ #define DEF_SIZE 5000 #define STACK 50 +#ifdef __MINGW32__ +/* Prevent \r\n\ line endings */ +#include +unsigned int _CRT_fmode = _O_BINARY; +#endif + int internal_wanted; int internal_mode; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/elf.c binutils/bfd/elf.c --- binutils-2.16.1/bfd/elf.c 2005-05-30 00:00:10.000000000 +0200 +++ binutils/bfd/elf.c 2006-03-30 01:23:21.000000000 +0200 @@ -41,6 +41,10 @@ #include "elf-bfd.h" #include "libiberty.h" +#if (defined(BPA)) +#include "elf/spu.h" +#endif + static int elf_sort_sections (const void *, const void *); static bfd_boolean assign_file_positions_except_relocs (bfd *, struct bfd_link_info *); static bfd_boolean prep_headers (bfd *); @@ -3400,6 +3404,10 @@ asection *dynsec, *eh_frame_hdr; bfd_size_type amt; +#if defined(BPA) + bfd_boolean toe_segment=FALSE; +#endif + if (elf_tdata (abfd)->segment_map != NULL) return TRUE; @@ -3511,6 +3519,19 @@ one (we build the last one after this loop). */ new_segment = FALSE; } +#if defined(BPA) + else if (strcmp (hdr->name, ".toe") == 0) + { + new_segment = TRUE; + toe_segment = TRUE; + } + else if (toe_segment == TRUE) + { + /* no longer in toe_segment */ + new_segment = TRUE; + toe_segment = FALSE; + } +#endif else if (last_hdr->lma - last_hdr->vma != hdr->lma - hdr->vma) { /* If this section has a different relation between the @@ -3964,7 +3985,11 @@ bfd_size_type align; bfd_vma adjust; - if ((abfd->flags & D_PAGED) != 0) + /* CELL LOCAL Begin */ + /* FIXME - need to double check this merge */ + if ((abfd->flags & D_PAGED) != 0 + || m == elf_tdata (abfd)->segment_map) + /* CELL LOCAL End */ align = bed->maxpagesize; else { @@ -4263,7 +4288,152 @@ p->p_flags |= PF_W; } } + +#if (defined(BPA)) + if ((bfd_get_arch(abfd) == bfd_arch_spu)) { +#define SPU_SEG_ALIGN 0x10 + if( p->p_type == PT_LOAD ) { + bfd_vma adjust_segment; + bfd_vma adjust_memsz; + /* segment file size is increased to multiple of SPU_SEG_ALIGN byte for DMA transfer. */ + adjust_segment = p->p_filesz % SPU_SEG_ALIGN ; + if ( adjust_segment != 0 ) { + p->p_filesz += (SPU_SEG_ALIGN - adjust_segment); + off += (SPU_SEG_ALIGN - adjust_segment) ; + voff += (SPU_SEG_ALIGN - adjust_segment) ; + } + /* The memory size of the segment is aligned to 16byte boundary.*/ + adjust_memsz = p->p_memsz % SPU_SEG_ALIGN ; + if ( adjust_memsz != 0) + p->p_memsz += (SPU_SEG_ALIGN - adjust_memsz); + } + } +#endif + + } + + +#if (defined(BPA)) + + /* Offset for PT_NOTE segment contains SPU_PTNOTE_SPUNAME section is set in this routine. + + In actual assign_file_positions_for_segments() doesn't gurantee to set file offset + in program header for non PT_LOAD segment. + + In detail, procedure are below. + 1) offset is set for sections in PT_LOAD segments. (in assign_file_positions_for_segments()) + 2) program headers are created and written. (in assign_file_positions_for_segments()) + 3) offset is set for sections in non PT_LOAD segments. (in assign_file_positions_except_relocs()) + + Note: + For example, file offset of PT_NOTE are set in normal system. + Because .note is contained in both PT_LOAD and PT_NOTE, + its offset are set in 1) and no problem occured. + + So this routine is added to gurantee to set offset for SPU_PTNOTE_SPUNAME only contained in PT_NOTE. + */ + + { + unsigned int i; + Elf_Internal_Shdr **hdrpp; + Elf_Internal_Shdr ** const i_shdrpp = elf_elfsections (abfd); + unsigned int num_sec = elf_numsections (abfd); + Elf_Internal_Ehdr * const i_ehdrp = elf_elfheader (abfd); + + if (bfd_get_arch(abfd) == bfd_arch_spu) { + for (i = 1, hdrpp = i_shdrpp + 1; i < num_sec; i++, hdrpp++) { + Elf_Internal_Shdr *hdr; + + hdr = *hdrpp; + if (hdr->bfd_section != NULL + && hdr->bfd_section->name != NULL + && (strcmp(hdr->bfd_section->name, SPU_PTNOTE_SPUNAME) == 0 )) { + + off = _bfd_elf_assign_file_position_for_section (hdr, off, TRUE); + + elf_tdata (abfd)->next_file_pos = off; + } + } + } + } +#endif /* BPA */ + + +/* This is for SPU dynamic loading initial step. */ +#if 0 +#if (defined(BPA)) + /* Offset for non PT_LOAD segments is set in this routine. + This added routine is exactly same in assign_file_positions_except_relocs(). + + In actual assign_file_positions_for_segments() doesn't gurantee to set file offset + in program header for non PT_LOAD segment. + + In detail, procedure are below. + 1) offset is set for sections in PT_LOAD segments. (in assign_file_positions_for_segments()) + 2) program headers are created and written. (in assign_file_positions_for_segments()) + 3) offset is set for sections in non PT_LOAD segments. (in assign_file_positions_except_relocs()) + + So this routine is added to gurantee to set offset for not PT_LOAD segments. + + Note: + For example, file offset of PT_DYNAMIC are set in normal system. + Because .dynamic are contained in both PT_LOAD and PT_DYNAMIC. + So its offset are set in 1) and no problem occured. */ + + { + unsigned int i; + Elf_Internal_Shdr **hdrpp; + Elf_Internal_Shdr ** const i_shdrpp = elf_elfsections (abfd); + unsigned int num_sec = elf_numsections (abfd); + struct elf_obj_tdata * const tdata = elf_tdata (abfd); + Elf_Internal_Ehdr * const i_ehdrp = elf_elfheader (abfd); + + if ((bfd_get_arch(abfd) == bfd_arch_spu) && (i_ehdrp->e_type == ET_DYN)) { + /* Assign file positions for the other sections. */ + + for (i = 1, hdrpp = i_shdrpp + 1; i < num_sec; i++, hdrpp++) + { + Elf_Internal_Shdr *hdr; + + hdr = *hdrpp; + if (hdr->bfd_section != NULL + && hdr->bfd_section->filepos != 0) + hdr->sh_offset = hdr->bfd_section->filepos; + else if ((hdr->sh_flags & SHF_ALLOC) != 0) + { + ((*_bfd_error_handler) + (_("%s: warning: allocated section `%s' not in segment"), + bfd_get_filename (abfd), + (hdr->bfd_section == NULL + ? "*unknown*" + : hdr->bfd_section->name))); + if ((abfd->flags & D_PAGED) != 0) + off += (hdr->sh_addr - off) % bed->maxpagesize; + else + off += (hdr->sh_addr - off) % hdr->sh_addralign; + off = _bfd_elf_assign_file_position_for_section (hdr, off, + false); + } + else if (hdr->sh_type == SHT_REL + || hdr->sh_type == SHT_RELA + || hdr == i_shdrpp[tdata->symtab_section] + || hdr == i_shdrpp[tdata->symtab_shndx_section] + || hdr == i_shdrpp[tdata->strtab_section]) + hdr->sh_offset = -1; + else + off = _bfd_elf_assign_file_position_for_section (hdr, off, TRUE); + + if (i == SHN_LORESERVE - 1) + { + i += SHN_HIRESERVE + 1 - SHN_LORESERVE; + hdrpp += SHN_HIRESERVE + 1 - SHN_LORESERVE; + } + } + } + elf_tdata (abfd)->next_file_pos = off; } +#endif +#endif /* Now that we have set the section file positions, we can set up the file positions for the non PT_LOAD segments. */ diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/elf32-spu.c binutils/bfd/elf32-spu.c --- binutils-2.16.1/bfd/elf32-spu.c 1970-01-01 01:00:00.000000000 +0100 +++ binutils/bfd/elf32-spu.c 2006-03-30 01:23:21.000000000 +0200 @@ -0,0 +1,1015 @@ +/* SPU specific support for 32-bit ELF */ + +/* (C) Copyright + Sony Computer Entertainment, Inc., + Toshiba Corporation, + International Business Machines Corporation, + 2001,2002,2003,2004,2005. + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "bfdlink.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/spu.h" + +void spu_elf_info_to_howto PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); +void spu_elf_info_to_howto_rel PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); +reloc_howto_type *spu_elf_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type)); +static void spu_elf_final_write_processing PARAMS ((bfd *, bfd_boolean)); +static bfd_boolean spu_elf_relocate_section PARAMS ((bfd *, struct bfd_link_info *, bfd *, + asection *, bfd_byte *, Elf_Internal_Rela *, + Elf_Internal_Sym *, asection **)); +static asection * spu_elf_gc_mark_hook PARAMS ((asection *, struct bfd_link_info *, + Elf_Internal_Rela *, struct elf_link_hash_entry *, + Elf_Internal_Sym *)); +static bfd_boolean spu_elf_gc_sweep_hook PARAMS ((bfd *, struct bfd_link_info *, asection *, + const Elf_Internal_Rela *)); + +#if defined(BPA) +static void spu_elf_post_process_headers PARAMS ((bfd *, struct bfd_link_info *)); +static bfd_boolean spu_elf_section_processing PARAMS ((bfd *, Elf_Internal_Shdr *)); +static bfd_boolean spu_elf_always_size_sections PARAMS ((bfd *, struct bfd_link_info *)); +#endif + +/* When USE_REL is not defined bfd uses reloc entry addends + * instead of inserting the addend into the instruction. + * #define USE_REL 0 + */ + + +/* Values of type 'enum elf_spu_reloc_type' are used to index this + * array, so it must be declared in the order of that type. */ +static reloc_howto_type elf_howto_table[] = { + HOWTO(R_SPU_NONE, 0, 0, 0, FALSE, 0, complain_overflow_dont, bfd_elf_generic_reloc, "SPU_NONE", FALSE, 0x00000000, 0x00000000, FALSE), + HOWTO(R_SPU_ADDR10, 4, 2,10, FALSE, 14, complain_overflow_bitfield, bfd_elf_generic_reloc, "SPU_ADDR10", FALSE, 0x00ffc000, 0x00ffc000, FALSE), + HOWTO(R_SPU_ADDR16, 2, 2,16, FALSE, 7, complain_overflow_bitfield, bfd_elf_generic_reloc, "SPU_ADDR16", FALSE, 0x007fff80, 0x007fff80, FALSE), + HOWTO(R_SPU_ADDR16_HI,16,2,16, FALSE, 7, complain_overflow_bitfield, bfd_elf_generic_reloc, "SPU_ADDR16_HI", FALSE, 0x007fff80, 0x007fff80, FALSE), + HOWTO(R_SPU_ADDR16_LO,0, 2,16, FALSE, 7, complain_overflow_dont, bfd_elf_generic_reloc, "SPU_ADDR16_LO", FALSE, 0x007fff80, 0x007fff80, FALSE), + HOWTO(R_SPU_ADDR18, 0, 2,18, FALSE, 7, complain_overflow_bitfield, bfd_elf_generic_reloc, "SPU_ADDR18", FALSE, 0x01ffff80, 0x01ffff80, FALSE), + HOWTO(R_SPU_GLOB_DAT, 0, 2,32, FALSE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "SPU_GLOB_DAT", FALSE, 0xffffffff, 0xffffffff, FALSE), + HOWTO(R_SPU_REL16, 2, 2,16, TRUE, 7, complain_overflow_bitfield, bfd_elf_generic_reloc, "SPU_REL16", FALSE, 0x007fff80, 0x007fff80, TRUE), + HOWTO(R_SPU_ADDR7, 0, 2, 7, FALSE, 14, complain_overflow_dont, bfd_elf_generic_reloc, "SPU_ADDR7", FALSE, 0x001fc000, 0x001fc000, FALSE), + HOWTO(R_SPU_REL9, 2, 2, 9, TRUE, 0, complain_overflow_signed, bfd_elf_generic_reloc, "SPU_REL9", FALSE, 0x0180007f, 0x0180007f, TRUE), + HOWTO(R_SPU_REL9I, 2, 2, 9, TRUE, 0, complain_overflow_signed, bfd_elf_generic_reloc, "SPU_REL9I", FALSE, 0x0000c07f, 0x0000c07f, TRUE), + HOWTO(R_SPU_ADDR10I, 0, 2,10, FALSE, 14, complain_overflow_signed, bfd_elf_generic_reloc, "SPU_ADDR10I", FALSE, 0x00ffc000, 0x00ffc000, FALSE), + HOWTO(R_SPU_ADDR16I, 0, 2,16, FALSE, 7, complain_overflow_signed, bfd_elf_generic_reloc, "SPU_ADDR16I", FALSE, 0x007fff80, 0x007fff80, FALSE), +}; + +static struct bfd_elf_special_section const spu_elf_special_sections[]= +{ + { ".toe", 4, 0, SHT_PROGBITS, SHF_ALLOC }, + { NULL, 0, 0, 0, 0 } +}; + +static enum elf_spu_reloc_type +spu_elf_bfd_to_reloc_type (bfd_reloc_code_real_type code) +{ + switch (code) + { + default: + return R_SPU_NONE; + case BFD_RELOC_SPU_IMM10W: + return R_SPU_ADDR10; + case BFD_RELOC_SPU_IMM16W: + return R_SPU_ADDR16; + case BFD_RELOC_SPU_LO16: + return R_SPU_ADDR16_LO; + case BFD_RELOC_SPU_HI16: + return R_SPU_ADDR16_HI; + case BFD_RELOC_SPU_IMM18: + return R_SPU_ADDR18; + case BFD_RELOC_32: + return R_SPU_GLOB_DAT; + case BFD_RELOC_SPU_PCREL16: + return R_SPU_REL16; + case BFD_RELOC_SPU_IMM7: + return R_SPU_ADDR7; + case BFD_RELOC_SPU_IMM8: + return R_SPU_NONE; + case BFD_RELOC_SPU_PCREL9a: + return R_SPU_REL9; + case BFD_RELOC_SPU_PCREL9b: + return R_SPU_REL9I; + case BFD_RELOC_SPU_IMM10: + return R_SPU_ADDR10I; + case BFD_RELOC_SPU_IMM16: + return R_SPU_ADDR16I; + } +} + +void +spu_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr ATTRIBUTE_UNUSED, + Elf_Internal_Rela * dst ATTRIBUTE_UNUSED) +{ + enum elf_spu_reloc_type r_type; + + r_type = (enum elf_spu_reloc_type) ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < R_SPU_max); + cache_ptr->howto = &elf_howto_table[(int) r_type]; +} + +void +spu_elf_info_to_howto_rel (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, Elf_Internal_Rela * dst) +{ + enum elf_spu_reloc_type type; + + type = (enum elf_spu_reloc_type) ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (type < R_SPU_max); + cache_ptr->howto = &elf_howto_table[(int) type]; +} + +reloc_howto_type * +spu_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + return elf_howto_table + spu_elf_bfd_to_reloc_type (code); +} + +/* Look through the relocs for a section during the first phase and + make any required dynamic sections. + + We iterate over the relocations three times: + + spu_elf_check_relocs + This creates any needed dynamic sections as we first read all the + input objects. We need to do create the sections now so they get + mapped to the correct output sections. At this points we don't + know which symbols are resolved from dynamic objects. + + allocate_dynrelocs + This computes sizes of the sections. Now we do know which + symbols come from where, so we can determine the correct amount + of space to allocate. Some sections will require no space and + are stripped by spu_elf_size_dynamic_sections. + + spu_elf_relocate_section + This finally creates the relocations in the correct section. + */ +static bfd_boolean +spu_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, + asection *sec, const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + asection *sreloc; + bfd *dynobj; + + if (info->relocatable) + return TRUE; + + /* Don't do anything special with non-loaded, non-alloced sections. + In particular, there's not much point in propagating relocs to + shared libs that the dynamic linker won't relocate. */ + if ((sec->flags & SEC_ALLOC) == 0) + return TRUE; + + dynobj = elf_hash_table (info)->dynobj; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = (sym_hashes + + symtab_hdr->sh_size / sizeof (Elf32_External_Sym) + - symtab_hdr->sh_info); + + sreloc = NULL; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + unsigned long r_symndx; + struct elf_link_hash_entry *h; + enum elf_spu_reloc_type r_type; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + r_type = ELF32_R_TYPE (rel->r_info); + switch (r_type) + { + case R_SPU_ADDR10: + case R_SPU_ADDR16: + case R_SPU_ADDR16_HI: + case R_SPU_ADDR16_LO: + case R_SPU_ADDR18: + case R_SPU_GLOB_DAT: + case R_SPU_REL16: + case R_SPU_ADDR7: + case R_SPU_ADDR10I: + case R_SPU_ADDR16I: + if (h != NULL + && (!h->def_regular + || h->root.type == bfd_link_hash_defweak + || (info->shared && ! info->symbolic))) + { + /* We might need to copy these reloc types into the output file. + Create a reloc section in dynobj. */ + if (sreloc == NULL) + { + const char *name; + + name = (bfd_elf_string_from_elf_section + (abfd, + elf_elfheader (abfd)->e_shstrndx, + elf_section_data (sec)->rel_hdr.sh_name)); + if (name == NULL) + return FALSE; + + if (strncmp (name, ".rela", 5) != 0 + || strcmp (bfd_get_section_name (abfd, sec), + name + 5) != 0) + { + (*_bfd_error_handler) + (_("%B: bad relocation section name `%s\'"), + abfd, name); + bfd_set_error (bfd_error_bad_value); + } + + if (dynobj == NULL) + dynobj = elf_hash_table (info)->dynobj = abfd; + + sreloc = bfd_get_section_by_name (dynobj, name); + if (sreloc == NULL) + { + flagword flags; + + sreloc = bfd_make_section (dynobj, name); + flags = (SEC_HAS_CONTENTS | SEC_READONLY + | SEC_IN_MEMORY | SEC_LINKER_CREATED); + if ((sec->flags & SEC_ALLOC) != 0) + flags |= SEC_ALLOC | SEC_LOAD; + if (sreloc == NULL + || ! bfd_set_section_flags (dynobj, sreloc, flags) + || ! bfd_set_section_alignment (dynobj, sreloc, 3)) + return FALSE; + } + elf_section_data (sec)->sreloc = sreloc; + } + } + break; + + default: + break; + } + } + return TRUE; +} + + +static bfd_boolean +spu_elf_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + Elf_Internal_Rela *rel, *relend; + bfd_boolean ret = TRUE; + + if (info->relocatable) + return TRUE; + + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = (struct elf_link_hash_entry **) (elf_sym_hashes (input_bfd)); + + rel = relocs; + relend = relocs + input_section->reloc_count; + for (; rel < relend; rel++) + { + int r_type; + reloc_howto_type *howto; + unsigned long r_symndx; + Elf_Internal_Sym *sym; + asection *sec; + struct elf_link_hash_entry *h; + const char *sym_name; + bfd_vma relocation; + bfd_reloc_status_type r; + bfd_boolean unresolved_reloc; + bfd_boolean warned; + + r_symndx = ELF32_R_SYM (rel->r_info); + r_type = ELF32_R_TYPE (rel->r_info); + howto = elf_howto_table + r_type; + unresolved_reloc = FALSE; + warned = FALSE; + + h = NULL; + sym = NULL; + sec = NULL; + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + sym_name = bfd_elf_sym_name (input_bfd, symtab_hdr, sym); + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + } + else + { + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned); + sym_name = h->root.root.string; + } + + switch (r_type) + { + /* Relocations that always need to be propagated if this is a shared + object. */ + case R_SPU_ADDR10: + case R_SPU_ADDR16: + case R_SPU_ADDR16_HI: + case R_SPU_ADDR16_LO: + case R_SPU_ADDR18: + case R_SPU_GLOB_DAT: + case R_SPU_REL16: + case R_SPU_ADDR7: + case R_SPU_ADDR10I: + case R_SPU_ADDR16I: + /* r_symndx will be zero only for relocs against symbols + from removed linkonce sections, or sections discarded by + a linker script. */ + if (r_symndx == 0) + break; + /* Fall thru. */ + + if ((info->shared + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak) + && (!SYMBOL_CALLS_LOCAL (info, h))) + || (!info->shared + && h != NULL + && h->dynindx != -1 + && h->def_dynamic + && !h->def_regular)) + { + Elf_Internal_Rela outrel; + bfd_boolean skip, relocate; + asection *sreloc; + bfd_byte *loc; + bfd_vma out_off; + + /* When generating a dynamic object, these relocations + are copied into the output file to be resolved at run + time. */ + + skip = FALSE; + relocate = FALSE; + + out_off = _bfd_elf_section_offset (output_bfd, info, + input_section, rel->r_offset); + if (out_off == (bfd_vma) -1) + skip = TRUE; + else if (out_off == (bfd_vma) -2) + skip = TRUE, relocate = TRUE; + out_off += (input_section->output_section->vma + + input_section->output_offset); + outrel.r_offset = out_off; + outrel.r_addend = rel->r_addend; + + if (skip) + memset (&outrel, 0, sizeof outrel); + else if (!SYMBOL_REFERENCES_LOCAL (info, h)) + outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); + else + { + /* This symbol is local, or marked to become local. */ + outrel.r_addend += relocation; + if (r_type == R_SPU_GLOB_DAT) + { + outrel.r_info = ELF32_R_INFO (0, R_SPU_GLOB_DAT); + + /* Prelink also wants simple and consistent rules + for relocs. This make all RELATIVE relocs have + *r_offset equal to r_addend. */ + relocate = TRUE; + } + else + { + long indx = 0; + + if (bfd_is_abs_section (sec)) + ; + else if (sec == NULL || sec->owner == NULL) + { + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + else + { + asection *osec; + + osec = sec->output_section; + indx = elf_section_data (osec)->dynindx; + + /* We are turning this relocation into one + against a section symbol, so subtract out + the output section's address but not the + offset of the input section in the output + section. */ + outrel.r_addend -= osec->vma; + } + + outrel.r_info = ELF32_R_INFO (indx, r_type); + } + } + + sreloc = elf_section_data (input_section)->sreloc; + if (sreloc == NULL) + abort (); + + loc = sreloc->contents; + loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + + /* If this reloc is against an external symbol, it will + be computed at runtime, so there's no need to do + anything now. However, for the sake of prelink ensure + that the section contents are a known value. */ + if (! relocate) + { + unresolved_reloc = FALSE; + /* The value chosen here is quite arbitrary as ld.so + ignores section contents except for the special + case of .opd where the contents might be accessed + before relocation. Choose zero, as that won't + cause reloc overflow. */ + relocation = 0; + rel->r_addend = 0; + /* Adjust pc_relative relocs to have zero in *r_offset. */ + if (howto->pc_relative) + rel->r_addend = (input_section->output_section->vma + + input_section->output_offset + + rel->r_offset); + } + } + break; + } + + if (unresolved_reloc + && !((input_section->flags & SEC_DEBUGGING) != 0 + && h->def_dynamic)) + { + (*_bfd_error_handler) + (_("%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'"), + input_bfd, + bfd_get_section_name (input_bfd, input_section), + (long) rel->r_offset, + howto->name, + sym_name); + ret = FALSE; + } + + r = _bfd_final_link_relocate (howto, + input_bfd, + input_section, + contents, + rel->r_offset, relocation, rel->r_addend); + + if (r != bfd_reloc_ok) + { + const char *name; + const char *msg = (const char *) 0; + + if (h != NULL) + name = h->root.root.string; + else + { + name = (bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name)); + if (name == NULL || *name == '\0') + name = bfd_section_name (input_bfd, sec); + } + + switch (r) + { + case bfd_reloc_overflow: + if (!((*info->callbacks->reloc_overflow) + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma) 0, input_bfd, input_section, rel->r_offset))) + return FALSE; + break; + + case bfd_reloc_undefined: + if (!((*info->callbacks->undefined_symbol) + (info, name, input_bfd, input_section, + rel->r_offset, TRUE))) + return FALSE; + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + goto common_error; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + goto common_error; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous error"); + goto common_error; + + default: + msg = _("internal error: unknown error"); + /* fall through */ + + common_error: + if (!((*info->callbacks->warning) + (info, msg, name, input_bfd, input_section, + rel->r_offset))) + return FALSE; + break; + } + } + } + + return ret; +} + +static asection * +spu_elf_gc_mark_hook (asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel ATTRIBUTE_UNUSED, struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + if (h != NULL) + { + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + else + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + return NULL; +} + +static bfd_boolean +spu_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec ATTRIBUTE_UNUSED, const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) +{ + return TRUE; +} + +static void +spu_elf_final_write_processing (bfd * abfd, + bfd_boolean linker ATTRIBUTE_UNUSED) +{ + elf_elfheader (abfd)->e_machine = EM_SPU; + + /* We do these verifications here because this function is called only + * once. There may be a better place to do it, I didn't look. */ + + BFD_ASSERT (elf_elfheader (abfd)->e_ident[EI_CLASS] == ELFCLASS32); + BFD_ASSERT (elf_elfheader (abfd)->e_ident[EI_DATA] == ELFDATA2MSB); + BFD_ASSERT (elf_elfheader (abfd)->e_flags == 0); + + /* Verify that elf_howto_table is in the correct order. */ + { + unsigned int i; + for (i = 0; i < sizeof (elf_howto_table) / sizeof (*elf_howto_table); i++) + { + BFD_ASSERT (elf_howto_table[i].type == i); + } + } +} + + +#if defined(BPA) +static void +spu_elf_post_process_headers (bfd * abfd, struct bfd_link_info *link_info) +{ + Elf_Internal_Ehdr *i_ehdrp; /* Elf file header, internal form */ + + /* e_type is set if -plugin assigned. */ + + i_ehdrp = elf_elfheader (abfd); + + if (link_info != NULL) + { + if (link_info->spuplugin) + { + i_ehdrp->e_type = ET_DYN; + } + } +} + +#endif + +#if defined(BPA) +static bfd_boolean +spu_elf_section_processing (bfd * abfd ATTRIBUTE_UNUSED, + Elf_Internal_Shdr * i_shdrp) +{ + /* Content of PT_NOTE segment for SPU plugin is set here. + Because it doesn't have SEC_ALLOC attribute, + it is not written in file as usual process. + + If this routine is not used, some special writing process has to be done somewhere. + (e.g., special function would be needed as string table writing process.) */ + + asection *sec; + + sec = i_shdrp->bfd_section; + if ((sec != NULL) && + (sec->name != NULL) && (strcmp (sec->name, SPU_PTNOTE_SPUNAME) == 0)) + { + + SPUPLUGIN_INFO *spuplugin_info; + spuplugin_info = bfd_alloc (abfd, sizeof (SPUPLUGIN_INFO)); + + bfd_put_32(abfd, (bfd_vma) SPU_PLUGIN_NAMESZ, &spuplugin_info->namesz) ; + bfd_put_32(abfd, (bfd_vma) SPU_PLUGIN_LOOKUPNAMESZ, &spuplugin_info->descsz) ; + bfd_put_32(abfd, (bfd_vma) 1, &spuplugin_info->type) ; + strncpy( spuplugin_info->name, SPU_PLUGIN_NAME, SPU_PLUGIN_NAMESZ); + strncpy( spuplugin_info->lookupname, bfd_get_filename(abfd), SPU_PLUGIN_LOOKUPNAMESZ); + + i_shdrp->contents = (unsigned char*)spuplugin_info ; + } + return TRUE; +} +#endif + +#if defined(BPA) +/* + * Make SPU_PTNOTE_SPUNAME section + * */ +static bfd_boolean +spu_elf_always_size_sections (bfd * abfd, struct bfd_link_info *link_info ATTRIBUTE_UNUSED) +{ + + register asection *s; + char *sname = SPU_PTNOTE_SPUNAME; + + s = bfd_get_section_by_name(abfd, sname); + /* don't create the section if already exists */ + if (s == NULL) { + s = bfd_make_section (abfd, sname); + if (s == NULL) { + return FALSE; + } + } + + if (!bfd_set_section_flags + (abfd, s, + (SEC_LOAD | SEC_IN_MEMORY | SEC_HAS_CONTENTS | SEC_LINKER_CREATED | + SEC_READONLY))) { + return FALSE; + } + + if (!bfd_set_section_alignment (abfd, s, 2)) { + return FALSE; + } + + if (!bfd_set_section_size (abfd, s, sizeof (SPUPLUGIN_INFO))) { + return FALSE; + } + + return TRUE; +} +#endif + +static bfd_boolean +spu_elf_finish_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED) +{ + return TRUE; +} +static bfd_boolean +spu_elf_finish_dynamic_symbol (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + struct elf_link_hash_entry *h ATTRIBUTE_UNUSED, + Elf_Internal_Sym *sym ATTRIBUTE_UNUSED) +{ + return TRUE; +} + +/* compute the sizes of the required dynamic relocatios */ +static bfd_boolean +allocate_dynrelocs (bfd *abfd, struct bfd_link_info *info, + asection *sec, const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + asection *sreloc; + bfd *dynobj; + + if (info->relocatable) + return TRUE; + + /* Don't do anything special with non-loaded, non-alloced sections. + In particular, there's not much point in propagating relocs to + shared libs that the dynamic linker won't relocate. */ + if ((sec->flags & SEC_ALLOC) == 0) + return TRUE; + + /* spu_elf_check_relocs will have set sreloc for the sections we + need to check. */ + sreloc = elf_section_data (sec)->sreloc; + if (sreloc == NULL) + return TRUE; + + dynobj = elf_hash_table (info)->dynobj; + if (dynobj == NULL) + abort(); + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = (sym_hashes + + symtab_hdr->sh_size / sizeof (Elf32_External_Sym) + - symtab_hdr->sh_info); + + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + unsigned long r_symndx; + struct elf_link_hash_entry *h; + enum elf_spu_reloc_type r_type; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + r_type = ELF32_R_TYPE (rel->r_info); + switch (r_type) + { + case R_SPU_ADDR10: + case R_SPU_ADDR16: + case R_SPU_ADDR16_HI: + case R_SPU_ADDR16_LO: + case R_SPU_ADDR18: + case R_SPU_GLOB_DAT: + case R_SPU_REL16: + case R_SPU_ADDR7: + case R_SPU_ADDR10I: + case R_SPU_ADDR16I: + if ((info->shared + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak) + && (!SYMBOL_CALLS_LOCAL (info, h))) + || (!info->shared + && h != NULL + && h->dynindx != -1 + && h->def_dynamic + && !h->def_regular)) + { + /* We must copy these reloc types into the output file. + Increase the size of the reloc section. */ + sreloc->rawsize += sizeof (Elf32_External_Rela); + } + break; + + default: + break; + } + } + return TRUE; +} + +/* Set the sizes of the dynamic sections. */ + +static bfd_boolean +spu_elf_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED, struct bfd_link_info * info) +{ + bfd * dynobj; + asection * s; + bfd_boolean relocs; + bfd_boolean reltext; + asection *o; + bfd *inputobj; + + /* Check all the relocations of all input objects to determine + the size of dynamic sections. */ + for (inputobj = info->input_bfds; + inputobj; + inputobj = inputobj->link_next) + { + for (o = inputobj->sections; o != NULL; o = o->next) + { + Elf_Internal_Rela *internal_relocs; + bfd_boolean ok; + + if ((o->flags & SEC_RELOC) == 0 + || o->reloc_count == 0 + || ((info->strip == strip_all || info->strip == strip_debugger) + && (o->flags & SEC_DEBUGGING) != 0) + || bfd_is_abs_section (o->output_section)) + continue; + + internal_relocs = _bfd_elf_link_read_relocs (inputobj, o, NULL, NULL, + info->keep_memory); + if (internal_relocs == NULL) + return FALSE; + + ok = allocate_dynrelocs (inputobj, info, o, internal_relocs); + + if (elf_section_data (o)->relocs != internal_relocs) + free (internal_relocs); + + if (! ok) + return FALSE; + } + } + + dynobj = elf_hash_table (info)->dynobj; + BFD_ASSERT (dynobj != NULL); + + /* The code above has determined the sizes of the various dynamic + sections. Allocate memory for them. */ + relocs = FALSE; + reltext = FALSE; + for (s = dynobj->sections; s != NULL; s = s->next) + { + const char * name; + bfd_boolean strip; + + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + if (s->contents != NULL) + continue; + + /* It's OK to base decisions on the section name, because none + of the dynobj section names depend upon the input files. */ + name = bfd_get_section_name (dynobj, s); + + strip = FALSE; + + if (strncmp (name, ".rela", 5) == 0) + { + if (s->rawsize == 0) + { + /* If we don't need this section, strip it from the output + file. */ + strip = TRUE; + } + else + { + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; + } + } + else + /* It's not one of our sections, so don't allocate space. */ + continue; + + if (strip) + { + _bfd_strip_section_from_output (info, s); + continue; + } + + /* Allocate memory for the section contents. We use bfd_zalloc + here in case unused entries are not reclaimed before the + section's contents are written out. This should not happen, + but this way if it does, we get a R_SPU_NONE reloc instead of + garbage. */ + s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->rawsize); + if (s->contents == NULL && s->rawsize != 0) + return FALSE; + } + + return TRUE; +} + +/* Create dynamic sections when linking against a dynamic object. */ + +static bfd_boolean +spu_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) +{ + flagword flags; + asection *s; + const struct elf_backend_data *bed = get_elf_backend_data (abfd); + + /* We need to create .dynbss, and .rel[a].bss sections. */ + + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED); + + if (bed->want_dynbss) + { + /* The .dynbss section is a place to put symbols which are defined + by dynamic objects, are referenced by regular objects, and are + not functions. We must allocate space for them in the process + image and use a R_*_COPY reloc to tell the dynamic linker to + initialize them at run time. The linker script puts the .dynbss + section into the .bss section of the final image. */ + s = bfd_make_section (abfd, ".dynbss"); + if (s == NULL + || ! bfd_set_section_flags (abfd, s, SEC_ALLOC | SEC_LINKER_CREATED)) + return FALSE; + + /* The .rel[a].bss section holds copy relocs. This section is not + normally needed. We need to create it here, though, so that the + linker will map it to an output section. We can't just create it + only if we need it, because we will not know whether we need it + until we have seen all the input files, and the first time the + main linker code calls BFD after examining all the input files + (size_dynamic_sections) the input sections have already been + mapped to the output sections. If the section turns out not to + be needed, we can discard it later. We will never need this + section when generating a shared object, since they do not use + copy relocs. */ + if (! info->shared) + { + s = bfd_make_section (abfd, + (bed->default_use_rela_p + ? ".rela.bss" : ".rel.bss")); + if (s == NULL + || ! bfd_set_section_flags (abfd, s, flags | SEC_READONLY) + || ! bfd_set_section_alignment (abfd, s, bed->s->log_file_align)) + return FALSE; + } + } + + return TRUE; +} + +static bfd_boolean +spu_elf_adjust_dynamic_symbol (struct bfd_link_info *info ATTRIBUTE_UNUSED, + struct elf_link_hash_entry *h ATTRIBUTE_UNUSED) +{ + return TRUE; +} + + +#define elf_backend_can_gc_sections 1 +#define elf_backend_rela_normal 1 + + +#define bfd_elf32_bfd_reloc_type_lookup spu_elf_reloc_type_lookup +#define elf_info_to_howto spu_elf_info_to_howto +#define elf_info_to_howto_rel spu_elf_info_to_howto_rel +#define elf_backend_relocate_section spu_elf_relocate_section +#define elf_backend_final_write_processing spu_elf_final_write_processing +#define elf_backend_gc_mark_hook spu_elf_gc_mark_hook +#define elf_backend_gc_sweep_hook spu_elf_gc_sweep_hook +#define elf_backend_adjust_dynamic_symbol spu_elf_adjust_dynamic_symbol +#define elf_backend_check_relocs spu_elf_check_relocs + +#define elf_backend_create_dynamic_sections spu_elf_create_dynamic_sections +#define elf_backend_finish_dynamic_sections spu_elf_finish_dynamic_sections +#define elf_backend_finish_dynamic_symbol spu_elf_finish_dynamic_symbol +#define elf_backend_size_dynamic_sections spu_elf_size_dynamic_sections + +#define TARGET_BIG_SYM bfd_elf32_spu_vec +#define TARGET_BIG_NAME "elf32-spu" +#define ELF_ARCH bfd_arch_spu +#define ELF_MACHINE_CODE EM_SPU +#define ELF_MAXPAGESIZE 0x80 /* This matches the alignment need for DMA. */ + +#if defined(BPA) +#define elf_backend_post_process_headers spu_elf_post_process_headers +#define elf_backend_section_processing spu_elf_section_processing +#define elf_backend_always_size_sections spu_elf_always_size_sections +#define elf_backend_special_sections spu_elf_special_sections +#endif + +#include "elf32-target.h" diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/elf64-ppc.c binutils/bfd/elf64-ppc.c --- binutils-2.16.1/bfd/elf64-ppc.c 2005-06-12 19:37:59.000000000 +0200 +++ binutils/bfd/elf64-ppc.c 2006-03-30 01:23:21.000000000 +0200 @@ -3967,7 +3967,8 @@ newsym->value = 0; newsym->flags = BSF_WEAK; - bh = NULL; + /* We don't want to search the "wrap" hash table */ + bh = bfd_link_hash_lookup (info->hash, newsym->name, TRUE, FALSE, FALSE); if (!_bfd_generic_link_add_one_symbol (info, abfd, newsym->name, newsym->flags, newsym->section, newsym->value, NULL, FALSE, FALSE, @@ -8985,6 +8986,8 @@ if (stub_type != ppc_stub_plt_call) { + /* CELL Local: Fix for lib00001372 in 2.15, not sure + if it is necessary in 2.16.1, but leaving it in. */ /* Check whether we need a TOC adjusting stub. Since the linker pastes together pieces from different object files when creating the diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/elflink.c binutils/bfd/elflink.c --- binutils-2.16.1/bfd/elflink.c 2005-04-29 15:40:22.000000000 +0200 +++ binutils/bfd/elflink.c 2006-03-30 01:23:21.000000000 +0200 @@ -909,6 +909,11 @@ else olddef = TRUE; + /* CELL LOCAL BEGIN changes */ +#if 0 + To be compatible with TLS references generated by binutils 2.15, we + disable this check. + /* Check TLS symbol. */ if ((ELF_ST_TYPE (sym->st_info) == STT_TLS || h->type == STT_TLS) && ELF_ST_TYPE (sym->st_info) != h->type) @@ -956,6 +961,8 @@ bfd_set_error (bfd_error_bad_value); return FALSE; } +#endif + /* CELL LOCAL END changes */ /* We need to remember if a symbol has a definition in a dynamic object or is weak in all dynamic objects. Internal and hidden diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/opncls.c binutils/bfd/opncls.c --- binutils-2.16.1/bfd/opncls.c 2005-03-07 11:32:38.000000000 +0100 +++ binutils/bfd/opncls.c 2006-03-30 01:23:21.000000000 +0200 @@ -1357,3 +1357,18 @@ return TRUE; } + +/* + * Added at SCEA - set direction. Needed to compensate for WIN32 + * lack of fcntl + */ +void +bfd_set_direction(bfd *abfd, int fdflags) +{ + switch (fdflags & (O_ACCMODE)) { + case O_RDONLY: abfd->direction = read_direction; break; + case O_WRONLY: abfd->direction = write_direction; break; + case O_RDWR: abfd->direction = both_direction; break; + default: abort (); + } +} diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/reloc.c binutils/bfd/reloc.c --- binutils-2.16.1/bfd/reloc.c 2005-03-02 22:23:21.000000000 +0100 +++ binutils/bfd/reloc.c 2006-03-30 01:23:21.000000000 +0200 @@ -4159,6 +4159,33 @@ Intel i860 Relocations. ENUM + BFD_RELOC_SPU_IMM7 +ENUMX + BFD_RELOC_SPU_IMM8 +ENUMX + BFD_RELOC_SPU_IMM10 +ENUMX + BFD_RELOC_SPU_IMM10W +ENUMX + BFD_RELOC_SPU_IMM16 +ENUMX + BFD_RELOC_SPU_IMM16W +ENUMX + BFD_RELOC_SPU_IMM18 +ENUMX + BFD_RELOC_SPU_PCREL9a +ENUMX + BFD_RELOC_SPU_PCREL9b +ENUMX + BFD_RELOC_SPU_PCREL16 +ENUMX + BFD_RELOC_SPU_LO16 +ENUMX + BFD_RELOC_SPU_HI16 +ENUMDOC + SPU Relocations. + +ENUM BFD_RELOC_OPENRISC_ABS_26 ENUMX BFD_RELOC_OPENRISC_REL_26 diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/bfd/targets.c binutils/bfd/targets.c --- binutils-2.16.1/bfd/targets.c 2005-03-01 02:56:27.000000000 +0100 +++ binutils/bfd/targets.c 2006-03-30 01:23:21.000000000 +0200 @@ -613,6 +613,7 @@ extern const bfd_target bfd_elf32_shlnbsd_vec; extern const bfd_target bfd_elf32_shnbsd_vec; extern const bfd_target bfd_elf32_sparc_vec; +extern const bfd_target bfd_elf32_spu_vec; extern const bfd_target bfd_elf32_tradbigmips_vec; extern const bfd_target bfd_elf32_tradlittlemips_vec; extern const bfd_target bfd_elf32_us_cris_vec; @@ -918,6 +919,7 @@ &bfd_elf32_sh64blin_vec, #endif &bfd_elf32_sparc_vec, + &bfd_elf32_spu_vec, &bfd_elf32_tradbigmips_vec, &bfd_elf32_tradlittlemips_vec, &bfd_elf32_us_cris_vec, diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/binutils/ar.c binutils/binutils/ar.c --- binutils-2.16.1/binutils/ar.c 2005-03-03 12:46:12.000000000 +0100 +++ binutils/binutils/ar.c 2006-03-30 01:23:21.000000000 +0200 @@ -362,6 +362,15 @@ program_name = argv[0]; xmalloc_set_program_name (program_name); + { + const char *response_file = expandargv (&argc, &argv); + if (response_file) + { + fatal (_("cannot file response file. --- %s"), response_file); + xexit (1); + } + } + if (is_ranlib < 0) { char *temp; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/binutils/doc/objcopy.1 binutils/binutils/doc/objcopy.1 --- binutils-2.16.1/binutils/doc/objcopy.1 2005-04-20 20:49:51.000000000 +0200 +++ binutils/binutils/doc/objcopy.1 2006-03-30 01:23:21.000000000 +0200 @@ -164,6 +164,8 @@ [\fB\-\-change\-section\-vma\fR \fIsection\fR{=,+,\-}\fIval\fR] [\fB\-\-change\-warnings\fR] [\fB\-\-no\-change\-warnings\fR] [\fB\-\-set\-section\-flags\fR \fIsection\fR=\fIflags\fR] + [\fB\-\-set\-section\-align\fR \fIsection\fR=\fIalignment\fR] + [\fB\-\-set\-section\-pad\fR \fIsection\fR=\fIalignment\fR] [\fB\-\-add\-section\fR \fIsectionname\fR=\fIfilename\fR] [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR[,\fIflags\fR]] [\fB\-\-change\-leading\-char\fR] [\fB\-\-remove\-leading\-char\fR] @@ -526,6 +528,13 @@ \&\fBcontents\fR flag of a section which does have contents\*(--just remove the section instead. Not all flags are meaningful for all object file formats. +.IP "\fB\-\-set\-section\-align\fR \fIsection\fR\fB=\fR\fIalignment\fR" 4 +.IX Item "--set-section-align section=align" +Set the alignment for the named section to 2**align. +.IP "\fB\-\-set\-section\-pad\fR \fIsection\fR\fB=\fR\fIalignment\fR" 4 +.IX Item "--set-section-pad section=pad_align" +Set the size for the named section such that its size is a multiple +of pad_align. .IP "\fB\-\-add\-section\fR \fIsectionname\fR\fB=\fR\fIfilename\fR" 4 .IX Item "--add-section sectionname=filename" Add a new section named \fIsectionname\fR while copying the file. The diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/binutils/objcopy.c binutils/binutils/objcopy.c --- binutils-2.16.1/binutils/objcopy.c 2005-03-03 12:46:12.000000000 +0100 +++ binutils/binutils/objcopy.c 2006-03-30 01:23:21.000000000 +0200 @@ -120,6 +120,10 @@ bfd_vma lma_val; /* Amount to change by or set to. */ bfd_boolean set_flags; /* Whether to set the section flags. */ flagword flags; /* What to set the section flags to. */ + bfd_boolean set_align; /* Whether to set the section alignment. */ + int alignment; /* What to set the section alignment to. */ + bfd_boolean set_pad; /* Whether to set the section alignment. */ + int pad_align; /* What to set the section alignment to. */ }; static struct section_list *change_sections; @@ -249,7 +253,9 @@ OPTION_READONLY_TEXT, OPTION_WRITABLE_TEXT, OPTION_PURE, - OPTION_IMPURE + OPTION_IMPURE, + OPTION_SET_SECTION_ALIGN, + OPTION_SET_SECTION_PAD }; /* Options to handle if running as "strip". */ @@ -336,7 +342,9 @@ {"remove-leading-char", no_argument, 0, OPTION_REMOVE_LEADING_CHAR}, {"remove-section", required_argument, 0, 'R'}, {"rename-section", required_argument, 0, OPTION_RENAME_SECTION}, + {"set-section-align", required_argument, 0, OPTION_SET_SECTION_ALIGN}, {"set-section-flags", required_argument, 0, OPTION_SET_SECTION_FLAGS}, + {"set-section-pad", required_argument, 0, OPTION_SET_SECTION_PAD}, {"set-start", required_argument, 0, OPTION_SET_START}, {"srec-len", required_argument, 0, OPTION_SREC_LEN}, {"srec-forceS3", no_argument, 0, OPTION_SREC_FORCES3}, @@ -441,6 +449,12 @@ Warn if a named section does not exist\n\ --set-section-flags =\n\ Set section 's properties to \n\ + --set-section-align =\n\ + Set section 's alignment to\n\ + 2**\n\ + --set-section-pad =\n\ + Set section 's size to a multiple of\n\ + \n\ --add-section = Add section found in to output\n\ --rename-section =[,] Rename section to \n\ --change-leading-char Force output format's leading character style\n\ @@ -1907,6 +1921,8 @@ size = bfd_section_size (ibfd, isection); if (copy_byte >= 0) size = (size + interleave - 1) / interleave; + if (p != NULL && p->set_pad) + size += p->pad_align - (size % p->pad_align); if (! bfd_set_section_size (obfd, osection, size)) { err = _("size"); @@ -1942,9 +1958,18 @@ osection->lma = lma; + if (p != NULL && p->set_align) + { + if (! bfd_set_section_alignment (obfd, osection, p->alignment)) + { + bfd_nonfatal (bfd_get_filename (obfd)); + return FALSE; + } + } + /* FIXME: This is probably not enough. If we change the LMA we may have to recompute the header for the file as well. */ - if (!bfd_set_section_alignment (obfd, + else if (!bfd_set_section_alignment (obfd, osection, bfd_section_alignment (ibfd, isection))) { @@ -2816,6 +2841,51 @@ } break; + case OPTION_SET_SECTION_ALIGN: + { + const char *s; + int len; + char *name; + + s = strchr (optarg, '='); + if (s == NULL) + fatal (_("bad format for %s"), "--set-section-align"); + + len = s - optarg; + name = xmalloc (len + 1); + strncpy (name, optarg, len); + name[len] = '\0'; + + p = find_section_list (name, TRUE); + + p->set_align = TRUE; + p->alignment = atoi (s + 1); + } + break; + + case OPTION_SET_SECTION_PAD: + { + const char *s; + int len; + char *name; + + s = strchr (optarg, '='); + if (s == NULL) + fatal (_("bad format for %s"), "--set-section-align"); + + len = s - optarg; + name = xmalloc (len + 1); + strncpy (name, optarg, len); + name[len] = '\0'; + + p = find_section_list (name, TRUE); + + p->pad_align = atoi (s + 1); + if (p->pad_align > 0) + p->set_pad = TRUE; + } + break; + case OPTION_RENAME_SECTION: { flagword flags; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/binutils/readelf.c binutils/binutils/readelf.c --- binutils-2.16.1/binutils/readelf.c 2005-04-20 20:43:36.000000000 +0200 +++ binutils/binutils/readelf.c 2006-03-30 01:23:21.000000000 +0200 @@ -102,6 +102,7 @@ #include "elf/s390.h" #include "elf/sh.h" #include "elf/sparc.h" +#include "elf/spu.h" #include "elf/v850.h" #include "elf/vax.h" #include "elf/x86-64.h" @@ -723,6 +724,7 @@ case EM_XSTORMY16: case EM_CRX: case EM_VAX: + case EM_SPU: case EM_IP2K: case EM_IP2K_OLD: case EM_IQ2000: @@ -1219,6 +1221,10 @@ rtype = elf_vax_reloc_type (type); break; + case EM_SPU: + rtype = elf_spu_reloc_type (type); + break; + case EM_IP2K: case EM_IP2K_OLD: rtype = elf_ip2k_reloc_type (type); @@ -1715,6 +1721,7 @@ case EM_OR32: return "OpenRISC"; case EM_CRX: return "National Semiconductor CRX microprocessor"; case EM_DLX: return "OpenDLX"; + case EM_SPU: return "SPU"; case EM_IP2K_OLD: case EM_IP2K: return "Ubicom IP2xxx 8-bit microcontrollers"; case EM_IQ2000: return "Vitesse IQ2000"; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/config.sub binutils/config.sub --- binutils-2.16.1/config.sub 2005-01-19 01:34:56.000000000 +0100 +++ binutils/config.sub 2006-03-30 01:23:21.000000000 +0200 @@ -114,12 +114,26 @@ exit 1;; esac +# Here we handle any "marketing" names - translating them to +# standard triplets +case $1 in + spu) + set spu-unknown-elf + ;; + ppu | ppu-elf | cellppu | cellppu-elf) + set powerpc64-unknown-linux + ;; + *) + ;; +esac + # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). # Here we must recognize all the valid KERNEL-OS combinations. maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` case $maybe_os in nto-qnx* | linux-gnu* | linux-dietlibc | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | \ - kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova*) + kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova* | \ + lv2 ) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` ;; @@ -271,6 +285,9 @@ | z8k) basic_machine=$basic_machine-unknown ;; + spu | ppu) + basic_machine=$basic_machine-unknown + ;; m6811 | m68hc11 | m6812 | m68hc12) # Motorola 68HC11/12. basic_machine=$basic_machine-unknown @@ -348,6 +365,8 @@ | ymp-* \ | z8k-*) ;; + spu-* | ppu-*) + ;; # Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) @@ -1308,6 +1327,8 @@ -zvmoe) os=-zvmoe ;; + -lv2) + ;; -none) ;; *) diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/Makefile.am binutils/gas/Makefile.am --- binutils-2.16.1/gas/Makefile.am 2005-03-22 16:31:44.000000000 +0100 +++ binutils/gas/Makefile.am 2006-03-30 01:23:21.000000000 +0200 @@ -81,6 +81,7 @@ sh \ sh64 \ sparc \ + spu \ tahoe \ tic30 \ tic4x \ @@ -279,6 +280,7 @@ config/tc-sh.c \ config/tc-sh64.c \ config/tc-sparc.c \ + config/tc-spu.c \ config/tc-tahoe.c \ config/tc-tic30.c \ config/tc-tic54x.c \ @@ -332,6 +334,7 @@ config/tc-sh.h \ config/tc-sh64.h \ config/tc-sparc.h \ + config/tc-spu.h \ config/tc-tahoe.h \ config/tc-tic30.h \ config/tc-tic54x.h \ @@ -1451,6 +1454,12 @@ $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \ $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \ dwarf2dbg.h +DEPTC_spu_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + $(INCDIR)/opcode/spu.h $(INCDIR)/elf/spu.h $(INCDIR)/elf/reloc-macros.h \ + $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h DEPTC_tahoe_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \ $(srcdir)/config/tc-tahoe.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \ $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/tahoe.h @@ -1980,6 +1989,10 @@ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h +DEPOBJ_spu_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h DEPOBJ_tahoe_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \ $(srcdir)/config/tc-tahoe.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \ $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h @@ -2362,6 +2375,9 @@ DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h +DEP_spu_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h DEP_tahoe_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tahoe.h \ $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h DEP_tahoe_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tahoe.h \ diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/as.c binutils/gas/as.c --- binutils-2.16.1/gas/as.c 2005-03-03 02:29:52.000000000 +0100 +++ binutils/gas/as.c 2006-03-30 01:23:21.000000000 +0200 @@ -1066,6 +1066,15 @@ myname = argv[0]; xmalloc_set_program_name (myname); + { + const char *response_file = expandargv (&argc, &argv); + if (response_file) + { + as_bad (_("can't open response file %s"), response_file); + xexit (1); + } + } + START_PROGRESS (myname, 0); #ifndef OBJ_DEFAULT_OUTPUT_FILE_NAME diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/config/obj-coff.c binutils/gas/config/obj-coff.c --- binutils-2.16.1/gas/config/obj-coff.c 2005-03-01 12:24:31.000000000 +0100 +++ binutils/gas/config/obj-coff.c 2006-03-30 01:23:21.000000000 +0200 @@ -26,10 +26,6 @@ #include "obstack.h" #include "subsegs.h" -#ifdef TE_PE -#include "coff/pe.h" -#endif - /* I think this is probably always correct. */ #ifndef KEEP_RELOC_INFO #define KEEP_RELOC_INFO @@ -45,10 +41,6 @@ /* This is used to hold the symbol built by a sequence of pseudo-ops from .def and .endef. */ static symbolS *def_symbol_in_progress; -#ifdef TE_PE -/* PE weak alternate symbols begin with this string. */ -static const char weak_altprefix[] = ".weak."; -#endif /* TE_PE */ typedef struct { @@ -211,6 +203,47 @@ s_lcomm (0); } +/* Handle .weak. This is a GNU extension. */ + +static void +obj_coff_weak (ignore) + int ignore ATTRIBUTE_UNUSED; +{ + char *name; + int c; + symbolS *symbolP; + + do + { + name = input_line_pointer; + c = get_symbol_end (); + symbolP = symbol_find_or_make (name); + *input_line_pointer = c; + SKIP_WHITESPACE (); + +#if defined BFD_ASSEMBLER || defined S_SET_WEAK + S_SET_WEAK (symbolP); +#endif + +#ifdef TE_PE + S_SET_STORAGE_CLASS (symbolP, C_NT_WEAK); +#else + S_SET_STORAGE_CLASS (symbolP, C_WEAKEXT); +#endif + + if (c == ',') + { + input_line_pointer++; + SKIP_WHITESPACE (); + if (*input_line_pointer == '\n') + c = '\n'; + } + } + while (c == ','); + + demand_empty_rest_of_line (); +} + #ifdef BFD_ASSEMBLER static segT fetch_coff_debug_section PARAMS ((void)); @@ -1092,135 +1125,6 @@ demand_empty_rest_of_line (); } -#ifdef TE_PE - -/* Return nonzero if name begins with weak alternate symbol prefix. */ - -static int -weak_is_altname (const char * name) -{ - return ! strncmp (name, weak_altprefix, sizeof (weak_altprefix) - 1); -} - -/* Return the name of the alternate symbol - name corresponding to a weak symbol's name. */ - -static const char * -weak_name2altname (const char * name) -{ - char *alt_name; - - alt_name = xmalloc (sizeof (weak_altprefix) + strlen (name)); - strcpy (alt_name, weak_altprefix); - return strcat (alt_name, name); -} - -/* Return the name of the weak symbol corresponding to an - alterate symbol. */ - -static const char * -weak_altname2name (const char * name) -{ - char * weak_name; - char * dot; - - assert (weak_is_altname (name)); - - weak_name = xstrdup (name + 6); - if ((dot = strchr (weak_name, '.'))) - *dot = 0; - return weak_name; -} - -/* Make a weak symbol name unique by - appending the name of an external symbol. */ - -static const char * -weak_uniquify (const char * name) -{ - char *ret; - const char * unique = ""; - -#ifdef USE_UNIQUE - if (an_external_name != NULL) - unique = an_external_name; -#endif - assert (weak_is_altname (name)); - - if (strchr (name + sizeof (weak_altprefix), '.')) - return name; - - ret = xmalloc (strlen (name) + strlen (unique) + 2); - strcpy (ret, name); - strcat (ret, "."); - strcat (ret, unique); - return ret; -} - -#endif /* TE_PE */ - -/* Handle .weak. This is a GNU extension in formats other than PE. */ - -static void -obj_coff_weak (int ignore ATTRIBUTE_UNUSED) -{ - char *name; - int c; - symbolS *symbolP; -#ifdef TE_PE - symbolS *alternateP; -#endif - - do - { - name = input_line_pointer; - c = get_symbol_end (); - if (*name == 0) - { - as_warn (_("badly formed .weak directive ignored")); - ignore_rest_of_line (); - return; - } - c = 0; - symbolP = symbol_find_or_make (name); - *input_line_pointer = c; - SKIP_WHITESPACE (); - -#if defined BFD_ASSEMBLER || defined S_SET_WEAK - S_SET_WEAK (symbolP); -#endif - -#ifdef TE_PE - /* See _Microsoft Portable Executable and Common Object - File Format Specification_, section 5.5.3. - Create a symbol representing the alternate value. - coff_frob_symbol will set the value of this symbol from - the value of the weak symbol itself. */ - S_SET_STORAGE_CLASS (symbolP, C_NT_WEAK); - S_SET_NUMBER_AUXILIARY (symbolP, 1); - SA_SET_SYM_FSIZE (symbolP, IMAGE_WEAK_EXTERN_SEARCH_LIBRARY); - - alternateP = symbol_find_or_make (weak_name2altname (name)); - S_SET_EXTERNAL (alternateP); - S_SET_STORAGE_CLASS (alternateP, C_NT_WEAK); - - SA_SET_SYM_TAGNDX (symbolP, alternateP); -#endif - - if (c == ',') - { - input_line_pointer++; - SKIP_WHITESPACE (); - if (*input_line_pointer == '\n') - c = '\n'; - } - - } - while (c == ','); - - demand_empty_rest_of_line (); -} - void coff_obj_read_begin_hook () { @@ -1259,67 +1163,14 @@ if (!block_stack) block_stack = stack_init (512, sizeof (symbolS*)); -#ifdef TE_PE - if (S_GET_STORAGE_CLASS (symp) == C_NT_WEAK - && ! S_IS_WEAK (symp) - && weak_is_altname (S_GET_NAME (symp))) + if (S_IS_WEAK (symp)) { - /* This is a weak alternate symbol. All processing of - PECOFFweak symbols is done here, through the alternate. */ - symbolS *weakp = symbol_find (weak_altname2name (S_GET_NAME (symp))); - - assert (weakp); - assert (S_GET_NUMBER_AUXILIARY (weakp) == 1); - - if (symbol_equated_p (weakp)) - { - /* The weak symbol has an alternate specified; symp is unneeded. */ - S_SET_STORAGE_CLASS (weakp, C_NT_WEAK); - SA_SET_SYM_TAGNDX (weakp, - symbol_get_value_expression (weakp)->X_add_symbol); - - S_CLEAR_EXTERNAL (symp); - *punt = 1; - return; - } - else - { - /* The weak symbol has been assigned an alternate value. - Copy this value to symp, and set symp as weakp's alternate. */ - if (S_GET_STORAGE_CLASS (weakp) != C_NT_WEAK) - { - S_SET_STORAGE_CLASS (symp, S_GET_STORAGE_CLASS (weakp)); - S_SET_STORAGE_CLASS (weakp, C_NT_WEAK); - } - - if (S_IS_DEFINED (weakp)) - { - /* This is a defined weak symbol. Copy value information - from the weak symbol itself to the alternate symbol. */ - symbol_set_value_expression (symp, - symbol_get_value_expression (weakp)); - symbol_set_frag (symp, symbol_get_frag (weakp)); - S_SET_SEGMENT (symp, S_GET_SEGMENT (weakp)); - } - else - { - /* This is an undefined weak symbol. - Define the alternate symbol to zero. */ - S_SET_VALUE (symp, 0); - S_SET_SEGMENT (symp, absolute_section); - } - - S_SET_NAME (symp, weak_uniquify (S_GET_NAME (symp))); - S_SET_STORAGE_CLASS (symp, C_EXT); - - S_SET_VALUE (weakp, 0); - S_SET_SEGMENT (weakp, undefined_section); - } +#ifdef TE_PE + S_SET_STORAGE_CLASS (symp, C_NT_WEAK); +#else + S_SET_STORAGE_CLASS (symp, C_WEAKEXT); +#endif } -#else /* TE_PE */ - if (S_IS_WEAK (symp)) - S_SET_STORAGE_CLASS (symp, C_WEAKEXT); -#endif /* TE_PE */ if (!S_IS_DEFINED (symp) && !S_IS_WEAK (symp) diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/config/tc-ppc.c binutils/gas/config/tc-ppc.c --- binutils-2.16.1/gas/config/tc-ppc.c 2005-03-02 14:24:01.000000000 +0100 +++ binutils/gas/config/tc-ppc.c 2006-03-30 01:23:21.000000000 +0200 @@ -36,6 +36,9 @@ #include "coff/pe.h" #endif +#undef TARGET_CPU +#define TARGET_CPU "cellppu" + /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ /* Tell the main code what the endianness is. */ @@ -184,8 +187,11 @@ const char FLT_CHARS[] = "dD"; /* '+' and '-' can be used as postfix predicate predictors for conditional - branches. So they need to be accepted as symbol characters. */ -const char ppc_symbol_chars[] = "+-"; + branches. So they need to be accepted as symbol characters. + No they don't. The lexer already accepts them as part of an opcode + name without adding them to ppc_symbol_chars. And if they are added + they mess up argument/expression parsing. */ +const char ppc_symbol_chars[] = ""; /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ int ppc_cie_data_alignment; @@ -906,6 +912,15 @@ ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64 | PPC_OPCODE_POWER4); } + /* -mcellppu and -mppu means assemble for the CELL PPU arhictecrue */ + /* -mdd1.0, -mdd2.0 and -mdd3.0 are here for completeness. */ + else if (strcmp (arg, "cellppu") == 0 || strcmp (arg, "ppu") == 0 + || strcmp (arg, "dd1.0") == 0 || strcmp (arg, "dd2.0") == 0 + || strcmp (arg, "dd3.0") == 0 ) + { + ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_CELLPPU + | PPC_OPCODE_ALTIVEC; + } /* -mcom means assemble for the common intersection between Power and PowerPC. At present, we just allow the union, rather than the intersection. */ @@ -1100,6 +1115,7 @@ -mbooke64 generate code for 64-bit PowerPC BookE\n\ -mbooke, mbooke32 generate code for 32-bit PowerPC BookE\n\ -mpower4 generate code for Power4 architecture\n\ +-mcellppu, mppu generate code for CELL PPU architecture\n\ -mcom generate code Power/PowerPC common instructions\n\ -many generate code for any architecture (PWR/PWRX/PPC)\n")); fprintf (stream, _("\ @@ -1134,7 +1150,13 @@ if ((ppc_cpu & ~PPC_OPCODE_ANY) == 0) { - if (ppc_obj64) + if (strncmp (default_cpu, "ppu", 2) == 0 + || strncmp (default_cpu, "cellppu", 6) == 0) + { + ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_CELLPPU + | PPC_OPCODE_ALTIVEC; + } + else if (ppc_obj64) ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64; else if (strncmp (default_os, "aix", 3) == 0 && default_os[3] >= '4' && default_os[3] <= '9') @@ -1266,7 +1288,7 @@ if ((ppc_cpu & PPC_OPCODE_601) != 0 && (op->flags & PPC_OPCODE_POWER) != 0) continue; - + as_bad (_("Internal assembler error for instruction %s"), op->name); dup_insn = TRUE; @@ -1579,6 +1601,7 @@ MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), MAP64 ("toc", BFD_RELOC_PPC_TOC16), + MAP ("sdatoc", BFD_RELOC_PPC_TOC16), MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), @@ -2363,8 +2386,6 @@ if (ex.X_op == O_illegal) as_bad (_("illegal operand")); - else if (ex.X_op == O_absent) - as_bad (_("missing operand")); else if (ex.X_op == O_register) { insn = ppc_insert_operand (insn, operand, ex.X_add_number, diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/config/tc-spu.c binutils/gas/config/tc-spu.c --- binutils-2.16.1/gas/config/tc-spu.c 1970-01-01 01:00:00.000000000 +0100 +++ binutils/gas/config/tc-spu.c 2006-03-30 01:23:21.000000000 +0200 @@ -0,0 +1,1006 @@ +/* spu.c -- Assembler for the IBM Synergistic Processing Unit (SPU) */ + +/* (C) Copyright + Sony Computer Entertainment, Inc., + Toshiba Corporation, + International Business Machines Corporation, + 2001,2002,2003,2004,2005. + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. */ + + +#include "as.h" +#include "safe-ctype.h" +#include "subsegs.h" +#include "opcode/spu.h" +#include "dwarf2dbg.h" + +const struct spu_opcode spu_opcodes[] = { +#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + { MACFORMAT, (OPCODE) << (32-11), MNEMONIC, ASMFORMAT }, +#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + { MACFORMAT, ((OPCODE) << (32-11)) | ((FB) << (32-18)), MNEMONIC, ASMFORMAT }, +#include "opcode/spu-insns.h" +#undef APUOP +#undef APUOPFB +}; + +static const int spu_num_opcodes = + sizeof (spu_opcodes) / sizeof (spu_opcodes[0]); + +#define MAX_RELOCS 2 + +struct spu_insn +{ + unsigned int opcode; + expressionS exp[MAX_RELOCS]; + int reloc_arg[MAX_RELOCS]; + int flag[MAX_RELOCS]; + enum spu_insns tag; +}; + +static const char *get_imm PARAMS ((const char *param, struct spu_insn *insn, int arg)); +static const char *get_reg PARAMS ((const char *param, struct spu_insn *insn, int arg, int accept_expr)); + +static int calcop PARAMS ((struct spu_opcode *format, + const char *param, struct spu_insn *insn)); + +extern char *myname; +static struct hash_control *op_hash = NULL; + +/* These bits should be turned off in the first address of every segment */ +int md_seg_align = 7; + +/* These chars start a comment anywhere in a source file (except inside + another comment */ +const char comment_chars[] = "#"; + +/* These chars only start a comment at the beginning of a line. */ +const char line_comment_chars[] = "#"; + +/* gods own line continuation char */ +const char line_separator_chars[] = ";"; + +/* Chars that can be used to separate mant from exp in floating point nums */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant */ +/* as in 0f123.456 */ +/* or 0H1.234E-12 (see exp chars above) */ +const char FLT_CHARS[] = "dDfF"; + +const pseudo_typeS md_pseudo_table[] = +{ + {"align", s_align_ptwo, 4}, + {"def", s_set, 0}, + {"dfloat", float_cons, 'd'}, + {"ffloat", float_cons, 'f'}, + {"global", s_globl, 0}, + {"half", cons, 2}, + {"bss", s_lcomm_bytes, 1}, + {"string", stringer, 1}, + {"word", cons, 4}, + /* Force set to be treated as an instruction. */ + {"set", NULL, 0}, + {".set", s_set, 0}, + {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 }, + {"loc", dwarf2_directive_loc, 0}, + {0,0,0} +}; + +void +md_begin () +{ + const char *retval = NULL; + int i; + + /* initialize hash table */ + + op_hash = hash_new (); + + /* loop until you see the end of the list */ + + for (i = 0; i < spu_num_opcodes; i++) + { + /* hash each mnemonic and record its position */ + + retval = hash_insert (op_hash, spu_opcodes[i].mnemonic, (PTR)&spu_opcodes[i]); + + if (retval != NULL && strcmp(retval, "exists") != 0) + as_fatal (_("Can't hash instruction '%s':%s"), + spu_opcodes[i].mnemonic, retval); + } +} + +CONST char *md_shortopts = ""; +struct option md_longopts[] = { +#define OPTION_APUASM (OPTION_MD_BASE) + {"apuasm", no_argument, NULL, OPTION_APUASM}, +#define OPTION_DD2 (OPTION_MD_BASE+1) + {"mdd2.0", no_argument, NULL, OPTION_DD2}, +#define OPTION_DD1 (OPTION_MD_BASE+2) + {"mdd1.0", no_argument, NULL, OPTION_DD1}, +#define OPTION_DD3 (OPTION_MD_BASE+3) + {"mdd3.0", no_argument, NULL, OPTION_DD3}, + { NULL, no_argument, NULL, 0 } +}; +size_t md_longopts_size = sizeof (md_longopts); + +/* When set (by -apuasm) our assembler emulates the behaviour of apuasm. + * e.g. don't add bias to float conversion and don't right shift + * immediate values. */ +static int emulate_apuasm; + +/* Use the dd2.0 instructions set. The only differences are some new + * register names and the orx insn */ +static int use_dd2 = 1; + +int +md_parse_option (c, arg) + int c; + char *arg ATTRIBUTE_UNUSED; +{ + switch(c) + { + case OPTION_APUASM: emulate_apuasm = 1; break; + case OPTION_DD3: use_dd2 = 1; break; + case OPTION_DD2: use_dd2 = 1; break; + case OPTION_DD1: use_dd2 = 0; break; + default: return 0; + } + return 1; +} + +void +md_show_usage (stream) + FILE *stream; +{ + fputs (_("\ +SPU options:\n\ + --apuasm emulate behaviour of apuasm\n"), + stream); +} + + +struct arg_encode { + int size; + int pos; + int rshift; + int lo, hi; + int wlo, whi; + bfd_reloc_code_real_type reloc; +}; +static struct arg_encode arg_encode[A_MAX] = { + { 7, 0, 0, 0, 127, 0, -1, 0 }, /* A_T */ + { 7, 7, 0, 0, 127, 0, -1, 0 }, /* A_A */ + { 7, 14, 0, 0, 127, 0, -1, 0 }, /* A_B */ + { 7, 21, 0, 0, 127, 0, -1, 0 }, /* A_C */ + { 7, 7, 0, 0, 127, 0, -1, 0 }, /* A_S */ + { 7, 7, 0, 0, 127, 0, -1, 0 }, /* A_H */ + { 0, 0, 0, 0, -1, 0, -1, 0 }, /* A_P */ + { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7 }, /* A_S3 */ + { 7, 14, 0, -32, 31, -31, 0, BFD_RELOC_SPU_IMM7 }, /* A_S6 */ + { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7 }, /* A_S7N */ + { 7, 14, 0, -64, 63, -63, 0, BFD_RELOC_SPU_IMM7 }, /* A_S7 */ + { 8, 14, 0, 0, 127, 0, -1, BFD_RELOC_SPU_IMM8 }, /* A_U7A */ + { 8, 14, 0, 0, 127, 0, -1, BFD_RELOC_SPU_IMM8 }, /* A_U7B */ + { 10, 14, 0, -512, 511, -128, 255, BFD_RELOC_SPU_IMM10 }, /* A_S10B */ + { 10, 14, 0, -512, 511, 0, -1, BFD_RELOC_SPU_IMM10 }, /* A_S10 */ + { 2, 23, 9, -1024, 1023, 0, -1, BFD_RELOC_SPU_PCREL9a }, /* A_S11 */ + { 2, 14, 9, -1024, 1023, 0, -1, BFD_RELOC_SPU_PCREL9b }, /* A_S11I */ + { 10, 14, 4, -8192, 8191, 0, -1, BFD_RELOC_SPU_IMM10W }, /* A_S14 */ + { 16, 7, 0, -32768, 32767, 0, -1, BFD_RELOC_SPU_IMM16 }, /* A_S16 */ + { 16, 7, 2, -131072, 262143, 0, -1, BFD_RELOC_SPU_IMM16W }, /* A_S18 */ + { 16, 7, 2, -262144, 262143, 0, -1, BFD_RELOC_SPU_PCREL16 }, /* A_R18 */ + { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7 }, /* A_U3 */ + { 7, 14, 0, 0, 127, 0, 31, BFD_RELOC_SPU_IMM7 }, /* A_U5 */ + { 7, 14, 0, 0, 127, 0, 63, BFD_RELOC_SPU_IMM7 }, /* A_U6 */ + { 7, 14, 0, 0, -1, 0, -1, BFD_RELOC_SPU_IMM7 }, /* A_U7 */ + { 14, 0, 0, 0, 16383, 0, -1, 0 }, /* A_U14 */ + { 16, 7, 0, -32768, 65535, 0, -1, BFD_RELOC_SPU_IMM16 }, /* A_X16 */ + { 18, 7, 0, 0, 262143, 0, -1, BFD_RELOC_SPU_IMM18 }, /* A_U18 */ +}; + +/* Some flags for handling errors. This is very hackish and added after + * the fact. */ +static int syntax_error_arg; +static char * syntax_error_param; +static int syntax_reg; + +static char * +insn_fmt_string(struct spu_opcode *format) +{ + static char buf[64]; + int len = 0; + int i; + int paren; + len += sprintf (&buf[len], "%s\t", format->mnemonic); + for (i = 1; i <= format->arg[0]; i++) + { + int arg = format->arg[i]; + char *exp; + if (i > 1 && arg != A_P && format->arg[i-1] != A_P) + buf[len++] = ','; + if (arg == A_P) + exp = "("; + else if (arg < A_P) + exp = i == syntax_error_arg ? "REG" : "reg"; + else + exp = i == syntax_error_arg ? "IMM" : "imm"; + len += sprintf (&buf[len], "%s", exp); + if (i > 1 && format->arg[i-1] == A_P) + buf[len++] = ')'; + } + buf[len] = 0; + return buf; +} + +void +md_assemble (op) + char *op; +{ + char *param, *thisfrag; + char c; + struct spu_opcode *format; + struct spu_insn insn; + int i; + + assert (op); + + /* skip over instruction to find parameters */ + + for (param = op; *param != 0 && !ISSPACE (*param); param++) + ; + c = *param; + *param = 0; + + if (c != 0 && c != '\n') + param++; + + /* try to find the instruction in the hash table */ + + if ((format = (struct spu_opcode *) hash_find (op_hash, op)) == NULL) + { + as_bad (_("Invalid mnemonic '%s'"), op); + return; + } + + if (!use_dd2 && strcmp(format->mnemonic, "orx") == 0) + { + as_bad (_("'%s' is only available in DD2.0 or higher."), op); + return; + } + + while (1) + { + /* try parsing this instruction into insn */ + + for (i = 0; i < MAX_RELOCS; i++) + { + insn.exp[i].X_add_symbol = 0; + insn.exp[i].X_op_symbol = 0; + insn.exp[i].X_add_number = 0; + insn.exp[i].X_op = O_illegal; + insn.reloc_arg[i] = -1; + insn.flag[i] = 0; + } + insn.opcode = format->opcode; + insn.tag = (enum spu_insns)(format - spu_opcodes); + + syntax_error_arg = 0; + syntax_error_param = 0; + syntax_reg = 0; + if (calcop (format, param, &insn)) + break; + + /* if it doesn't parse try the next instruction */ + if (!strcmp (format[0].mnemonic, format[1].mnemonic)) + format++; + else + { + int parg = format[0].arg[syntax_error_arg-1]; + char *exp; + as_fatal (_("Error in argument %d. Expecting: \"%s\""), + syntax_error_arg - (parg == A_P), + insn_fmt_string(format)); + return; + } + } + + if ((syntax_reg & 4) + && ! (insn.tag == M_RDCH + || insn.tag == M_RCHCNT + || insn.tag == M_WRCH)) + as_warn (_("Mixing register syntax, with and without '$'.")); + if (syntax_error_param) + { + char *d = syntax_error_param; + while (*d != '$') + d--; + as_warn (_("Treating '%-*s' as a symbol."), syntax_error_param-d, d); + } + + /* grow the current frag and plop in the opcode */ + + thisfrag = frag_more (4); + md_number_to_chars (thisfrag, insn.opcode, 4); + + /* if this instruction requires labels mark it for later */ + + for (i = 0; i < MAX_RELOCS; i++) + if (insn.reloc_arg[i] >= 0) + { + fixS *fixP; + bfd_reloc_code_real_type reloc = arg_encode[insn.reloc_arg[i]].reloc; + int pcrel = 0; + if (reloc == BFD_RELOC_SPU_PCREL9a + || reloc == BFD_RELOC_SPU_PCREL9b + || reloc == BFD_RELOC_SPU_PCREL16) + pcrel = 1; + if (insn.flag[i] & 1) reloc = BFD_RELOC_SPU_HI16; + else if (insn.flag[i] & 2) reloc = BFD_RELOC_SPU_LO16; + fixP = fix_new_exp (frag_now, + thisfrag - frag_now->fr_literal, + 4, + &insn.exp[i], + pcrel, + reloc); + fixP->tc_fix_data = insn.reloc_arg[i]; + } + dwarf2_emit_insn(4); +} + +static int +calcop (format, param, insn) + struct spu_opcode *format; + const char *param; + struct spu_insn *insn; +{ + int i; + int paren = 0; + int arg; + + for (i = 1; i <= format->arg[0]; i++) + { + arg = format->arg[i]; + syntax_error_arg = i; + + while (ISSPACE(*param)) + param++; + if (*param == 0 || *param == ',') + return 0; + if (arg < A_P) + param = get_reg (param, insn, arg, 1); + else if (arg > A_P) + param = get_imm (param, insn, arg); + else if (arg == A_P) + { + paren++; + if ('(' != *param++) + return 0; + } + + if (!param) + return 0; + + while (ISSPACE(*param)) + param++; + + if (arg != A_P && paren) + { + paren--; + if (')' != *param++) + return 0; + } + else if (i < format->arg[0] + && format->arg[i] != A_P + && format->arg[i+1] != A_P) + { + if (',' != *param++) + { + syntax_error_arg++; + return 0; + } + } + } + while (ISSPACE(*param)) + param++; + return !paren && (*param == 0 || *param == '\n'); +} + +struct reg_name { + int regno; + int length; + char name[32]; +}; +#define REG_NAME(NO,NM) { NO, sizeof(NM)-1, NM } +static struct reg_name reg_name[] = { + REG_NAME(0, "lr"), /* link register */ + REG_NAME(1, "sp"), /* stack pointer */ + REG_NAME(0, "rp"), /* link register */ + REG_NAME(127, "fp"), /* frame pointer */ +}; +static struct reg_name sp_reg_name[] = { +}; +static struct reg_name ch_reg_name[] = { + REG_NAME( 0, "SPU_RdEventStat"), + REG_NAME( 1, "SPU_WrEventMask"), + REG_NAME( 2, "SPU_WrEventAck"), + REG_NAME( 3, "SPU_RdSigNotify1"), + REG_NAME( 4, "SPU_RdSigNotify2"), + REG_NAME( 7, "SPU_WrDec"), + REG_NAME( 8, "SPU_RdDec"), + REG_NAME( 11, "SPU_RdEventStatMask"), /* DD2.0 only */ + REG_NAME( 13, "SPU_RdMachStat"), + REG_NAME( 14, "SPU_WrSRR0"), + REG_NAME( 15, "SPU_RdSRR0"), + REG_NAME( 28, "SPU_WrOutMbox"), + REG_NAME( 29, "SPU_RdInMbox"), + REG_NAME( 30, "SPU_WrOutIntrMbox"), + REG_NAME( 9, "MFC_WrMSSyncReq"), + REG_NAME( 12, "MFC_RdTagMask"), /* DD2.0 only */ + REG_NAME( 16, "MFC_LSA"), + REG_NAME( 17, "MFC_EAH"), + REG_NAME( 18, "MFC_EAL"), + REG_NAME( 19, "MFC_Size"), + REG_NAME( 20, "MFC_TagID"), + REG_NAME( 21, "MFC_Cmd"), + REG_NAME( 22, "MFC_WrTagMask"), + REG_NAME( 23, "MFC_WrTagUpdate"), + REG_NAME( 24, "MFC_RdTagStat"), + REG_NAME( 25, "MFC_RdListStallStat"), + REG_NAME( 26, "MFC_WrListStallAck"), + REG_NAME( 27, "MFC_RdAtomicStat"), +}; +#undef REG_NAME + +static const char * +get_reg (param, insn, arg, accept_expr) + const char *param; + struct spu_insn *insn; + int arg; + int accept_expr; +{ + unsigned regno; + int saw_prefix = 0; + + if (*param == '$') + { + saw_prefix = 1; + param++; + } + + if (arg == A_H) /* Channel */ + { + if ((param[0] == 'c' || param[0] == 'C') + && (param[1] == 'h' || param[1] == 'H') + && ISDIGIT(param[2])) + param += 2; + } + else if (arg == A_S) /* Special purpose register */ + { + if ((param[0] == 's' || param[0] == 'S') + && (param[1] == 'p' || param[1] == 'P') + && ISDIGIT(param[2])) + param += 2; + } + + if (ISDIGIT(*param)) + { + regno = 0; + while (ISDIGIT(*param)) + regno = regno * 10 + *param++ - '0'; + } + else + { + struct reg_name *rn; + unsigned int i, n, l = 0; + + if (arg == A_H) /* Channel */ + { + rn = ch_reg_name; + n = sizeof(ch_reg_name)/sizeof(*ch_reg_name); + } + else if (arg == A_S) /* Special purpose register */ + { + rn = sp_reg_name; + n = sizeof(sp_reg_name)/sizeof(*sp_reg_name); + } + else + { + rn = reg_name; + n = sizeof(reg_name)/sizeof(*reg_name); + } + regno = 128; + for (i = 0; i < n; i++) + if (rn[i].length > l + && 0 == strncasecmp(param, rn[i].name, rn[i].length)) + { + l = rn[i].length; + regno = rn[i].regno; + } + param += l; + } + + if (!use_dd2 + && arg == A_H) + { + if (regno == 11) + as_bad (_("'SPU_RdEventStatMask' (channel 11) is only available in DD2.0 or higher.")); + else if (regno == 12) + as_bad (_("'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher.")); + } + + if (regno < 128) + { + insn->opcode |= regno << arg_encode[arg].pos; + if ((!saw_prefix && syntax_reg == 1) + || (saw_prefix && syntax_reg == 2)) + syntax_reg |= 4; + syntax_reg |= saw_prefix ? 1 : 2; + return param; + } + if (accept_expr) + { + char *save_ptr; + expressionS ex; + save_ptr = input_line_pointer; + input_line_pointer = (char *)param; + expression (&ex); + param = input_line_pointer; + input_line_pointer = save_ptr; + if (ex.X_op == O_register || ex.X_op == O_constant) + { + insn->opcode |= ex.X_add_number << arg_encode[arg].pos; + return param; + } + } + return 0; +} + +static const char * +get_imm (param, insn, arg) + const char *param; + struct spu_insn *insn; + int arg; +{ + int val; + char *save_ptr; + int low = 0, high = 0; + int reloc_i = insn->reloc_arg[0] >= 0 ? 1 : 0; + + if (strncmp(param, "%lo(", 4) == 0) + { + param += 3; + low = 1; + as_warn (_("Using old style, %%lo(expr), please change to PPC style, expr@l.")); + } + else if (strncmp(param, "%hi(", 4) == 0) + { + param += 3; + high = 1; + as_warn (_("Using old style, %%hi(expr), please change to PPC style, expr@h.")); + } + else if (strncmp(param, "%pic(", 5) == 0) + { + /* Currently we expect %pic(expr) == expr, so do nothing here. + * i.e. for code loaded at address 0 $toc will be 0. */ + param += 4; + } + + if (*param == '$') + { + /* Symbols can start with $, but if this symbol matches a register + * name, it's probably a mistake. The only way to avoid this + * warning is to rename the symbol. */ + struct spu_insn tmp_insn; + char *np; + if ((np = get_reg (param, &tmp_insn, arg, 0))) + syntax_error_param = np; + } + + save_ptr = input_line_pointer; + input_line_pointer = (char *)param; + expression (&insn->exp[reloc_i]); + param = input_line_pointer; + input_line_pointer = save_ptr; + + /* Similar to ppc_elf_suffix in tc-ppc.c. We have so few cases to + * handle we do it inlined here. */ + if (param[0] == '@' && !ISALNUM(param[2]) && param[2] != '@') + { + if (param[1] == 'h' || param[1] == 'H') + { + high = 1; + param += 2; + } + else if (param[1] == 'l' || param[1] == 'L') + { + low = 1; + param += 2; + } + } + + val = insn->exp[reloc_i].X_add_number; + + if (insn->exp[reloc_i].X_op == O_constant) + { + if (emulate_apuasm) + { + /* Convert the value to a format we expect. */ + val <<= arg_encode[arg].rshift; + if (arg == A_U7A) + val = 173 - val; + else if (arg == A_U7B) + val = 155 - val; + } + + if (high) + val = val >> 16; + else if (low) + val = val & 0xffff; + + /* Warn about out of range expressions. */ + { + int hi = arg_encode[arg].hi; + int lo = arg_encode[arg].lo; + int whi = arg_encode[arg].whi; + int wlo = arg_encode[arg].wlo; + if (hi > lo && (val < lo || val > hi)) + as_fatal (_("Constant expression %d out of range, [%d, %d]."), val, lo, hi); + else if (whi > wlo && (val < wlo || val > whi)) + as_warn (_("Constant expression %d out of range, [%d, %d]."), val, wlo, whi); + } + + if (arg == A_U7A) + val = 173 - val; + else if (arg == A_U7B) + val = 155 - val; + + /* Branch hints have a split encoding. Do the bottom part. */ + if (arg == A_S11 || arg == A_S11I) + insn->opcode |= ((val >> 2) & 0x7f); + + insn->opcode |= ((val >> arg_encode[arg].rshift) + & ((1<reloc_arg[reloc_i] = -1; + insn->flag[reloc_i] = 0; + } + else + { + insn->reloc_arg[reloc_i] = arg; + if (high) insn->flag[reloc_i] |= 1; + if (low) insn->flag[reloc_i] |= 2; + } + + return param; +} + +void +md_number_to_chars (buf, val, nbytes) + char *buf; + valueT val; + int nbytes; +{ + number_to_chars_bigendian (buf, val, nbytes); +} + +#define MAX_LITTLENUMS 6 + +/* Turn a string in input_line_pointer into a floating point constant of type + type, and store the appropriate bytes in *litP. The number of LITTLENUMS + emitted is stored in *sizeP . An error message is returned, or NULL on OK. + */ +char * +md_atof (type, litP, sizeP) + char type; + char *litP; + int *sizeP; +{ + int prec; + LITTLENUM_TYPE words[MAX_LITTLENUMS]; + LITTLENUM_TYPE *wordP; + char *t; + + switch (type) + { + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + case 'x': + case 'X': + prec = 6; + break; + + case 'p': + case 'P': + prec = 6; + break; + + default: + *sizeP = 0; + return _("Bad call to MD_ATOF()"); + } + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + + *sizeP = prec * sizeof (LITTLENUM_TYPE); + for (wordP = words; prec--;) + { + md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + return 0; +} + +int md_short_jump_size = 4; + +void +md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) + char *ptr; + addressT from_addr ATTRIBUTE_UNUSED, to_addr ATTRIBUTE_UNUSED; + fragS *frag; + symbolS *to_symbol; +{ + ptr[0] = (char) 0xc0; + ptr[1] = 0x00; + ptr[2] = 0x00; + ptr[3] = 0x00; + fix_new (frag, + ptr - frag->fr_literal, + 4, + to_symbol, + (offsetT) 0, + 0, + BFD_RELOC_SPU_PCREL16); +} + +int md_long_jump_size = 4; + +void +md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) + char *ptr; + addressT from_addr ATTRIBUTE_UNUSED, to_addr ATTRIBUTE_UNUSED; + fragS *frag; + symbolS *to_symbol; +{ + ptr[0] = (char) 0xc0; + ptr[1] = 0x00; + ptr[2] = 0x00; + ptr[3] = 0x00; + fix_new (frag, + ptr - frag->fr_literal, + 4, + to_symbol, + (offsetT) 0, + 0, + BFD_RELOC_SPU_PCREL16); +} + +int +md_estimate_size_before_relax (fragP, segment_type) + fragS *fragP ATTRIBUTE_UNUSED; + segT segment_type ATTRIBUTE_UNUSED; +{ + as_fatal (_("Relaxation should never occur")); + return (-1); +} + +/* If while processing a fixup, a reloc really needs to be created, + then it is done here. */ + +arelent * +tc_gen_reloc (seg, fixp) + asection *seg ATTRIBUTE_UNUSED; + fixS *fixp; +{ + arelent *reloc; + reloc = (arelent *) xmalloc (sizeof (arelent)); + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + if (fixp->fx_addsy) + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + else if (fixp->fx_subsy) + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); + if (reloc->howto == (reloc_howto_type *) NULL) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + _("reloc %d not supported by object file format"), + (int) fixp->fx_r_type); + return NULL; + } + reloc->addend = fixp->fx_addnumber; + return reloc; +} + +/* Round up a section's size to the appropriate boundary. */ + +valueT +md_section_align (seg, size) + segT seg; + valueT size; +{ + int align = bfd_get_section_alignment (stdoutput, seg); + valueT mask = ((valueT) 1 << align) - 1; + + return (size + mask) & ~mask; +} + +/* Where a PC relative offset is calculated from. On the spu they + are calculated from the beginning of the branch instruction. */ + +long +md_pcrel_from (fixp) + fixS *fixp; +{ + switch (fixp->fx_r_type) + { + case BFD_RELOC_SPU_PCREL9a: + case BFD_RELOC_SPU_PCREL9b: + case BFD_RELOC_SPU_PCREL16: + return fixp->fx_frag->fr_address + fixp->fx_where; + default: + abort (); + } + /*NOTREACHED*/ +} + +/* Fill in rs_align_code fragments. */ + +void +spu_handle_align (fragp) + fragS *fragp; +{ + static const unsigned char nop_pattern[8] = { + 0x40, 0x20, 0x00, 0x00, /* even nop */ + 0x00, 0x20, 0x00, 0x00, /* odd nop */ + }; + + int bytes; + char *p; + + if (fragp->fr_type != rs_align_code) + return; + + bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; + p = fragp->fr_literal + fragp->fr_fix; + + if (bytes & 3) + { + int fix = bytes & 3; + memset (p, 0, fix); + p += fix; + bytes -= fix; + fragp->fr_fix += fix; + } + if (bytes & 4) + { + memcpy (p, &nop_pattern[4], 4); + p += 4; + bytes -= 4; + fragp->fr_fix += 4; + } + + memcpy (p, nop_pattern, 8); + fragp->fr_var = 8; +} + +void +md_apply_fix3 (fixP, valP, seg) + fixS *fixP; + valueT * valP; + segT seg ATTRIBUTE_UNUSED; +{ + unsigned int res; + long val = (long)*valP; + char *place = fixP->fx_where + fixP->fx_frag->fr_literal; + + if (fixP->fx_addsy != NULL) + { + /* Hack around bfd_install_relocation brain damage. */ + if (fixP->fx_pcrel) + val += fixP->fx_frag->fr_address + fixP->fx_where; + } + + fixP->fx_addnumber = val; + + if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) + { + fixP->fx_done = 1; + res = 0; + if (fixP->tc_fix_data > A_P) + { + int hi = arg_encode[fixP->tc_fix_data].hi; + int lo = arg_encode[fixP->tc_fix_data].lo; + if (hi > lo && (val < lo || val > hi)) + as_bad_where (fixP->fx_file, fixP->fx_line, + "Relocation doesn't fit. (relocation value = 0x%x)", + (int) val); + } + switch (fixP->fx_r_type) + { + case 0: + break; + case BFD_RELOC_SPU_IMM7: + res = (val & 0x7f) << 14; + break; + case BFD_RELOC_SPU_IMM8: + res = (val & 0xff) << 14; + break; + case BFD_RELOC_SPU_IMM10: + res = (val & 0xcff) << 14; + break; + case BFD_RELOC_SPU_IMM10W: + res = (val & 0xcff0) << 10; + break; + case BFD_RELOC_SPU_IMM16: + res = (val & 0xffff) << 7; + break; + case BFD_RELOC_SPU_IMM16W: + res = (val & 0x3fffc) << 5; + break; + case BFD_RELOC_SPU_IMM18: + res = (val & 0x3ffff) << 7; + break; + case BFD_RELOC_16: +#if 0 + val = fixP->fx_offset; + number_to_chars_bigendian (place, val, 2); +#endif + res = val; + break; + case BFD_RELOC_32: + res = val; + break; + case BFD_RELOC_SPU_PCREL9a: + res = ((val & 0x1fc) >> 2) | ((val & 0x600) << 14); + break; + case BFD_RELOC_SPU_PCREL9b: + res = ((val & 0x1fc) >> 2) | ((val & 0x600) << 5); + break; + case BFD_RELOC_SPU_PCREL16: + res = (val & 0x3fffc) << 5; + break; + + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("reloc %d not supported by object file format"), + (int) fixP->fx_r_type); + abort (); + } + if (res != 0) + { + place[0] |= (res >> 24) & 0xff; + place[1] |= (res >> 16) & 0xff; + place[2] |= (res >> 8) & 0xff; + place[3] |= (res) & 0xff; + } + } +} diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/config/tc-spu.h binutils/gas/config/tc-spu.h --- binutils-2.16.1/gas/config/tc-spu.h 1970-01-01 01:00:00.000000000 +0100 +++ binutils/gas/config/tc-spu.h 2006-03-30 01:23:21.000000000 +0200 @@ -0,0 +1,107 @@ +/* spu.h -- Assembler for spu */ + +/* (C) Copyright + Sony Computer Entertainment, Inc., + Toshiba Corporation, + International Business Machines Corporation, + 2001,2002,2003,2004,2005. + + This file is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This file is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#define TC_SPU + +#ifdef OBJ_ELF +#define TARGET_FORMAT "elf32-spu" +#define TARGET_ARCH bfd_arch_spu +#define TARGET_NAME "elf32-spu" +#endif + +#define TARGET_BYTES_BIG_ENDIAN 1 + +#ifndef TARGET_NAME +#define TARGET_NAME "coff-spu" +#endif + +#ifndef TARGET_ARCH +#define TARGET_ARCH bfd_arch_spu +#endif + +#define COFF_MAGIC SPU_MAGIC +#define BFD_ARCH bfd_arch_spu + +#define NEED_FX_R_TYPE +#define TC_KEEP_FX_OFFSET +/* #define TC_CONS_RELOC RELOC_32 */ + +/* If defined, fixS will have a member named tc_fix_data of this type. */ +#define TC_FIX_TYPE int +#define TC_INIT_FIX_DATA(FIXP) ((FIXP)->tc_fix_data = 0) + +#define TC_FIX_ADJUSTABLE(FIXP) 0 + +/* Values passed to md_apply_fix3 don't include symbol values. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +/* This expression evaluates to false if the relocation is for a local + object for which we still want to do the relocation at runtime. + True if we are willing to perform this relocation while building + the .o file. This is only used for pcrel relocations. */ + +#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ + ((FIX)->fx_addsy == NULL \ + || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ + && ! S_IS_WEAK ((FIX)->fx_addsy) \ + && S_IS_DEFINED ((FIX)->fx_addsy) \ + && ! S_IS_COMMON ((FIX)->fx_addsy))) + +/* The spu uses pseudo-ops with no leading period. */ +#define NO_PSEUDO_DOT 1 + +/* Don't warn on word overflow; it happens on %hi relocs. */ +#undef WARN_SIGNED_OVERFLOW_WORD + +#define md_convert_frag(b,s,f) {as_fatal (_("spu convert_frag\n"));} + +/* We don't need to do anything special for undefined symbols. */ +#define md_undefined_symbol(s) 0 + +/* We have no special operand handling. */ +#define md_operand(e) + +/* Fill in rs_align_code fragments. */ +extern void spu_handle_align PARAMS ((fragS *)); +#define HANDLE_ALIGN(frag) spu_handle_align (frag) + +#define MAX_MEM_FOR_RS_ALIGN_CODE (7 + 8) + +#ifdef SPUCOFF + +/* Whether a reloc should be output. */ +#define TC_COUNT_RELOC(fixp) ((fixp)->fx_addsy != NULL || (fixp)->fx_subsy != NULL) + +/* Get the BFD reloc type to use for a gas fixS structure. */ +#define TC_COFF_FIX2RTYPE(fixp) tc_coff_fix2rtype (fixp) + +/* No special hook needed for symbols. */ +#define tc_coff_symbol_emit_hook(s) + +/* Align sections to a four byte boundary. */ +#ifndef max +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#endif +#define SUB_SEGMENT_ALIGN(SEG) max (section_alignment[(int) (SEG)], 4) + +#endif /* SPUCOFF */ diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/configure.tgt binutils/gas/configure.tgt --- binutils-2.16.1/gas/configure.tgt 2005-01-31 18:18:51.000000000 +0100 +++ binutils/gas/configure.tgt 2006-03-30 01:23:21.000000000 +0200 @@ -58,6 +58,7 @@ pj*) cpu_type=pj endian=big ;; powerpc*le*) cpu_type=ppc endian=little ;; powerpc*) cpu_type=ppc endian=big ;; + ppu*) cpu_type=ppc endian=big ;; rs6000*) cpu_type=ppc ;; s390x*) cpu_type=s390 arch=s390x ;; s390*) cpu_type=s390 arch=s390 ;; @@ -338,6 +339,7 @@ ppc-*-macos*) fmt=coff em=macos ;; ppc-*-nto*) fmt=elf ;; ppc-*-kaos*) fmt=elf ;; + ppc-*-lv2*) fmt=elf ;; ppc-*-lynxos*) fmt=elf em=lynx bfd_gas=yes ;; s390-*-linux-gnu*) fmt=elf em=linux ;; @@ -385,6 +387,9 @@ strongarm-*-elf) fmt=elf ;; strongarm-*-kaos*) fmt=elf ;; + spu-*-elf) fmt=elf bfd_gas=yes ;; + spu-*-lv2) fmt=elf bfd_gas=yes ;; + tic30-*-*aout*) fmt=aout bfd_gas=yes ;; tic30-*-*coff*) fmt=coff bfd_gas=yes ;; tic4x-*-* | c4x-*-*) fmt=coff bfd_gas=yes ;; diff --exclude '*.po' --exclude Makefile.in -ruN binutils-2.16.1/gas/doc/as.info-1 binutils/gas/doc/as.info-1 --- binutils-2.16.1/gas/doc/as.info-1 2005-06-12 21:02:26.000000000 +0200 +++ binutils/gas/doc/as.info-1 2006-03-30 01:23:21.000000000 +0200 @@ -1,5 +1,5 @@ -This is ../.././gas/doc/as.info, produced by makeinfo version 4.7 from -../.././gas/doc/as.texinfo. +This is /vobs/toolchain/binutils/gas/doc/as.info, produced by makeinfo +version 4.5 from /vobs/toolchain/binutils/gas/doc/as.texinfo. START-INFO-DIR-ENTRY * As: (as). The GNU assembler. @@ -24,7 +24,7 @@ Using as ******** -This file is a user guide to the GNU assembler `as' version 2.16.1. + This file is a user guide to the GNU assembler `as' version 2.16.1. This document is distributed under the terms of the GNU Free Documentation License. A copy of the license is included in the @@ -48,11 +48,11 @@  File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top -1 Overview -********** +Overview +******** -Here is a brief summary of how to invoke `as'. For details, *note -Command-Line Options: Invoking. + Here is a brief summary of how to invoke `as'. For details, *note +Command-Line Options: Invoking.. as [-a[cdhlns][=FILE]] [-alternate] [-D] [-defsym SYM=VAL] [-f] [-g] [-gstabs] [-gstabs+] @@ -63,17 +63,17 @@ [-version] [-version] [-W] [-warn] [-fatal-warnings] [-w] [-x] [-Z] [-target-help] [TARGET-OPTIONS] [-|FILES ...] - + _Target Alpha options:_ [-mCPU] [-mdebug | -no-mdebug] [-relax] [-g] [-GSIZE] [-F] [-32addr] - + _Target ARC options:_ [-marc[5|6|7|8]] [-EB|-EL] - + _Target ARM options:_ [-mcpu=PROCESSOR[+EXTENSION...]] [-march=ARCHITECTURE[+EXTENSION...]] @@ -85,27 +85,27 @@ [-mapcs-32|-mapcs-26|-mapcs-float| -mapcs-reentrant] [-mthumb-interwork] [-k] - + _Target CRIS options:_ [-underscore | -no-underscore] [-pic] [-N] [-emulation=criself | -emulation=crisaout] [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] - + _Target D10V options:_ [-O] - + _Target D30V options:_ [-O|-n|-N] - + _Target i386 options:_ [-32|-64] [-n] - + _Target i960 options:_ [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB| -AKC|-AMC] [-b] [-no-relax] - + _Target IA-64 options:_ [-mconstant-gp|-mauto-pic] [-milp32|-milp64|-mlp64|-mp64] @@ -113,17 +113,17 @@ [-munwind-check=warning|-munwind-check=error] [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] [-x|-xexplicit] [-xauto] [-xdebug] - + _Target IP2K options:_ [-mip2022|-mip2022ext] - + _Target M32R options:_ [-m32rx|-[no-]warn-explicit-parallel-conflicts| -W[n]p] - + _Target M680X0 options:_ [-l] [-m68000|-m68010|-m68020|...] - + _Target M68HC11 options:_ [-m68hc11|-m68hc12|-m68hcs12] [-mshort|-mlong] @@ -131,11 +131,11 @@ [-force-long-branchs] [-short-branchs] [-strict-direct-mode] [-print-insn-syntax] [-print-opcodes] [-generate-example] - + _Target MCORE options:_ [-jsri2bsr] [-sifilter] [-relax] [-mcpu=[210|340]] - + _Target MIPS options:_ [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] @@ -152,21 +152,21 @@ [-mdmx] [-no-mdmx] [-mdebug] [-no-mdebug] [-mpdr] [-mno-pdr] - + _Target MMIX options:_ [-fixed-special-register-names] [-globalize-symbols] [-gnu-syntax] [-relax] [-no-predefined-symbols] [-no-expand] [-no-merge-gregs] [-x] [-linker-allocated-gregs] - + _Target PDP11 options:_ [-mpic|-mno-pic] [-mall] [-mno-extensions] [-mEXTENSION|-mno-EXTENSION] [-mCPU] [-mMACHINE] - + _Target picoJava options:_ [-mb|-me] - + _Target PowerPC options:_ [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604| -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke| @@ -176,17 +176,17 @@ [-mrelocatable|-mrelocatable-lib] [-mlittle|-mlittle-endian|-mbig|-mbig-endian] [-msolaris|-mno-solaris] - + _Target SPARC options:_ [-Av6|-Av7|-Av8|-Asparclet|-Asparclite -Av8plus|-Av8plusa|-Av9|-Av9a] [-xarch=v8plus|-xarch=v8plusa] [-bump] [-32|-64] - + _Target TIC54X options:_ [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] [-merrors-to-file |-me ] - + _Target Xtensa options:_ [-[no-]text-section-literals] [-[no-]absolute-literals] [-[no-]target-align] [-[no-]longcalls] @@ -794,10 +794,10 @@  File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview -1.1 Structure of this Manual -============================ +Structure of this Manual +======================== -This manual is intended to describe what you need to know to use GNU + This manual is intended to describe what you need to know to use GNU `as'. We cover the syntax expected in source files, including notation for symbols, constants, and expressions; the directives that `as' understands; and of course how to invoke `as'. @@ -816,14 +816,15 @@  File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview -1.2 The GNU Assembler -===================== +The GNU Assembler +================= -GNU `as' is really a family of assemblers. If you use (or have used) -the GNU assembler on one architecture, you should find a fairly similar -environment when you use it on another architecture. Each version has -much in common with the others, including object file formats, most -assembler directives (often called "pseudo-ops") and assembler syntax. + GNU `as' is really a family of assemblers. If you use (or have +used) the GNU assembler on one architecture, you should find a fairly +similar environment when you use it on another architecture. Each +version has much in common with the others, including object file +formats, most assembler directives (often called "pseudo-ops") and +assembler syntax. `as' is primarily intended to assemble the output of the GNU C compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried @@ -841,10 +842,10 @@  File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview -1.3 Object File Formats -======================= +Object File Formats +=================== -The GNU assembler can be configured to produce several alternative + The GNU assembler can be configured to produce several alternative object file formats. For the most part, this does not affect how you write assembly language programs; but directives for debugging symbols are typically different in different file formats. *Note Symbol @@ -853,12 +854,12 @@  File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview -1.4 Command Line -================ +Command Line +============ -After the program name `as', the command line may contain options and -file names. Options may appear in any order, and may be before, after, -or between file names. The order of file names is significant. + After the program name `as', the command line may contain options +and file names. Options may appear in any order, and may be before, +after, or between file names. The order of file names is significant. `--' (two hyphens) by itself names the standard input file explicitly, as one of the files for `as' to assemble. @@ -880,13 +881,13 @@  File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview -1.5 Input Files -=============== +Input Files +=========== -We use the phrase "source program", abbreviated "source", to describe -the program input to one run of `as'. The program may be in one or -more files; how the source is partitioned into files doesn't change the -meaning of the source. + We use the phrase "source program", abbreviated "source", to +describe the program input to one run of `as'. The program may be in +one or more files; how the source is partitioned into files doesn't +change the meaning of the source. The source program is a concatenation of the text in all the files, in the order specified. @@ -912,9 +913,9 @@ Filenames and Line-numbers -------------------------- -There are two ways of locating a line in the input file (or files) and -either may be used in reporting error messages. One way refers to a -line number in a physical file; the other refers to a line number in a + There are two ways of locating a line in the input file (or files) +and either may be used in reporting error messages. One way refers to +a line number in a physical file; the other refers to a line number in a "logical" file. *Note Error and Warning Messages: Errors. "Physical files" are those files named in the command line given to @@ -930,10 +931,10 @@  File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview -1.6 Output (Object) File -======================== +Output (Object) File +==================== -Every time you run `as' it produces an output file, which is your + Every time you run `as' it produces an output file, which is your assembly language program translated into numbers. This file is the object file. Its default name is `a.out', or `b.out' when `as' is configured for the Intel 80960. You can give it another name by using @@ -951,14 +952,14 @@  File: as.info, Node: Errors, Prev: Object, Up: Overview -1.7 Error and Warning Messages -============================== +Error and Warning Messages +========================== -`as' may write warnings and error messages to the standard error file -(usually your terminal). This should not happen when a compiler runs -`as' automatically. Warnings report an assumption made so that `as' -could keep assembling a flawed program; errors report a grave problem -that stops the assembly. + `as' may write warnings and error messages to the standard error +file (usually your terminal). This should not happen when a compiler +runs `as' automatically. Warnings report an assumption made so that +`as' could keep assembling a flawed program; errors report a grave +problem that stops the assembly. Warning messages have the format @@ -981,12 +982,12 @@  File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top -2 Command-Line Options -********************** +Command-Line Options +******************** -This chapter describes command-line options available in _all_ versions -of the GNU assembler; *note Machine Dependencies::, for options specific -to particular machine architectures. + This chapter describes command-line options available in _all_ +versions of the GNU assembler; *note Machine Dependencies::, for +options specific to particular machine architectures. If you are invoking `as' via the GNU C compiler, you can use the `-Wa' option to pass arguments through to the assembler. The assembler @@ -1030,10 +1031,10 @@  File: as.info, Node: a, Next: alternate, Up: Invoking -2.1 Enable Listings: `-a[cdhlns]' -================================= +Enable Listings: `-a[cdhlns]' +============================= -These options enable listing output from the assembler. By itself, + These options enable listing output from the assembler. By itself, `-a' requests high-level, assembly, and symbols listing. You can use other letters to select specific options for the list: `-ah' requests a high-level language listing, `-al' requests an output-program assembly @@ -1069,27 +1070,28 @@  File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking -2.2 `--alternate' -================= +`--alternate' +============= -Begin in alternate macro mode, see *Note `.altmacro': Altmacro. + Begin in alternate macro mode, see *Note `.altmacro': Altmacro.  File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking -2.3 `-D' -======== +`-D' +==== -This option has no effect whatsoever, but it is accepted to make it more -likely that scripts written for other assemblers also work with `as'. + This option has no effect whatsoever, but it is accepted to make it +more likely that scripts written for other assemblers also work with +`as'.  File: as.info, Node: f, Next: I, Prev: D, Up: Invoking -2.4 Work Faster: `-f' -===================== +Work Faster: `-f' +================= -`-f' should only be used when assembling programs written by a + `-f' should only be used when assembling programs written by a (trusted) compiler. `-f' stops the assembler from doing whitespace and comment preprocessing on the input file(s) before assembling them. *Note Preprocessing: Preprocessing. @@ -1101,34 +1103,34 @@  File: as.info, Node: I, Next: K, Prev: f, Up: Invoking -2.5 `.include' Search Path: `-I' PATH -===================================== +`.include' Search Path: `-I' PATH +================================= -Use this option to add a PATH to the list of directories `as' searches -for files specified in `.include' directives (*note `.include': -Include.). You may use `-I' as many times as necessary to include a -variety of paths. The current working directory is always searched -first; after that, `as' searches any `-I' directories in the same order -as they were specified (left to right) on the command line. + Use this option to add a PATH to the list of directories `as' +searches for files specified in `.include' directives (*note +`.include': Include.). You may use `-I' as many times as necessary to +include a variety of paths. The current working directory is always +searched first; after that, `as' searches any `-I' directories in the +same order as they were specified (left to right) on the command line.  File: as.info, Node: K, Next: L, Prev: I, Up: Invoking -2.6 Difference Tables: `-K' -=========================== +Difference Tables: `-K' +======================= -`as' sometimes alters the code emitted for directives of the form -`.word SYM1-SYM2'; *note `.word': Word. You can use the `-K' option if -you want a warning issued when this is done. + `as' sometimes alters the code emitted for directives of the form +`.word SYM1-SYM2'; *note `.word': Word.. You can use the `-K' option +if you want a warning issued when this is done.  File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking -2.7 Include Local Labels: `-L' -============================== +Include Local Labels: `-L' +========================== -Labels beginning with `L' (upper case only) are called "local labels". -*Note Symbol Names::. Normally you do not see such labels when + Labels beginning with `L' (upper case only) are called "local +labels". *Note Symbol Names::. Normally you do not see such labels when debugging, because they are intended for the use of programs (like compilers) that compose assembler programs, not for your notice. Normally both `as' and `ld' discard such labels, so you do not normally @@ -1145,10 +1147,10 @@  File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking -2.8 Configuring listing output: `--listing' -=========================================== +Configuring listing output: `--listing' +======================================= -The listing feature of the assembler can be enabled via the command + The listing feature of the assembler can be enabled via the command line switch `-a' (*note a::). This feature combines the input source file(s) with a hex dump of the corresponding locations in the output object file, and displays them as a listing file. The format of this @@ -1182,10 +1184,10 @@  File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking -2.9 Assemble in MRI Compatibility Mode: `-M' -============================================ +Assemble in MRI Compatibility Mode: `-M' +======================================== -The `-M' or `--mri' option selects MRI compatibility mode. This + The `-M' or `--mri' option selects MRI compatibility mode. This changes the syntax and pseudo-op handling of `as' to make it compatible with the `ASM68K' or the `ASM960' (depending upon the configured target) assembler from Microtec Research. The exact nature of the MRI @@ -1313,11 +1315,11 @@  File: as.info, Node: MD, Next: o, Prev: M, Up: Invoking -2.10 Dependency Tracking: `--MD' -================================ +Dependency Tracking: `--MD' +=========================== -`as' can generate a dependency file for the file it creates. This file -consists of a single rule suitable for `make' describing the + `as' can generate a dependency file for the file it creates. This +file consists of a single rule suitable for `make' describing the dependencies of the main source file. The rule is written to the file named in its argument. @@ -1327,13 +1329,13 @@  File: as.info, Node: o, Next: R, Prev: MD, Up: Invoking -2.11 Name the Object File: `-o' -=============================== +Name the Object File: `-o' +========================== -There is always one object file output when you run `as'. By default -it has the name `a.out' (or `b.out', for Intel 960 targets only). You -use this option (which takes exactly one filename) to give the object -file a different name. + There is always one object file output when you run `as'. By +default it has the name `a.out' (or `b.out', for Intel 960 targets +only). You use this option (which takes exactly one filename) to give +the object file a different name. Whatever the object file is called, `as' overwrites any existing file of the same name. @@ -1341,10 +1343,10 @@  File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking -2.12 Join Data and Text Sections: `-R' -====================================== +Join Data and Text Sections: `-R' +================================= -`-R' tells `as' to write the object file as if all data-section data + `-R' tells `as' to write the object file as if all data-section data lives in the text section. This is only done at the very last moment: your binary data are the same, but data section parts are relocated differently. The data section part of your object file is zero bytes @@ -1365,23 +1367,23 @@  File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking -2.13 Display Assembly Statistics: `--statistics' -================================================ +Display Assembly Statistics: `--statistics' +=========================================== -Use `--statistics' to display two statistics about the resources used by -`as': the maximum amount of space allocated during the assembly (in -bytes), and the total execution time taken for the assembly (in CPU + Use `--statistics' to display two statistics about the resources +used by `as': the maximum amount of space allocated during the assembly +(in bytes), and the total execution time taken for the assembly (in CPU seconds).  File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking -2.14 Compatible Output: `--traditional-format' -============================================== +Compatible Output: `--traditional-format' +========================================= -For some targets, the output of `as' is different in some ways from the -output of some existing assembler. This switch requests `as' to use -the traditional format instead. + For some targets, the output of `as' is different in some ways from +the output of some existing assembler. This switch requests `as' to +use the traditional format instead. For example, it disables the exception frame optimizations which `as' normally does by default on `gcc' output. @@ -1389,19 +1391,20 @@  File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking -2.15 Announce Version: `-v' -=========================== +Announce Version: `-v' +====================== -You can find out what version of as is running by including the option -`-v' (which you can also spell as `-version') on the command line. + You can find out what version of as is running by including the +option `-v' (which you can also spell as `-version') on the command +line.  File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking -2.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings' -====================================================================== +Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings' +================================================================= -`as' should never give a warning or error message when assembling + `as' should never give a warning or error message when assembling compiler output. But programs written by people often cause `as' to give a warning that a particular assumption was made. All such warnings are directed to the standard error file. @@ -1420,23 +1423,23 @@  File: as.info, Node: Z, Prev: W, Up: Invoking -2.17 Generate Object File in Spite of Errors: `-Z' -================================================== +Generate Object File in Spite of Errors: `-Z' +============================================= -After an error message, `as' normally produces no output. If for some -reason you are interested in object file output even after `as' gives -an error message on your program, use the `-Z' option. If there are -any errors, `as' continues anyways, and writes an object file after a -final warning message of the form `N errors, M warnings, generating bad -object file.' + After an error message, `as' normally produces no output. If for +some reason you are interested in object file output even after `as' +gives an error message on your program, use the `-Z' option. If there +are any errors, `as' continues anyways, and writes an object file after +a final warning message of the form `N errors, M warnings, generating +bad object file.'  File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top -3 Syntax -******** +Syntax +****** -This chapter describes the machine-independent syntax allowed in a + This chapter describes the machine-independent syntax allowed in a source file. `as' syntax is similar to what many other assemblers use; it is inspired by the BSD 4.2 assembler, except that `as' does not assemble Vax bit-fields. @@ -1453,10 +1456,10 @@  File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax -3.1 Preprocessing -================= +Preprocessing +============= -The `as' internal preprocessor: + The `as' internal preprocessor: * adjusts and removes extra whitespace. It leaves one space or tab before the keywords on a line, and turns any other whitespace on the line into a single space. @@ -1489,21 +1492,22 @@  File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax -3.2 Whitespace -============== +Whitespace +========== -"Whitespace" is one or more blanks or tabs, in any order. Whitespace -is used to separate symbols, and to make programs neater for people to -read. Unless within character constants (*note Character Constants: -Characters.), any whitespace means the same as exactly one space. + "Whitespace" is one or more blanks or tabs, in any order. +Whitespace is used to separate symbols, and to make programs neater for +people to read. Unless within character constants (*note Character +Constants: Characters.), any whitespace means the same as exactly one +space.  File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax -3.3 Comments -============ +Comments +======== -There are two ways of rendering comments to `as'. In both cases the + There are two ways of rendering comments to `as'. In both cases the comment is equivalent to one space. Anything from `/*' through the next `*/' is a comment. This means @@ -1513,7 +1517,7 @@ The only way to include a newline ('\n') in a comment is to use this sort of comment. */ - + /* This sort of comment does not nest. */ Anything from the "line comment" character to the next newline is @@ -1555,33 +1559,33 @@  File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax -3.4 Symbols -=========== +Symbols +======= -A "symbol" is one or more characters chosen from the set of all letters -(both upper and lower case), digits and the three characters `_.$'. On -most machines, you can also use `$' in symbol names; exceptions are -noted in *Note Machine Dependencies::. No symbol may begin with a -digit. Case is significant. There is no length limit: all characters -are significant. Symbols are delimited by characters not in that set, -or by the beginning of a file (since the source program must end with a -newline, the end of a file is not a possible symbol delimiter). *Note -Symbols::. + A "symbol" is one or more characters chosen from the set of all +letters (both upper and lower case), digits and the three characters +`_.$'. On most machines, you can also use `$' in symbol names; +exceptions are noted in *Note Machine Dependencies::. No symbol may +begin with a digit. Case is significant. There is no length limit: +all characters are significant. Symbols are delimited by characters +not in that set, or by the beginning of a file (since the source +program must end with a newline, the end of a file is not a possible +symbol delimiter). *Note Symbols::.  File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax -3.5 Statements -============== +Statements +========== -A "statement" ends at a newline character (`\n') or line separator + A "statement" ends at a newline character (`\n') or line separator character. (The line separator is usually `;', unless this conflicts with the comment character; *note Machine Dependencies::.) The newline or separator character is considered part of the preceding statement. Newlines and separators within character constants are an exception: they do not end statements. -It is an error to end any statement with end-of-file: the last + It is an error to end any statement with end-of-file: the last character of any input file should be a newline. An empty statement is allowed, and may include whitespace. It is @@ -1613,10 +1617,10 @@  File: as.info, Node: Constants, Prev: Statements, Up: Syntax -3.6 Constants -============= +Constants +========= -A constant is a number, written so that its value is known by + A constant is a number, written so that its value is known by inspection, without knowing any context. Like this: .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. .ascii "Ring the bell\7" # A string constant. @@ -1632,11 +1636,11 @@  File: as.info, Node: Characters, Next: Numbers, Up: Constants -3.6.1 Character Constants -------------------------- +Character Constants +------------------- -There are two kinds of character constants. A "character" stands for -one character in one byte and its value may be used in numeric + There are two kinds of character constants. A "character" stands +for one character in one byte and its value may be used in numeric expressions. String constants (properly called string _literals_) are potentially many bytes and their values may not be used in arithmetic expressions. @@ -1649,10 +1653,10 @@  File: as.info, Node: Strings, Next: Chars, Up: Characters -3.6.1.1 Strings -............... +Strings +....... -A "string" is written between double-quotes. It may contain + A "string" is written between double-quotes. It may contain double-quotes or null characters. The way to get special characters into a string is to "escape" these characters: precede them with a backslash `\' character. For example `\\' represents one backslash: @@ -1709,10 +1713,10 @@  File: as.info, Node: Chars, Prev: Strings, Up: Characters -3.6.1.2 Characters -.................. +Characters +.......... -A single character may be written as a single quote immediately + A single character may be written as a single quote immediately followed by that character. The same escapes apply to characters as to strings. So if you want to write the character backslash, you must write `'\\' where the first `\' escapes the second `\'. As you can @@ -1726,10 +1730,10 @@  File: as.info, Node: Numbers, Prev: Characters, Up: Constants -3.6.2 Number Constants ----------------------- +Number Constants +---------------- -`as' distinguishes three kinds of numbers according to how they are + `as' distinguishes three kinds of numbers according to how they are stored in the target machine. _Integers_ are numbers that would fit into an `int' in the C language. _Bignums_ are integers, but they are stored in more than 32 bits. _Flonums_ are floating point numbers, @@ -1744,11 +1748,11 @@  File: as.info, Node: Integers, Next: Bignums, Up: Numbers -3.6.2.1 Integers -................ +Integers +........ -A binary integer is `0b' or `0B' followed by zero or more of the binary -digits `01'. + A binary integer is `0b' or `0B' followed by zero or more of the +binary digits `01'. An octal integer is `0' followed by zero or more of the octal digits (`01234567'). @@ -1766,21 +1770,21 @@  File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers -3.6.2.2 Bignums -............... +Bignums +....... -A "bignum" has the same syntax and semantics as an integer except that -the number (or its negative) takes more than 32 bits to represent in -binary. The distinction is made because in some places integers are + A "bignum" has the same syntax and semantics as an integer except +that the number (or its negative) takes more than 32 bits to represent +in binary. The distinction is made because in some places integers are permitted while bignums are not.  File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers -3.6.2.3 Flonums -............... +Flonums +....... -A "flonum" represents a floating point number. The translation is + A "flonum" represents a floating point number. The translation is indirect: a decimal floating point number from the text is converted by `as' to a generic binary floating point number of more than sufficient precision. This generic floating point number is converted to a @@ -1831,8 +1835,8 @@  File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top -4 Sections and Relocation -************************* +Sections and Relocation +*********************** * Menu: @@ -1845,12 +1849,12 @@  File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections -4.1 Background -============== +Background +========== -Roughly, a section is a range of addresses, with no gaps; all data "in" -those addresses is treated the same for some particular purpose. For -example there may be a "read only" section. + Roughly, a section is a range of addresses, with no gaps; all data +"in" those addresses is treated the same for some particular purpose. +For example there may be a "read only" section. The linker `ld' reads many object files (partial programs) and combines their contents to form a runnable program. When `as' emits an @@ -1912,7 +1916,8 @@ In fact, every address `as' ever uses is expressed as (SECTION) + (OFFSET INTO SECTION) - Further, most expressions `as' computes have this section-relative + +Further, most expressions `as' computes have this section-relative nature. (For some object formats, such as SOM for the HPPA, some expressions are symbol-relative instead.) @@ -1950,10 +1955,10 @@  File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections -4.2 Linker Sections -=================== +Linker Sections +=============== -`ld' deals with just four kinds of sections, summarized below. + `ld' deals with just four kinds of sections, summarized below. *named sections* *text section* @@ -1994,28 +1999,28 @@ +-----+----+--+ partial program # 1: |ttttt|dddd|00| +-----+----+--+ - + text data bss seg. seg. seg. - + +---+---+---+ partial program # 2: |TTT|DDD|000| +---+---+---+ - + +--+---+-----+--+----+---+-----+~~ linked program: | |TTT|ttttt| |dddd|DDD|00000| +--+---+-----+--+----+---+-----+~~ - + addresses: 0 ...  File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections -4.3 Assembler Internal Sections -=============================== +Assembler Internal Sections +=========================== -These sections are meant only for the internal use of `as'. They have -no meaning at run-time. You do not really need to know about these + These sections are meant only for the internal use of `as'. They +have no meaning at run-time. You do not really need to know about these sections for most purposes; but they can be mentioned in `as' warning messages, so it might be helpful to have an idea of their meanings to `as'. These sections are used to permit the value of every expression @@ -2033,10 +2038,10 @@  File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections -4.4 Sub-Sections -================ +Sub-Sections +============ -Assembled bytes conventionally fall into two sections: text and data. + Assembled bytes conventionally fall into two sections: text and data. You may have separate groups of data in named sections that you want to end up near to each other in the object file, even though they are not contiguous in the assembler source. `as' allows you to use @@ -2049,7 +2054,7 @@ compiler could issue a `.text 0' before each section of code being output, and a `.text 1' before each group of constants being output. -Subsections are optional. If you do not use subsections, everything + Subsections are optional. If you do not use subsections, everything goes in subsection number zero. Each subsection is zero-padded up to a multiple of four bytes. @@ -2096,10 +2101,10 @@  File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections -4.5 bss Section -=============== +bss Section +=========== -The bss section is used for local common variable storage. You may + The bss section is used for local common variable storage. You may allocate address space in the bss section, but you may not dictate data to load into it before your program executes. When your program starts running, all the contents of the bss section are zeroed bytes. @@ -2119,10 +2124,10 @@  File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top -5 Symbols -********* +Symbols +******* -Symbols are a central concept: the programmer uses symbols to name + Symbols are a central concept: the programmer uses symbols to name things, the linker uses symbols to link, and the debugger uses symbols to debug. @@ -2140,14 +2145,14 @@  File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols -5.1 Labels -========== +Labels +====== -A "label" is written as a symbol immediately followed by a colon `:'. -The symbol then represents the current value of the active location -counter, and is, for example, a suitable instruction operand. You are -warned if you use the same symbol to represent two different locations: -the first definition overrides any other definitions. + A "label" is written as a symbol immediately followed by a colon +`:'. The symbol then represents the current value of the active +location counter, and is, for example, a suitable instruction operand. +You are warned if you use the same symbol to represent two different +locations: the first definition overrides any other definitions. On the HPPA, the usual form for a label need not be immediately followed by a colon, but instead must start in column zero. Only one @@ -2158,20 +2163,21 @@  File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols -5.2 Giving Symbols Other Values -=============================== +Giving Symbols Other Values +=========================== -A symbol can be given an arbitrary value by writing a symbol, followed -by an equals sign `=', followed by an expression (*note Expressions::). -This is equivalent to using the `.set' directive. *Note `.set': Set. + A symbol can be given an arbitrary value by writing a symbol, +followed by an equals sign `=', followed by an expression (*note +Expressions::). This is equivalent to using the `.set' directive. +*Note `.set': Set.  File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols -5.3 Symbol Names -================ +Symbol Names +============ -Symbol names begin with a letter or with one of `._'. On most + Symbol names begin with a letter or with one of `._'. On most machines, you can also use `$' in symbol names; exceptions are noted in *Note Machine Dependencies::. That character may be followed by any string of digits, letters, dollar signs (unless otherwise noted in @@ -2179,8 +2185,8 @@ family, `?' is also allowed in the body of a symbol name, though not at its beginning. -Case of letters is significant: `foo' is a different symbol name than -`Foo'. + Case of letters is significant: `foo' is a different symbol name +than `Foo'. Each symbol has exactly one name. Each name in an assembly language program refers to exactly one symbol. You may use that symbol name any @@ -2189,7 +2195,7 @@ Local Symbol Names ------------------ -Local symbols help compilers and programmers use names temporarily. + Local symbols help compilers and programmers use names temporarily. They create symbols which are guaranteed to be unique over the entire scope of the input source code and which can be referred to by a simple notation. To define a local symbol, write a label of the form `N:' @@ -2258,7 +2264,7 @@ Dollar Local Labels ------------------- -`as' also supports an even more local form of local labels called + `as' also supports an even more local form of local labels called dollar labels. These labels go out of scope (ie they become undefined) as soon as a non-local label is defined. Thus they remain valid for only a small region of the input source code. Normal local labels, by @@ -2277,10 +2283,10 @@  File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols -5.4 The Special Dot Symbol -========================== +The Special Dot Symbol +====================== -The special symbol `.' refers to the current address that `as' is + The special symbol `.' refers to the current address that `as' is assembling into. Thus, the expression `melvin: .long .' defines `melvin' to contain its own address. Assigning a value to `.' is treated the same as a `.org' directive. Thus, the expression `.=.+4' @@ -2289,10 +2295,10 @@  File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols -5.5 Symbol Attributes -===================== +Symbol Attributes +================= -Every symbol has, as well as its name, the attributes "Value" and + Every symbol has, as well as its name, the attributes "Value" and "Type". Depending on output format, symbols can also have auxiliary attributes. @@ -2315,12 +2321,12 @@  File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes -5.5.1 Value ------------ +Value +----- -The value of a symbol is (usually) 32 bits. For a symbol which labels a -location in the text, data, bss or absolute sections the value is the -number of addresses from the start of that section to the label. + The value of a symbol is (usually) 32 bits. For a symbol which +labels a location in the text, data, bss or absolute sections the value +is the number of addresses from the start of that section to the label. Naturally for text, data and bss sections the value of a symbol changes as `ld' changes section base addresses during linking. Absolute symbols' values do not change during linking: that is why they are @@ -2338,10 +2344,10 @@  File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes -5.5.2 Type ----------- +Type +---- -The type attribute of a symbol contains relocation (section) + The type attribute of a symbol contains relocation (section) information, any flag settings indicating that a symbol is external, and (optionally), other information for linkers and debuggers. The exact format depends on the object-code output format in use. @@ -2349,8 +2355,8 @@  File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes -5.5.3 Symbol Attributes: `a.out' --------------------------------- +Symbol Attributes: `a.out' +-------------------------- * Menu: @@ -2360,51 +2366,51 @@  File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols -5.5.3.1 Descriptor -.................. +Descriptor +.......... -This is an arbitrary 16-bit value. You may establish a symbol's + This is an arbitrary 16-bit value. You may establish a symbol's descriptor value by using a `.desc' statement (*note `.desc': Desc.). A descriptor value means nothing to `as'.  File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols -5.5.3.2 Other -............. +Other +..... -This is an arbitrary 8-bit value. It means nothing to `as'. + This is an arbitrary 8-bit value. It means nothing to `as'.  File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes -5.5.4 Symbol Attributes for COFF --------------------------------- +Symbol Attributes for COFF +-------------------------- -The COFF format supports a multitude of auxiliary symbol attributes; + The COFF format supports a multitude of auxiliary symbol attributes; like the primary symbol attributes, they are set between `.def' and `.endef' directives. -5.5.4.1 Primary Attributes -.......................... +Primary Attributes +.................. -The symbol name is set with `.def'; the value and type, respectively, -with `.val' and `.type'. + The symbol name is set with `.def'; the value and type, +respectively, with `.val' and `.type'. -5.5.4.2 Auxiliary Attributes -............................ +Auxiliary Attributes +.................... -The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and + The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and `.weak' can generate auxiliary symbol table information for COFF.  File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes -5.5.5 Symbol Attributes for SOM -------------------------------- +Symbol Attributes for SOM +------------------------- -The SOM format for the HPPA supports a multitude of symbol attributes -set with the `.EXPORT' and `.IMPORT' directives. + The SOM format for the HPPA supports a multitude of symbol +attributes set with the `.EXPORT' and `.IMPORT' directives. The attributes are described in `HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT' @@ -2413,11 +2419,11 @@  File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top -6 Expressions -************* +Expressions +*********** -An "expression" specifies an address or numeric value. Whitespace may -precede and/or follow an expression. + An "expression" specifies an address or numeric value. Whitespace +may precede and/or follow an expression. The result of an expression must be an absolute number, or else an offset into a particular section. If an expression is not absolute, @@ -2434,10 +2440,10 @@  File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions -6.1 Empty Expressions -===================== +Empty Expressions +================= -An empty expression has no value: it is just whitespace or null. + An empty expression has no value: it is just whitespace or null. Wherever an absolute expression is required, you may omit the expression, and `as' assumes a value of (absolute) 0. This is compatible with other assemblers. @@ -2445,10 +2451,10 @@  File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions -6.2 Integer Expressions -======================= +Integer Expressions +=================== -An "integer expression" is one or more _arguments_ delimited by + An "integer expression" is one or more _arguments_ delimited by _operators_. * Menu: @@ -2461,15 +2467,15 @@  File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs -6.2.1 Arguments ---------------- +Arguments +--------- -"Arguments" are symbols, numbers or subexpressions. In other contexts -arguments are sometimes called "arithmetic operands". In this manual, -to avoid confusing them with the "instruction operands" of the machine -language, we use the term "argument" to refer to parts of expressions -only, reserving the word "operand" to refer only to machine instruction -operands. + "Arguments" are symbols, numbers or subexpressions. In other +contexts arguments are sometimes called "arithmetic operands". In this +manual, to avoid confusing them with the "instruction operands" of the +machine language, we use the term "argument" to refer to parts of +expressions only, reserving the word "operand" to refer only to machine +instruction operands. Symbols are evaluated to yield {SECTION NNN} where SECTION is one of text, data, bss, absolute, or undefined. NNN is a signed, 2's @@ -2489,10 +2495,10 @@  File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs -6.2.2 Operators ---------------- +Operators +--------- -"Operators" are arithmetic functions, like `+' or `%'. Prefix + "Operators" are arithmetic functions, like `+' or `%'. Prefix operators are followed by an argument. Infix operators appear between their arguments. Operators may be preceded and/or followed by whitespace. @@ -2500,10 +2506,10 @@  File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs -6.2.3 Prefix Operator ---------------------- +Prefix Operator +--------------- -`as' has the following "prefix operators". They each take one + `as' has the following "prefix operators". They each take one argument, which must be absolute. `-' @@ -2515,10 +2521,10 @@  File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs -6.2.4 Infix Operators ---------------------- +Infix Operators +--------------- -"Infix operators" take two arguments, one on either side. Operators + "Infix operators" take two arguments, one on either side. Operators have precedence, but operations with equal precedence are performed left to right. Apart from `+' or `-', both arguments must be absolute, and the result is absolute. @@ -2614,10 +2620,10 @@  File: as.info, Node: Pseudo Ops, Next: Machine Dependencies, Prev: Expressions, Up: Top -7 Assembler Directives -********************** +Assembler Directives +******************** -All assembler directives have names that begin with a period (`.'). + All assembler directives have names that begin with a period (`.'). The rest of the name is letters, usually in lower case. This chapter discusses directives that are available regardless of @@ -2768,22 +2774,22 @@  File: as.info, Node: Abort, Next: ABORT, Up: Pseudo Ops -7.1 `.abort' -============ +`.abort' +======== -This directive stops the assembly immediately. It is for compatibility -with other assemblers. The original idea was that the assembly -language source would be piped into the assembler. If the sender of -the source quit, it could use this directive tells `as' to quit also. -One day `.abort' will not be supported. + This directive stops the assembly immediately. It is for +compatibility with other assemblers. The original idea was that the +assembly language source would be piped into the assembler. If the +sender of the source quit, it could use this directive tells `as' to +quit also. One day `.abort' will not be supported.  File: as.info, Node: ABORT, Next: Align, Prev: Abort, Up: Pseudo Ops -7.2 `.ABORT' -============ +`.ABORT' +======== -When producing COFF output, `as' accepts this directive as a synonym + When producing COFF output, `as' accepts this directive as a synonym for `.abort'. When producing `b.out' output, `as' accepts this directive, but @@ -2792,10 +2798,10 @@  File: as.info, Node: Align, Next: Altmacro, Prev: ABORT, Up: Pseudo Ops -7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR' -========================================= +`.align ABS-EXPR, ABS-EXPR, ABS-EXPR' +===================================== -Pad the location counter (in the current subsection) to a particular + Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the alignment required, as described below. @@ -2837,29 +2843,29 @@  File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops -7.4 `.ascii "STRING"'... -======================== +`.ascii "STRING"'... +==================== -`.ascii' expects zero or more string literals (*note Strings::) + `.ascii' expects zero or more string literals (*note Strings::) separated by commas. It assembles each string (with no automatic trailing zero byte) into consecutive addresses.  File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops -7.5 `.asciz "STRING"'... -======================== +`.asciz "STRING"'... +==================== -`.asciz' is just like `.ascii', but each string is followed by a zero -byte. The "z" in `.asciz' stands for "zero". + `.asciz' is just like `.ascii', but each string is followed by a +zero byte. The "z" in `.asciz' stands for "zero".  File: as.info, Node: Balign, Next: Byte, Prev: Asciz, Up: Pseudo Ops -7.6 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' -============================================== +`.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' +========================================== -Pad the location counter (in the current subsection) to a particular + Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the alignment request in bytes. For example `.balign 8' advances the location counter until it is a multiple of 8. If the location counter @@ -2892,21 +2898,21 @@  File: as.info, Node: Byte, Next: Comm, Prev: Balign, Up: Pseudo Ops -7.7 `.byte EXPRESSIONS' -======================= +`.byte EXPRESSIONS' +=================== -`.byte' expects zero or more expressions, separated by commas. Each + `.byte' expects zero or more expressions, separated by commas. Each expression is assembled into the next byte.  File: as.info, Node: Comm, Next: CFI directives, Prev: Byte, Up: Pseudo Ops -7.8 `.comm SYMBOL , LENGTH ' -============================ +`.comm SYMBOL , LENGTH ' +======================== -`.comm' declares a common symbol named SYMBOL. When linking, a common -symbol in one object file may be merged with a defined or common symbol -of the same name in another object file. If `ld' does not see a + `.comm' declares a common symbol named SYMBOL. When linking, a +common symbol in one object file may be merged with a defined or common +symbol of the same name in another object file. If `ld' does not see a definition for the symbol-just one or more common symbols-then it will allocate LENGTH bytes of uninitialized memory. LENGTH must be an absolute expression. If `ld' sees multiple common symbols with the @@ -2929,89 +2935,90 @@  File: as.info, Node: CFI directives, Next: Data, Prev: Comm, Up: Pseudo Ops -7.9 `.cfi_startproc' -==================== +`.cfi_startproc' +================ -`.cfi_startproc' is used at the beginning of each function that should -have an entry in `.eh_frame'. It initializes some internal data + `.cfi_startproc' is used at the beginning of each function that +should have an entry in `.eh_frame'. It initializes some internal data structures and emits architecture dependent initial CFI instructions. Don't forget to close the function by `.cfi_endproc'. -7.10 `.cfi_endproc' -=================== +`.cfi_endproc' +============== -`.cfi_endproc' is used at the end of a function where it closes its + `.cfi_endproc' is used at the end of a function where it closes its unwind entry previously opened by `.cfi_startproc'. and emits it to `.eh_frame'. -7.11 `.cfi_def_cfa REGISTER, OFFSET' -==================================== +`.cfi_def_cfa REGISTER, OFFSET' +=============================== -`.cfi_def_cfa' defines a rule for computing CFA as: take address from -REGISTER and add OFFSET to it. + `.cfi_def_cfa' defines a rule for computing CFA as: take address +from REGISTER and add OFFSET to it. -7.12 `.cfi_def_cfa_register REGISTER' -===================================== +`.cfi_def_cfa_register REGISTER' +================================ -`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on -REGISTER will be used instead of the old one. Offset remains the same. + `.cfi_def_cfa_register' modifies a rule for computing CFA. From now +on REGISTER will be used instead of the old one. Offset remains the +same. -7.13 `.cfi_def_cfa_offset OFFSET' -================================= +`.cfi_def_cfa_offset OFFSET' +============================ -`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register + `.cfi_def_cfa_offset' modifies a rule for computing CFA. Register remains the same, but OFFSET is new. Note that it is the absolute offset that will be added to a defined register to compute CFA address. -7.14 `.cfi_adjust_cfa_offset OFFSET' -==================================== +`.cfi_adjust_cfa_offset OFFSET' +=============================== -Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is + Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is added/substracted from the previous offset. -7.15 `.cfi_offset REGISTER, OFFSET' -=================================== +`.cfi_offset REGISTER, OFFSET' +============================== -Previous value of REGISTER is saved at offset OFFSET from CFA. + Previous value of REGISTER is saved at offset OFFSET from CFA. -7.16 `.cfi_rel_offset REGISTER, OFFSET' -======================================= +`.cfi_rel_offset REGISTER, OFFSET' +================================== -Previous value of REGISTER is saved at offset OFFSET from the current -CFA register. This is transformed to `.cfi_offset' using the known -displacement of the CFA register from the CFA. This is often easier to -use, because the number will match the code it's annotating. + Previous value of REGISTER is saved at offset OFFSET from the +current CFA register. This is transformed to `.cfi_offset' using the +known displacement of the CFA register from the CFA. This is often +easier to use, because the number will match the code it's annotating. -7.17 `.cfi_window_save' -======================= +`.cfi_window_save' +================== -SPARC register window has been saved. + SPARC register window has been saved. -7.18 `.cfi_escape' EXPRESSION[, ...] -==================================== +`.cfi_escape' EXPRESSION[, ...] +=============================== -Allows the user to add arbitrary bytes to the unwind info. One might -use this to add OS-specific CFI opcodes, or generic CFI opcodes that -GAS does not yet support. + Allows the user to add arbitrary bytes to the unwind info. One +might use this to add OS-specific CFI opcodes, or generic CFI opcodes +that GAS does not yet support.  File: as.info, Node: Data, Next: Def, Prev: CFI directives, Up: Pseudo Ops -7.19 `.data SUBSECTION' -======================= +`.data SUBSECTION' +================== -`.data' tells `as' to assemble the following statements onto the end of -the data subsection numbered SUBSECTION (which is an absolute + `.data' tells `as' to assemble the following statements onto the end +of the data subsection numbered SUBSECTION (which is an absolute expression). If SUBSECTION is omitted, it defaults to zero.  File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops -7.20 `.def NAME' -================ +`.def NAME' +=========== -Begin defining debugging information for a symbol NAME; the definition -extends until the `.endef' directive is encountered. + Begin defining debugging information for a symbol NAME; the +definition extends until the `.endef' directive is encountered. This directive is only observed when `as' is configured for COFF format output; when producing `b.out', `.def' is recognized, but @@ -3020,10 +3027,10 @@  File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops -7.21 `.desc SYMBOL, ABS-EXPRESSION' -=================================== +`.desc SYMBOL, ABS-EXPRESSION' +============================== -This directive sets the descriptor of the symbol (*note Symbol + This directive sets the descriptor of the symbol (*note Symbol Attributes::) to the low 16 bits of an absolute expression. The `.desc' directive is not available when `as' is configured for @@ -3034,11 +3041,11 @@  File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops -7.22 `.dim' -=========== +`.dim' +====== -This directive is generated by compilers to include auxiliary debugging -information in the symbol table. It is only permitted inside + This directive is generated by compilers to include auxiliary +debugging information in the symbol table. It is only permitted inside `.def'/`.endef' pairs. `.dim' is only meaningful when generating COFF format output; when @@ -3047,10 +3054,10 @@  File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops -7.23 `.double FLONUMS' -====================== +`.double FLONUMS' +================= -`.double' expects zero or more flonums, separated by commas. It + `.double' expects zero or more flonums, separated by commas. It assembles floating point numbers. The exact kind of floating point numbers emitted depends on how `as' is configured. *Note Machine Dependencies::. @@ -3058,47 +3065,48 @@  File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops -7.24 `.eject' -============= +`.eject' +======== -Force a page break at this point, when generating assembly listings. + Force a page break at this point, when generating assembly listings.  File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops -7.25 `.else' -============ +`.else' +======= -`.else' is part of the `as' support for conditional assembly; *note -`.if': If. It marks the beginning of a section of code to be assembled -if the condition for the preceding `.if' was false. + `.else' is part of the `as' support for conditional assembly; *note +`.if': If.. It marks the beginning of a section of code to be +assembled if the condition for the preceding `.if' was false.  File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops -7.26 `.elseif' -============== +`.elseif' +========= -`.elseif' is part of the `as' support for conditional assembly; *note -`.if': If. It is shorthand for beginning a new `.if' block that would -otherwise fill the entire `.else' section. + `.elseif' is part of the `as' support for conditional assembly; +*note `.if': If.. It is shorthand for beginning a new `.if' block that +would otherwise fill the entire `.else' section.  File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops -7.27 `.end' -=========== +`.end' +====== -`.end' marks the end of the assembly file. `as' does not process + `.end' marks the end of the assembly file. `as' does not process anything in the file past the `.end' directive.  File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops -7.28 `.endef' -============= +`.endef' +======== -This directive flags the end of a symbol definition begun with `.def'. + This directive flags the end of a symbol definition begun with +`.def'. `.endef' is only meaningful when generating COFF format output; if `as' is configured to generate `b.out', it accepts this directive but @@ -3107,39 +3115,39 @@  File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops -7.29 `.endfunc' -=============== +`.endfunc' +========== -`.endfunc' marks the end of a function specified with `.func'. + `.endfunc' marks the end of a function specified with `.func'.  File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops -7.30 `.endif' -============= +`.endif' +======== -`.endif' is part of the `as' support for conditional assembly; it marks -the end of a block of code that is only assembled conditionally. *Note -`.if': If. + `.endif' is part of the `as' support for conditional assembly; it +marks the end of a block of code that is only assembled conditionally. +*Note `.if': If.  File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops -7.31 `.equ SYMBOL, EXPRESSION' -============================== +`.equ SYMBOL, EXPRESSION' +========================= -This directive sets the value of SYMBOL to EXPRESSION. It is -synonymous with `.set'; *note `.set': Set. + This directive sets the value of SYMBOL to EXPRESSION. It is +synonymous with `.set'; *note `.set': Set.. The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'.  File: as.info, Node: Equiv, Next: Err, Prev: Equ, Up: Pseudo Ops -7.32 `.equiv SYMBOL, EXPRESSION' -================================ +`.equiv SYMBOL, EXPRESSION' +=========================== -The `.equiv' directive is like `.equ' and `.set', except that the + The `.equiv' directive is like `.equ' and `.set', except that the assembler will signal an error if SYMBOL is already defined. Note a symbol which has been referenced but not actually defined is considered to be undefined. @@ -3154,22 +3162,22 @@  File: as.info, Node: Err, Next: Error, Prev: Equiv, Up: Pseudo Ops -7.33 `.err' -=========== +`.err' +====== -If `as' assembles a `.err' directive, it will print an error message + If `as' assembles a `.err' directive, it will print an error message and, unless the `-Z' option was used, it will not generate an object file. This can be used to signal error an conditionally compiled code.  File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops -7.34 `.error "STRING"' -====================== +`.error "STRING"' +================= -Similarly to `.err', this directive emits an error, but you can specify -a string that will be emitted as the error message. If you don't -specify the message, it defaults to `".error directive invoked in + Similarly to `.err', this directive emits an error, but you can +specify a string that will be emitted as the error message. If you +don't specify the message, it defaults to `".error directive invoked in source file"'. *Note Error and Warning Messages: Errors. .error "This code has not been assembled and tested." @@ -3177,40 +3185,40 @@  File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops -7.35 `.exitm' -============= +`.exitm' +======== -Exit early from the current macro definition. *Note Macro::. + Exit early from the current macro definition. *Note Macro::.  File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops -7.36 `.extern' -============== +`.extern' +========= -`.extern' is accepted in the source program--for compatibility with + `.extern' is accepted in the source program--for compatibility with other assemblers--but it is ignored. `as' treats all undefined symbols as external.  File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops -7.37 `.fail EXPRESSION' -======================= +`.fail EXPRESSION' +================== -Generates an error or a warning. If the value of the EXPRESSION is 500 -or more, `as' will print a warning message. If the value is less than -500, `as' will print an error message. The message will include the -value of EXPRESSION. This can occasionally be useful inside complex -nested macros or conditional assembly. + Generates an error or a warning. If the value of the EXPRESSION is +500 or more, `as' will print a warning message. If the value is less +than 500, `as' will print an error message. The message will include +the value of EXPRESSION. This can occasionally be useful inside +complex nested macros or conditional assembly.  File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops -7.38 `.file STRING' -=================== +`.file STRING' +============== -`.file' tells `as' that we are about to start a new logical file. + `.file' tells `as' that we are about to start a new logical file. STRING is the new file name. In general, the filename is recognized whether or not it is surrounded by quotes `"'; but if you wish to specify an empty file name, you must give the quotes-`""'. This @@ -3222,10 +3230,10 @@  File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops -7.39 `.fill REPEAT , SIZE , VALUE' -================================== +`.fill REPEAT , SIZE , VALUE' +============================= -REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT + REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or more, but if it is more than 8, then it is deemed to have the value 8, compatible with other people's assemblers. The contents of each REPEAT @@ -3243,21 +3251,21 @@  File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops -7.40 `.float FLONUMS' -===================== +`.float FLONUMS' +================ -This directive assembles zero or more flonums, separated by commas. It -has the same effect as `.single'. The exact kind of floating point + This directive assembles zero or more flonums, separated by commas. +It has the same effect as `.single'. The exact kind of floating point numbers emitted depends on how `as' is configured. *Note Machine Dependencies::.  File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops -7.41 `.func NAME[,LABEL]' -========================= +`.func NAME[,LABEL]' +==================== -`.func' emits debugging information to denote function NAME, and is + `.func' emits debugging information to denote function NAME, and is ignored unless the file is assembled with debugging enabled. Only `--gstabs[+]' is currently supported. LABEL is the entry point of the function and if omitted NAME prepended with the `leading char' is used. @@ -3268,10 +3276,10 @@  File: as.info, Node: Global, Next: Hidden, Prev: Func, Up: Pseudo Ops -7.42 `.global SYMBOL', `.globl SYMBOL' -====================================== +`.global SYMBOL', `.globl SYMBOL' +================================= -`.global' makes the symbol visible to `ld'. If you define SYMBOL in + `.global' makes the symbol visible to `ld'. If you define SYMBOL in your partial program, its value is made available to other partial programs that are linked with it. Otherwise, SYMBOL takes its attributes from a symbol of the same name from another file linked into @@ -3287,10 +3295,10 @@  File: as.info, Node: Hidden, Next: hword, Prev: Global, Up: Pseudo Ops -7.43 `.hidden NAMES' -==================== +`.hidden NAMES' +=============== -This is one of the ELF visibility directives. The other two are + This is one of the ELF visibility directives. The other two are `.internal' (*note `.internal': Internal.) and `.protected' (*note `.protected': Protected.). @@ -3303,10 +3311,10 @@  File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops -7.44 `.hword EXPRESSIONS' -========================= +`.hword EXPRESSIONS' +==================== -This expects zero or more EXPRESSIONS, and emits a 16 bit number for + This expects zero or more EXPRESSIONS, and emits a 16 bit number for each. This directive is a synonym for `.short'; depending on the target @@ -3315,27 +3323,27 @@  File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops -7.45 `.ident' -============= +`.ident' +======== -This directive is used by some assemblers to place tags in object files. -`as' simply accepts the directive for source-file compatibility with -such assemblers, but does not actually emit anything for it. + This directive is used by some assemblers to place tags in object +files. `as' simply accepts the directive for source-file compatibility +with such assemblers, but does not actually emit anything for it.  File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops -7.46 `.if ABSOLUTE EXPRESSION' -============================== +`.if ABSOLUTE EXPRESSION' +========================= -`.if' marks the beginning of a section of code which is only considered -part of the source program being assembled if the argument (which must -be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional -section of code must be marked by `.endif' (*note `.endif': Endif.); -optionally, you may include code for the alternative condition, flagged -by `.else' (*note `.else': Else.). If you have several conditions to -check, `.elseif' may be used to avoid nesting blocks if/else within -each subsequent `.else' block. + `.if' marks the beginning of a section of code which is only +considered part of the source program being assembled if the argument +(which must be an ABSOLUTE EXPRESSION) is non-zero. The end of the +conditional section of code must be marked by `.endif' (*note `.endif': +Endif.); optionally, you may include code for the alternative +condition, flagged by `.else' (*note `.else': Else.). If you have +several conditions to check, `.elseif' may be used to avoid nesting +blocks if/else within each subsequent `.else' block. The following variants of `.if' are also supported: `.ifdef SYMBOL' @@ -3397,13 +3405,13 @@  File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops -7.47 `.incbin "FILE"[,SKIP[,COUNT]]' -==================================== +`.incbin "FILE"[,SKIP[,COUNT]]' +=============================== -The `incbin' directive includes FILE verbatim at the current location. -You can control the search paths used with the `-I' command-line option -(*note Command-Line Options: Invoking.). Quotation marks are required -around FILE. + The `incbin' directive includes FILE verbatim at the current +location. You can control the search paths used with the `-I' +command-line option (*note Command-Line Options: Invoking.). Quotation +marks are required around FILE. The SKIP argument skips a number of bytes from the start of the FILE. The COUNT argument indicates the maximum number of bytes to @@ -3414,24 +3422,24 @@  File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops -7.48 `.include "FILE"' -====================== +`.include "FILE"' +================= -This directive provides a way to include supporting files at specified -points in your source program. The code from FILE is assembled as if -it followed the point of the `.include'; when the end of the included -file is reached, assembly of the original file continues. You can -control the search paths used with the `-I' command-line option (*note -Command-Line Options: Invoking.). Quotation marks are required around -FILE. + This directive provides a way to include supporting files at +specified points in your source program. The code from FILE is +assembled as if it followed the point of the `.include'; when the end +of the included file is reached, assembly of the original file +continues. You can control the search paths used with the `-I' +command-line option (*note Command-Line Options: Invoking.). Quotation +marks are required around FILE.  File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops -7.49 `.int EXPRESSIONS' -======================= +`.int EXPRESSIONS' +================== -Expect zero or more EXPRESSIONS, of any section, separated by commas. + Expect zero or more EXPRESSIONS, of any section, separated by commas. For each expression, emit a number that, at run time, is the value of that expression. The byte order and bit size of the number depends on what kind of target the assembly is for. @@ -3439,10 +3447,10 @@  File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops -7.50 `.internal NAMES' -====================== +`.internal NAMES' +================= -This is one of the ELF visibility directives. The other two are + This is one of the ELF visibility directives. The other two are `.hidden' (*note `.hidden': Hidden.) and `.protected' (*note `.protected': Protected.). @@ -3456,13 +3464,13 @@  File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops -7.51 `.irp SYMBOL,VALUES'... -============================ +`.irp SYMBOL,VALUES'... +======================= -Evaluate a sequence of statements assigning different values to SYMBOL. -The sequence of statements starts at the `.irp' directive, and is -terminated by an `.endr' directive. For each VALUE, SYMBOL is set to -VALUE, and the sequence of statements is assembled. If no VALUE is + Evaluate a sequence of statements assigning different values to +SYMBOL. The sequence of statements starts at the `.irp' directive, and +is terminated by an `.endr' directive. For each VALUE, SYMBOL is set +to VALUE, and the sequence of statements is assembled. If no VALUE is listed, the sequence of statements is assembled once, with SYMBOL set to the null string. To refer to SYMBOL within the sequence of statements, use \SYMBOL. @@ -3482,12 +3490,12 @@  File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops -7.52 `.irpc SYMBOL,VALUES'... -============================= +`.irpc SYMBOL,VALUES'... +======================== -Evaluate a sequence of statements assigning different values to SYMBOL. -The sequence of statements starts at the `.irpc' directive, and is -terminated by an `.endr' directive. For each character in VALUE, + Evaluate a sequence of statements assigning different values to +SYMBOL. The sequence of statements starts at the `.irpc' directive, +and is terminated by an `.endr' directive. For each character in VALUE, SYMBOL is set to the character, and the sequence of statements is assembled. If no VALUE is listed, the sequence of statements is assembled once, with SYMBOL set to the null string. To refer to SYMBOL @@ -3508,10 +3516,10 @@  File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops -7.53 `.lcomm SYMBOL , LENGTH' -============================= +`.lcomm SYMBOL , LENGTH' +======================== -Reserve LENGTH (an absolute expression) bytes for a local common + Reserve LENGTH (an absolute expression) bytes for a local common denoted by SYMBOL. The section and value of SYMBOL are those of the new local common. The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed. SYMBOL is not declared @@ -3527,17 +3535,17 @@  File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops -7.54 `.lflags' -============== +`.lflags' +========= -`as' accepts this directive, for compatibility with other assemblers, -but ignores it. + `as' accepts this directive, for compatibility with other +assemblers, but ignores it.  File: as.info, Node: Line, Next: Ln, Prev: Lflags, Up: Pseudo Ops -7.55 `.line LINE-NUMBER' -======================== +`.line LINE-NUMBER' +=================== Change the logical line number. LINE-NUMBER must be an absolute expression. The next line has that logical line number. Therefore any @@ -3560,11 +3568,11 @@  File: as.info, Node: Linkonce, Next: List, Prev: Ln, Up: Pseudo Ops -7.56 `.linkonce [TYPE]' -======================= +`.linkonce [TYPE]' +================== -Mark the current section so that the linker only includes a single copy -of it. This may be used to include the same section in several + Mark the current section so that the linker only includes a single +copy of it. This may be used to include the same section in several different object files, but ensure that the linker will only include it once in the final output file. The `.linkonce' pseudo-op must be used for each instance of the section. Duplicate sections are detected @@ -3595,29 +3603,29 @@  File: as.info, Node: Ln, Next: Linkonce, Prev: Line, Up: Pseudo Ops -7.57 `.ln LINE-NUMBER' -====================== +`.ln LINE-NUMBER' +================= -`.ln' is a synonym for `.line'. + `.ln' is a synonym for `.line'.  File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops -7.58 `.mri VAL' -=============== +`.mri VAL' +========== -If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero, -this tells `as' to exit MRI mode. This change affects code assembled -until the next `.mri' directive, or until the end of the file. *Note -MRI mode: M. + If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is +zero, this tells `as' to exit MRI mode. This change affects code +assembled until the next `.mri' directive, or until the end of the +file. *Note MRI mode: M.  File: as.info, Node: List, Next: Long, Prev: Linkonce, Up: Pseudo Ops -7.59 `.list' -============ +`.list' +======= -Control (in conjunction with the `.nolist' directive) whether or not + Control (in conjunction with the `.nolist' directive) whether or not assembly listings are generated. These two directives maintain an internal counter (which is zero initially). `.list' increments the counter, and `.nolist' decrements it. Assembly listings are generated @@ -3630,18 +3638,18 @@  File: as.info, Node: Long, Next: Macro, Prev: List, Up: Pseudo Ops -7.60 `.long EXPRESSIONS' -======================== +`.long EXPRESSIONS' +=================== -`.long' is the same as `.int', *note `.int': Int. + `.long' is the same as `.int', *note `.int': Int..  File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops -7.61 `.macro' -============= +`.macro' +======== -The commands `.macro' and `.endm' allow you to define macros that + The commands `.macro' and `.endm' allow you to define macros that generate assembly output. For example, this definition specifies a macro `sum' that puts a sequence of numbers into memory: @@ -3714,10 +3722,10 @@  File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops -7.62 `.altmacro' -================ +`.altmacro' +=========== -Enable alternate macro mode, enabling: + Enable alternate macro mode, enabling: `LOCAL NAME [ , ... ]' One additional directive, `LOCAL', is available. It is used to @@ -3752,18 +3760,18 @@  File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops -7.63 `.noaltmacro' -================== +`.noaltmacro' +============= -Disable alternate macro mode. *Note Altmacro:: + Disable alternate macro mode. *Note Altmacro::  File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops -7.64 `.nolist' -============== +`.nolist' +========= -Control (in conjunction with the `.list' directive) whether or not + Control (in conjunction with the `.list' directive) whether or not assembly listings are generated. These two directives maintain an internal counter (which is zero initially). `.list' increments the counter, and `.nolist' decrements it. Assembly listings are generated @@ -3772,11 +3780,11 @@  File: as.info, Node: Octa, Next: Org, Prev: Nolist, Up: Pseudo Ops -7.65 `.octa BIGNUMS' -==================== +`.octa BIGNUMS' +=============== -This directive expects zero or more bignums, separated by commas. For -each bignum, it emits a 16-byte integer. + This directive expects zero or more bignums, separated by commas. +For each bignum, it emits a 16-byte integer. The term "octa" comes from contexts in which a "word" is two bytes; hence _octa_-word for 16 bytes. @@ -3784,14 +3792,14 @@  File: as.info, Node: Org, Next: P2align, Prev: Octa, Up: Pseudo Ops -7.66 `.org NEW-LC , FILL' -========================= +`.org NEW-LC , FILL' +==================== -Advance the location counter of the current section to NEW-LC. NEW-LC -is either an absolute expression or an expression with the same section -as the current subsection. That is, you can't use `.org' to cross -sections: if NEW-LC has the wrong section, the `.org' directive is -ignored. To be compatible with former assemblers, if the section of + Advance the location counter of the current section to NEW-LC. +NEW-LC is either an absolute expression or an expression with the same +section as the current subsection. That is, you can't use `.org' to +cross sections: if NEW-LC has the wrong section, the `.org' directive +is ignored. To be compatible with former assemblers, if the section of NEW-LC is absolute, `as' issues a warning, then pretends the section of NEW-LC is the same as the current subsection. @@ -3813,10 +3821,10 @@  File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops -7.67 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' -================================================ +`.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' +=========================================== -Pad the location counter (in the current subsection) to a particular + Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the number of low-order zero bits the location counter must have after advancement. For example `.p2align 3' advances the location counter @@ -3850,10 +3858,10 @@  File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops -7.68 `.previous' -================ +`.previous' +=========== -This is one of the ELF section stack manipulation directives. The + This is one of the ELF section stack manipulation directives. The others are `.section' (*note Section::), `.subsection' (*note SubSection::), `.pushsection' (*note PushSection::), and `.popsection' (*note PopSection::). @@ -3869,10 +3877,10 @@  File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops -7.69 `.popsection' -================== +`.popsection' +============= -This is one of the ELF section stack manipulation directives. The + This is one of the ELF section stack manipulation directives. The others are `.section' (*note Section::), `.subsection' (*note SubSection::), `.pushsection' (*note PushSection::), and `.previous' (*note Previous::). @@ -3884,19 +3892,19 @@  File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops -7.70 `.print STRING' -==================== +`.print STRING' +=============== -`as' will print STRING on the standard output during assembly. You + `as' will print STRING on the standard output during assembly. You must put STRING in double quotes.  File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops -7.71 `.protected NAMES' -======================= +`.protected NAMES' +================== -This is one of the ELF visibility directives. The other two are + This is one of the ELF visibility directives. The other two are `.hidden' (*note Hidden::) and `.internal' (*note Internal::). This directive overrides the named symbols default visibility (which @@ -3909,11 +3917,11 @@  File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops -7.72 `.psize LINES , COLUMNS' -============================= +`.psize LINES , COLUMNS' +======================== -Use this directive to declare the number of lines--and, optionally, the -number of columns--to use for each page, when generating listings. + Use this directive to declare the number of lines--and, optionally, +the number of columns--to use for each page, when generating listings. If you do not use `.psize', listings use a default line-count of 60. You may omit the comma and COLUMNS specification; the default width is @@ -3928,19 +3936,19 @@  File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops -7.73 `.purgem NAME' -=================== +`.purgem NAME' +============== -Undefine the macro NAME, so that later uses of the string will not be + Undefine the macro NAME, so that later uses of the string will not be expanded. *Note Macro::.  File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops -7.74 `.pushsection NAME , SUBSECTION' -===================================== +`.pushsection NAME , SUBSECTION' +================================ -This is one of the ELF section stack manipulation directives. The + This is one of the ELF section stack manipulation directives. The others are `.section' (*note Section::), `.subsection' (*note SubSection::), `.popsection' (*note PopSection::), and `.previous' (*note Previous::). @@ -3952,13 +3960,13 @@  File: as.info, Node: Quad, Next: Rept, Prev: PushSection, Up: Pseudo Ops -7.75 `.quad BIGNUMS' -==================== +`.quad BIGNUMS' +=============== -`.quad' expects zero or more bignums, separated by commas. For each + `.quad' expects zero or more bignums, separated by commas. For each bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes, it prints a warning message; and just takes the lowest order 8 -bytes of the bignum. +bytes of the bignum. The term "quad" comes from contexts in which a "word" is two bytes; hence _quad_-word for 8 bytes. @@ -3966,11 +3974,11 @@  File: as.info, Node: Rept, Next: Sbttl, Prev: Quad, Up: Pseudo Ops -7.76 `.rept COUNT' -================== +`.rept COUNT' +============= -Repeat the sequence of lines between the `.rept' directive and the next -`.endr' directive COUNT times. + Repeat the sequence of lines between the `.rept' directive and the +next `.endr' directive COUNT times. For example, assembling @@ -3987,10 +3995,10 @@  File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops -7.77 `.sbttl "SUBHEADING"' -========================== +`.sbttl "SUBHEADING"' +===================== -Use SUBHEADING as the title (third line, immediately after the title + Use SUBHEADING as the title (third line, immediately after the title line) when generating assembly listings. This directive affects subsequent pages, as well as the current page @@ -3999,10 +4007,10 @@  File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops -7.78 `.scl CLASS' -================= +`.scl CLASS' +============ -Set the storage-class value for a symbol. This directive may only be + Set the storage-class value for a symbol. This directive may only be used inside a `.def'/`.endef' pair. Storage class may flag whether a symbol is static or external, or it may record further symbolic debugging information. @@ -4014,10 +4022,10 @@  File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops -7.79 `.section NAME' -==================== +`.section NAME' +=============== -Use the `.section' directive to assemble the following code into a + Use the `.section' directive to assemble the following code into a section named NAME. This directive is only supported for targets that actually support @@ -4195,12 +4203,12 @@  File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops -7.80 `.set SYMBOL, EXPRESSION' -============================== +`.set SYMBOL, EXPRESSION' +========================= -Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and -type to conform to EXPRESSION. If SYMBOL was flagged as external, it -remains flagged (*note Symbol Attributes::). + Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value +and type to conform to EXPRESSION. If SYMBOL was flagged as external, +it remains flagged (*note Symbol Attributes::). You may `.set' a symbol many times in the same assembly. @@ -4212,10 +4220,10 @@  File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops -7.81 `.short EXPRESSIONS' -========================= +`.short EXPRESSIONS' +==================== -`.short' is normally the same as `.word'. *Note `.word': Word. + `.short' is normally the same as `.word'. *Note `.word': Word. In some configurations, however, `.short' and `.word' generate numbers of different lengths; *note Machine Dependencies::. @@ -4223,21 +4231,21 @@  File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops -7.82 `.single FLONUMS' -====================== +`.single FLONUMS' +================= -This directive assembles zero or more flonums, separated by commas. It -has the same effect as `.float'. The exact kind of floating point + This directive assembles zero or more flonums, separated by commas. +It has the same effect as `.float'. The exact kind of floating point numbers emitted depends on how `as' is configured. *Note Machine Dependencies::.  File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops -7.83 `.size' -============ +`.size' +======= -This directive is used to set the size associated with a symbol. + This directive is used to set the size associated with a symbol. COFF Version ------------ @@ -4265,30 +4273,30 @@  File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops -7.84 `.sleb128 EXPRESSIONS' -=========================== +`.sleb128 EXPRESSIONS' +====================== -SLEB128 stands for "signed little endian base 128." This is a compact, -variable length representation of numbers used by the DWARF symbolic -debugging format. *Note `.uleb128': Uleb128. + SLEB128 stands for "signed little endian base 128." This is a +compact, variable length representation of numbers used by the DWARF +symbolic debugging format. *Note `.uleb128': Uleb128.  File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops -7.85 `.skip SIZE , FILL' -======================== +`.skip SIZE , FILL' +=================== -This directive emits SIZE bytes, each of value FILL. Both SIZE and + This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL are absolute expressions. If the comma and FILL are omitted, FILL is assumed to be zero. This is the same as `.space'.  File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops -7.86 `.space SIZE , FILL' -========================= +`.space SIZE , FILL' +==================== -This directive emits SIZE bytes, each of value FILL. Both SIZE and + This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL are absolute expressions. If the comma and FILL are omitted, FILL is assumed to be zero. This is the same as `.skip'. @@ -4307,13 +4315,13 @@  File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops -7.87 `.stabd, .stabn, .stabs' -============================= +`.stabd, .stabn, .stabs' +======================== -There are three directives that begin `.stab'. All emit symbols (*note -Symbols::), for use by symbolic debuggers. The symbols are not entered -in the `as' hash table: they cannot be referenced elsewhere in the -source file. Up to five fields are required: + There are three directives that begin `.stab'. All emit symbols +(*note Symbols::), for use by symbolic debuggers. The symbols are not +entered in the `as' hash table: they cannot be referenced elsewhere in +the source file. Up to five fields are required: STRING This is the symbol's name. It may contain any character except @@ -4361,10 +4369,10 @@  File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops -7.88 `.string' "STR" -==================== +`.string' "STR" +=============== -Copy the characters in STR to the object file. You may specify more + Copy the characters in STR to the object file. You may specify more than one string to copy, separated by commas. Unless otherwise specified for a particular machine, the assembler marks the end of each string with a 0 byte. You can use any of the escape sequences @@ -4373,10 +4381,10 @@  File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops -7.89 `.struct EXPRESSION' -========================= +`.struct EXPRESSION' +==================== -Switch to the absolute section, and set the section offset to + Switch to the absolute section, and set the section offset to EXPRESSION, which must be an absolute expression. You might use this as follows: .struct 0 @@ -4394,10 +4402,10 @@  File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops -7.90 `.subsection NAME' -======================= +`.subsection NAME' +================== -This is one of the ELF section stack manipulation directives. The + This is one of the ELF section stack manipulation directives. The others are `.section' (*note Section::), `.pushsection' (*note PushSection::), `.popsection' (*note PopSection::), and `.previous' (*note Previous::). @@ -4409,10 +4417,10 @@  File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops -7.91 `.symver' -============== +`.symver' +========= -Use the `.symver' directive to bind symbols to specific version nodes + Use the `.symver' directive to bind symbols to specific version nodes within a source file. This is only supported on ELF platforms, and is typically used when assembling files to be linked into a shared library. There are cases where it may make sense to use this in objects to be @@ -4458,11 +4466,11 @@  File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops -7.92 `.tag STRUCTNAME' -====================== +`.tag STRUCTNAME' +================= -This directive is generated by compilers to include auxiliary debugging -information in the symbol table. It is only permitted inside + This directive is generated by compilers to include auxiliary +debugging information in the symbol table. It is only permitted inside `.def'/`.endef' pairs. Tags are used to link structure definitions in the symbol table with instances of those structures. @@ -4472,20 +4480,20 @@  File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops -7.93 `.text SUBSECTION' -======================= +`.text SUBSECTION' +================== -Tells `as' to assemble the following statements onto the end of the + Tells `as' to assemble the following statements onto the end of the text subsection numbered SUBSECTION, which is an absolute expression. If SUBSECTION is omitted, subsection number zero is used.  File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops -7.94 `.title "HEADING"' -======================= +`.title "HEADING"' +================== -Use HEADING as the title (second line, immediately after the source + Use HEADING as the title (second line, immediately after the source file name and pagenumber) when generating assembly listings. This directive affects subsequent pages, as well as the current page @@ -4494,10 +4502,10 @@  File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops -7.95 `.type' -============ +`.type' +======= -This directive is used to set the type of a symbol. + This directive is used to set the type of a symbol. COFF Version ------------ @@ -4527,36 +4535,36 @@ .type ,#function .type ,#object - + .type ,@function .type ,@object - + .type ,%function .type ,%object - + .type ,"function" .type ,"object" - + .type STT_FUNCTION .type STT_OBJECT  File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops -7.96 `.uleb128 EXPRESSIONS' -=========================== +`.uleb128 EXPRESSIONS' +====================== -ULEB128 stands for "unsigned little endian base 128." This is a + ULEB128 stands for "unsigned little endian base 128." This is a compact, variable length representation of numbers used by the DWARF symbolic debugging format. *Note `.sleb128': Sleb128.  File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops -7.97 `.val ADDR' -================ +`.val ADDR' +=========== -This directive, permitted only within `.def'/`.endef' pairs, records + This directive, permitted only within `.def'/`.endef' pairs, records the address ADDR as the value attribute of a symbol table entry. `.val' is used only for COFF output; when `as' is configured for @@ -4565,49 +4573,49 @@  File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops -7.98 `.version "STRING"' -======================== +`.version "STRING"' +=================== -This directive creates a `.note' section and places into it an ELF + This directive creates a `.note' section and places into it an ELF formatted note of type NT_VERSION. The note's name is set to `string'.  File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops -7.99 `.vtable_entry TABLE, OFFSET' -================================== +`.vtable_entry TABLE, OFFSET' +============================= -This directive finds or creates a symbol `table' and creates a + This directive finds or creates a symbol `table' and creates a `VTABLE_ENTRY' relocation for it with an addend of `offset'.  File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops -7.100 `.vtable_inherit CHILD, PARENT' -===================================== +`.vtable_inherit CHILD, PARENT' +=============================== -This directive finds the symbol `child' and finds or creates the symbol -`parent' and then creates a `VTABLE_INHERIT' relocation for the parent -whose addend is the value of the child symbol. As a special case the -parent name of `0' is treated as refering the `*ABS*' section. + This directive finds the symbol `child' and finds or creates the +symbol `parent' and then creates a `VTABLE_INHERIT' relocation for the +parent whose addend is the value of the child symbol. As a special +case the parent name of `0' is treated as refering the `*ABS*' section.  File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops -7.101 `.warning "STRING"' -========================= +`.warning "STRING"' +=================== -Similar to the directive `.error' (*note `.error "STRING"': Error.), + Similar to the directive `.error' (*note `.error "STRING"': Error.), but just emits a warning.  File: as.info, Node: Weak, Next: Word, Prev: Warning, Up: Pseudo Ops -7.102 `.weak NAMES' -=================== +`.weak NAMES' +============= -This directive sets the weak attribute on the comma separated list of -symbol `names'. If the symbols do not already exist, they will be + This directive sets the weak attribute on the comma separated list +of symbol `names'. If the symbols do not already exist, they will be created. On COFF targets other than PE, weak symbols are a GNU extension. @@ -4622,10 +4630,10 @@  File: as.info, Node: Word, Next: Deprecated, Prev: Weak, Up: Pseudo Ops -7.103 `.word EXPRESSIONS' -========================= +`.word EXPRESSIONS' +=================== -This directive expects zero or more EXPRESSIONS, of any section, + This directive expects zero or more EXPRESSIONS, of any section, separated by commas. The size of the number emitted, and its byte order, depend on what @@ -4662,10 +4670,10 @@  File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops -7.104 Deprecated Directives -=========================== +Deprecated Directives +===================== -One day these directives won't work. They are included for + One day these directives won't work. They are included for compatibility with older assemblers. .abort @@ -4674,10 +4682,10 @@  File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Pseudo Ops, Up: Top -8 Machine Dependent Features -**************************** +Machine Dependent Features +************************** -The machine instruction sets are (almost by definition) different on + The machine instruction sets are (almost by definition) different on each machine where `as' runs. Floating point representations vary as well, and `as' often supports a few additional directives or command-line options for compatibility with other assemblers on a @@ -4761,8 +4769,8 @@  File: as.info, Node: AMD29K-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies -8.1 AMD 29K Dependent Features -============================== +AMD 29K Dependent Features +========================== * Menu: @@ -4775,16 +4783,16 @@  File: as.info, Node: AMD29K Options, Next: AMD29K Syntax, Up: AMD29K-Dependent -8.1.1 Options -------------- +Options +------- -`as' has no additional command-line options for the AMD 29K family. + `as' has no additional command-line options for the AMD 29K family.  File: as.info, Node: AMD29K Syntax, Next: AMD29K Floating Point, Prev: AMD29K Options, Up: AMD29K-Dependent -8.1.2 Syntax ------------- +Syntax +------ * Menu: @@ -4795,20 +4803,20 @@  File: as.info, Node: AMD29K-Macros, Next: AMD29K-Chars, Up: AMD29K Syntax -8.1.2.1 Macros -.............. +Macros +...... -The macro syntax used on the AMD 29K is like that described in the AMD -29K Family Macro Assembler Specification. Normal `as' macros should -still work. + The macro syntax used on the AMD 29K is like that described in the +AMD 29K Family Macro Assembler Specification. Normal `as' macros +should still work.  File: as.info, Node: AMD29K-Chars, Next: AMD29K-Regs, Prev: AMD29K-Macros, Up: AMD29K Syntax -8.1.2.2 Special Characters -.......................... +Special Characters +.................. -`;' is the line comment character. + `;' is the line comment character. The character `?' is permitted in identifiers (but may not begin an identifier). @@ -4816,20 +4824,22 @@  File: as.info, Node: AMD29K-Regs, Prev: AMD29K-Chars, Up: AMD29K Syntax -8.1.2.3 Register Names -...................... +Register Names +.............. -General-purpose registers are represented by predefined symbols of the -form `GRNNN' (for global registers) or `LRNNN' (for local registers), -where NNN represents a number between `0' and `127', written with no -leading zeros. The leading letters may be in either upper or lower -case; for example, `gr13' and `LR7' are both valid register names. + General-purpose registers are represented by predefined symbols of +the form `GRNNN' (for global registers) or `LRNNN' (for local +registers), where NNN represents a number between `0' and `127', +written with no leading zeros. The leading letters may be in either +upper or lower case; for example, `gr13' and `LR7' are both valid +register names. You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with `%%' to flag the expression as a register number): %%EXPRESSION - --where EXPRESSION must be an absolute expression evaluating to a + +--where EXPRESSION must be an absolute expression evaluating to a number between `0' and `255'. The range [0, 127] refers to global registers, and the range [128, 255] to local registers. @@ -4851,16 +4861,16 @@  File: as.info, Node: AMD29K Floating Point, Next: AMD29K Directives, Prev: AMD29K Syntax, Up: AMD29K-Dependent -8.1.3 Floating Point --------------------- +Floating Point +-------------- -The AMD 29K family uses IEEE floating-point numbers. + The AMD 29K family uses IEEE floating-point numbers.  File: as.info, Node: AMD29K Directives, Next: AMD29K Opcodes, Prev: AMD29K Floating Point, Up: AMD29K-Dependent -8.1.4 AMD 29K Machine Directives --------------------------------- +AMD 29K Machine Directives +-------------------------- `.block SIZE , FILL' This directive emits SIZE bytes, each of value FILL. Both SIZE @@ -4900,10 +4910,10 @@  File: as.info, Node: AMD29K Opcodes, Prev: AMD29K Directives, Up: AMD29K-Dependent -8.1.5 Opcodes -------------- +Opcodes +------- -`as' implements all the standard AMD 29K opcodes. No additional + `as' implements all the standard AMD 29K opcodes. No additional pseudo-instructions are needed on this family. For information on the 29K machine instruction set, see `Am29000 @@ -4912,8 +4922,8 @@  File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AMD29K-Dependent, Up: Machine Dependencies -8.2 Alpha Dependent Features -============================ +Alpha Dependent Features +======================== * Menu: @@ -4927,18 +4937,18 @@  File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent -8.2.1 Notes ------------ +Notes +----- -The documentation here is primarily for the ELF object format. `as' + The documentation here is primarily for the ELF object format. `as' also supports the ECOFF and EVAX formats, but features specific to these formats are not yet documented.  File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent -8.2.2 Options -------------- +Options +------- `-mCPU' This option specifies the target processor. If an attempt is made @@ -4991,10 +5001,10 @@  File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent -8.2.3 Syntax ------------- +Syntax +------ -The assembler syntax closely follow the Alpha Reference Manual; + The assembler syntax closely follow the Alpha Reference Manual; assembler directives and general syntax closely follow the OSF/1 and OpenVMS syntax, with a few differences for ELF. @@ -5007,20 +5017,20 @@  File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax -8.2.3.1 Special Characters -.......................... +Special Characters +.................. -`#' is the line comment character. + `#' is the line comment character. `;' can be used instead of a newline to separate statements.  File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax -8.2.3.2 Register Names -...................... +Register Names +.............. -The 32 integer registers are referred to as `$N' or `$rN'. In + The 32 integer registers are referred to as `$N' or `$rN'. In addition, registers 15, 28, 29, and 30 may be referred to by the symbols `$fp', `$at', `$gp', and `$sp' respectively. @@ -5029,11 +5039,11 @@  File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax -8.2.3.3 Relocations -................... +Relocations +........... -Some of these relocations are available for ECOFF, but mostly only for -ELF. They are modeled after the relocation format introduced in + Some of these relocations are available for ECOFF, but mostly only +for ELF. They are modeled after the relocation format introduced in Digital Unix 4.0, but there are additions. The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the @@ -5186,18 +5196,18 @@  File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent -8.2.4 Floating Point --------------------- +Floating Point +-------------- -The Alpha family uses both IEEE and VAX floating-point numbers. + The Alpha family uses both IEEE and VAX floating-point numbers.  File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent -8.2.5 Alpha Assembler Directives --------------------------------- +Alpha Assembler Directives +-------------------------- -`as' for the Alpha supports many additional directives for + `as' for the Alpha supports many additional directives for compatibility with the native assembler. This section describes them only briefly. @@ -5327,18 +5337,18 @@  File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent -8.2.6 Opcodes -------------- +Opcodes +------- -For detailed information on the Alpha machine instruction set, see the -Alpha Architecture Handbook + For detailed information on the Alpha machine instruction set, see +the Alpha Architecture Handbook (ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf).  File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies -8.3 ARC Dependent Features -========================== +ARC Dependent Features +====================== * Menu: @@ -5351,8 +5361,8 @@  File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent -8.3.1 Options -------------- +Options +------- `-marc[5|6|7|8]' This option selects the core processor variant. Using `-marc' is @@ -5392,8 +5402,8 @@  File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent -8.3.2 Syntax ------------- +Syntax +------ * Menu: @@ -5403,36 +5413,36 @@  File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax -8.3.2.1 Special Characters -.......................... +Special Characters +.................. -*TODO* + *TODO*  File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax -8.3.2.2 Register Names -...................... +Register Names +.............. -*TODO* + *TODO*  File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Syntax, Up: ARC-Dependent -8.3.3 Floating Point --------------------- +Floating Point +-------------- -The ARC core does not currently have hardware floating point support. -Software floating point support is provided by `GCC' and uses IEEE -floating-point numbers. + The ARC core does not currently have hardware floating point +support. Software floating point support is provided by `GCC' and uses +IEEE floating-point numbers.  File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Point, Up: ARC-Dependent -8.3.4 ARC Machine Directives ----------------------------- +ARC Machine Directives +---------------------- -The ARC version of `as' supports the following additional machine + The ARC version of `as' supports the following additional machine directives: `.2byte EXPRESSIONS' @@ -5475,7 +5485,7 @@ example: .extCondCode is_busy,0x14 - + add.is_busy r1,r2,r3 bis_busy _main @@ -5607,17 +5617,17 @@  File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent -8.3.5 Opcodes -------------- +Opcodes +------- -For information on the ARC instruction set, see `ARC Programmers + For information on the ARC instruction set, see `ARC Programmers Reference Manual', ARC International (www.arc.com)  File: as.info, Node: ARM-Dependent, Next: CRIS-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies -8.4 ARM Dependent Features -========================== +ARM Dependent Features +====================== * Menu: @@ -5631,8 +5641,8 @@  File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent -8.4.1 Options -------------- +Options +------- `-mcpu=PROCESSOR[+EXTENSION...]' This option specifies the target processor. The assembler will @@ -5753,8 +5763,8 @@  File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent -8.4.2 Syntax ------------- +Syntax +------ * Menu: @@ -5764,12 +5774,12 @@  File: as.info, Node: ARM-Chars, Next: ARM-Regs, Up: ARM Syntax -8.4.2.1 Special Characters -.......................... +Special Characters +.................. -The presence of a `@' on a line indicates the start of a comment that -extends to the end of the current line. If a `#' appears as the first -character of a line, the whole line is treated as a comment. + The presence of a `@' on a line indicates the start of a comment +that extends to the end of the current line. If a `#' appears as the +first character of a line, the whole line is treated as a comment. The `;' character can be used instead of a newline to separate statements. @@ -5781,24 +5791,24 @@  File: as.info, Node: ARM-Regs, Prev: ARM-Chars, Up: ARM Syntax -8.4.2.2 Register Names -...................... +Register Names +.............. -*TODO* Explain about ARM register naming, and the predefined names. + *TODO* Explain about ARM register naming, and the predefined names.  File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent -8.4.3 Floating Point --------------------- +Floating Point +-------------- -The ARM family uses IEEE floating-point numbers. + The ARM family uses IEEE floating-point numbers.  File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent -8.4.4 ARM Machine Directives ----------------------------- +ARM Machine Directives +---------------------- `.align EXPRESSION [, EXPRESSION]' This is the generic .ALIGN directive. For the ARM however if the @@ -5958,10 +5968,10 @@  File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent -8.4.5 Opcodes -------------- +Opcodes +------- -`as' implements all the standard ARM opcodes. It also implements + `as' implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions. `NOP' @@ -6012,10 +6022,10 @@  File: as.info, Node: ARM Mapping Symbols, Prev: ARM Opcodes, Up: ARM-Dependent -8.4.6 Mapping Symbols ---------------------- +Mapping Symbols +--------------- -The ARM ELF specification requires that special symbols be inserted + The ARM ELF specification requires that special symbols be inserted into object files to mark certain features: `$a' @@ -6037,8 +6047,8 @@  File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies -8.5 CRIS Dependent Features -=========================== +CRIS Dependent Features +======================= * Menu: @@ -6050,10 +6060,10 @@  File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent -8.5.1 Command-line Options --------------------------- +Command-line Options +-------------------- -The CRIS version of `as' has these machine-dependent command-line + The CRIS version of `as' has these machine-dependent command-line options. The format of the generated object files can be either ELF or a.out, @@ -6123,11 +6133,11 @@  File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent -8.5.2 Instruction expansion ---------------------------- +Instruction expansion +--------------------- -`as' will silently choose an instruction that fits the operand size for -`[register+constant]' operands. For example, the offset `127' in + `as' will silently choose an instruction that fits the operand size +for `[register+constant]' operands. For example, the offset `127' in `move.d [r3+127],r4' fits in an instruction using a signed-byte offset. Similarly, `move.d [r2+32767],r1' will generate an instruction using a 16-bit offset. For symbolic expressions and constants that do not fit @@ -6149,11 +6159,11 @@  File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent -8.5.3 Symbols -------------- +Symbols +------- -Some symbols are defined by the assembler. They're intended to be used -in conditional assembly, for example: + Some symbols are defined by the assembler. They're intended to be +used in conditional assembly, for example: .if ..asm.arch.cris.v32 CODE FOR CRIS V32 .elseif ..asm.arch.cris.common_v10_v32 @@ -6187,10 +6197,10 @@  File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent -8.5.4 Syntax ------------- +Syntax +------ -There are different aspects of the CRIS assembly syntax. + There are different aspects of the CRIS assembly syntax. * Menu: @@ -6202,11 +6212,11 @@  File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax -8.5.4.1 Special Characters -.......................... +Special Characters +.................. -The character `#' is a line comment character. It starts a comment if -and only if it is placed at the beginning of a line. + The character `#' is a line comment character. It starts a comment +if and only if it is placed at the beginning of a line. A `;' character starts a comment anywhere on the line, causing all characters up to the end of the line to be ignored. @@ -6218,10 +6228,10 @@  File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax -8.5.4.2 Symbols in position-independent code -............................................ +Symbols in position-independent code +.................................... -When generating position-independent code (SVR4 PIC) for use in + When generating position-independent code (SVR4 PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol suffixes are used to specify what kind of run-time symbol lookup will be used, expressed in the object as different _relocation types_. @@ -6293,11 +6303,11 @@  File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax -8.5.4.3 Register names -...................... +Register names +.............. -A `$' character may always prefix a general or special register name in -an instruction operand but is mandatory when the option + A `$' character may always prefix a general or special register name +in an instruction operand but is mandatory when the option `--no-underscore' is specified or when the `.syntax register_prefix' directive is in effect (*note crisnous::). Register names are case-insensitive. @@ -6305,10 +6315,10 @@  File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax -8.5.4.4 Assembler Directives -............................ +Assembler Directives +.................... -There are a few CRIS-specific pseudo-directives in addition to the + There are a few CRIS-specific pseudo-directives in addition to the generic ones. *Note Pseudo Ops::. Constants emitted by pseudo-directives are in little-endian order for CRIS. There is no support for floating-point-specific directives for CRIS. @@ -6355,8 +6365,8 @@  File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies -8.6 D10V Dependent Features -=========================== +D10V Dependent Features +======================= * Menu: @@ -6368,10 +6378,11 @@  File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent -8.6.1 D10V Options ------------------- +D10V Options +------------ -The Mitsubishi D10V version of `as' has a few machine dependent options. + The Mitsubishi D10V version of `as' has a few machine dependent +options. `-O' The D10V can often execute two sub-instructions in parallel. When @@ -6395,10 +6406,10 @@  File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent -8.6.2 Syntax ------------- +Syntax +------ -The D10V syntax is based on the syntax in Mitsubishi's D10V + The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below. * Menu: @@ -6413,10 +6424,10 @@  File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax -8.6.2.1 Size Modifiers -...................... +Size Modifiers +.............. -The D10V version of `as' uses the instruction names in the D10V + The D10V version of `as' uses the instruction names in the D10V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? `as' @@ -6433,10 +6444,10 @@  File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax -8.6.2.2 Sub-Instructions -........................ +Sub-Instructions +................ -The D10V assembler takes as input a series of instructions, either + The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single @@ -6455,11 +6466,11 @@  File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax -8.6.2.3 Special Characters -.......................... +Special Characters +.................. -`;' and `#' are the line comment characters. Sub-instructions may be -executed in order, in reverse-order, or in parallel. Instructions + `;' and `#' are the line comment characters. Sub-instructions may +be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols: @@ -6503,11 +6514,11 @@  File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax -8.6.2.4 Register Names -...................... +Register Names +.............. -You can use the predefined symbols `r0' through `r15' to refer to the -D10V registers. You can also use `sp' as an alias for `r15'. The + You can use the predefined symbols `r0' through `r15' to refer to +the D10V registers. You can also use `sp' as an alias for `r15'. The accumulators are `a0' and `a1'. There are special register-pair names that may optionally be used in opcodes that require even-numbered registers. Register names are not case sensitive. @@ -6573,11 +6584,11 @@  File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax -8.6.2.5 Addressing Modes -........................ +Addressing Modes +................ -`as' understands the following addressing modes for the D10V. `RN' in -the following refers to any of the numbered registers, but _not_ the + `as' understands the following addressing modes for the D10V. `RN' +in the following refers to any of the numbered registers, but _not_ the control registers. `RN' Register direct @@ -6606,10 +6617,10 @@  File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax -8.6.2.6 @WORD Modifier -...................... +@WORD Modifier +.............. -Any symbol followed by `@word' will be replaced by the symbol's value + Any symbol followed by `@word' will be replaced by the symbol's value shifted right by 2. This is used in situations such as loading a register with the address of a function (or any other code fragment). For example, if you want to load a register with the location of the @@ -6620,21 +6631,21 @@  File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent -8.6.3 Floating Point --------------------- +Floating Point +-------------- -The D10V has no hardware floating point, but the `.float' and `.double' -directives generates IEEE floating-point numbers for compatibility with -other development tools. + The D10V has no hardware floating point, but the `.float' and +`.double' directives generates IEEE floating-point numbers for +compatibility with other development tools.  File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent -8.6.4 Opcodes -------------- +Opcodes +------- -For detailed information on the D10V machine instruction set, see `D10V -Architecture: A VLIW Microprocessor for Multimedia Applications' + For detailed information on the D10V machine instruction set, see +`D10V Architecture: A VLIW Microprocessor for Multimedia Applications' (Mitsubishi Electric Corp.). `as' implements all the standard D10V opcodes. The only changes are those described in the section on size modifiers @@ -6642,8 +6653,8 @@  File: as.info, Node: D30V-Dependent, Next: H8/300-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies -8.7 D30V Dependent Features -=========================== +D30V Dependent Features +======================= * Menu: @@ -6655,10 +6666,11 @@  File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent -8.7.1 D30V Options ------------------- +D30V Options +------------ -The Mitsubishi D30V version of `as' has a few machine dependent options. + The Mitsubishi D30V version of `as' has a few machine dependent +options. `-O' The D30V can often execute two sub-instructions in parallel. When @@ -6677,10 +6689,10 @@  File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent -8.7.2 Syntax ------------- +Syntax +------ -The D30V syntax is based on the syntax in Mitsubishi's D30V + The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below. * Menu: @@ -6695,10 +6707,10 @@  File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax -8.7.2.1 Size Modifiers -...................... +Size Modifiers +.............. -The D30V version of `as' uses the instruction names in the D30V + The D30V version of `as' uses the instruction names in the D30V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? `as' @@ -6715,10 +6727,10 @@  File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax -8.7.2.2 Sub-Instructions -........................ +Sub-Instructions +................ -The D30V assembler takes as input a series of instructions, either + The D30V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single @@ -6737,11 +6749,11 @@  File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax -8.7.2.3 Special Characters -.......................... +Special Characters +.................. -`;' and `#' are the line comment characters. Sub-instructions may be -executed in order, in reverse-order, or in parallel. Instructions + `;' and `#' are the line comment characters. Sub-instructions may +be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially unless you use the `-O' option. @@ -6802,12 +6814,12 @@  File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax -8.7.2.4 Guarded Execution -......................... +Guarded Execution +................. -`as' supports the full range of guarded execution directives for each -instruction. Just append the directive after the instruction proper. -The directives are: + `as' supports the full range of guarded execution directives for +each instruction. Just append the directive after the instruction +proper. The directives are: `/tx' Execute the instruction if flag f0 is true. @@ -6830,12 +6842,12 @@  File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax -8.7.2.5 Register Names -...................... +Register Names +.............. -You can use the predefined symbols `r0' through `r63' to refer to the -D30V registers. You can also use `sp' as an alias for `r63' and `link' -as an alias for `r62'. The accumulators are `a0' and `a1'. + You can use the predefined symbols `r0' through `r63' to refer to +the D30V registers. You can also use `sp' as an alias for `r63' and +`link' as an alias for `r62'. The accumulators are `a0' and `a1'. The D30V also has predefined symbols for these control registers and status bits: @@ -6911,11 +6923,11 @@  File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax -8.7.2.6 Addressing Modes -........................ +Addressing Modes +................ -`as' understands the following addressing modes for the D30V. `RN' in -the following refers to any of the numbered registers, but _not_ the + `as' understands the following addressing modes for the D30V. `RN' +in the following refers to any of the numbered registers, but _not_ the control registers. `RN' Register direct @@ -6944,21 +6956,21 @@  File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent -8.7.3 Floating Point --------------------- +Floating Point +-------------- -The D30V has no hardware floating point, but the `.float' and `.double' -directives generates IEEE floating-point numbers for compatibility with -other development tools. + The D30V has no hardware floating point, but the `.float' and +`.double' directives generates IEEE floating-point numbers for +compatibility with other development tools.  File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent -8.7.4 Opcodes -------------- +Opcodes +------- -For detailed information on the D30V machine instruction set, see `D30V -Architecture: A VLIW Microprocessor for Multimedia Applications' + For detailed information on the D30V machine instruction set, see +`D30V Architecture: A VLIW Microprocessor for Multimedia Applications' (Mitsubishi Electric Corp.). `as' implements all the standard D30V opcodes. The only changes are those described in the section on size modifiers @@ -6966,8 +6978,8 @@  File: as.info, Node: H8/300-Dependent, Next: H8/500-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies -8.8 H8/300 Dependent Features -============================= +H8/300 Dependent Features +========================= * Menu: @@ -6980,17 +6992,17 @@  File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent -8.8.1 Options -------------- +Options +------- -`as' has no additional command-line options for the Renesas (formerly -Hitachi) H8/300 family. + `as' has no additional command-line options for the Renesas +(formerly Hitachi) H8/300 family.  File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent -8.8.2 Syntax ------------- +Syntax +------ * Menu: @@ -7001,10 +7013,10 @@  File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax -8.8.2.1 Special Characters -.......................... +Special Characters +.................. -`;' is the line comment character. + `;' is the line comment character. `$' can be used instead of a newline to separate statements. Therefore _you may not use `$' in symbol names_ on the H8/300. @@ -7012,13 +7024,13 @@  File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax -8.8.2.2 Register Names -...................... +Register Names +.............. -You can use predefined symbols of the form `rNh' and `rNl' to refer to -the H8/300 registers as sixteen 8-bit general-purpose registers. N is -a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid -register names. + You can use predefined symbols of the form `rNh' and `rNl' to refer +to the H8/300 registers as sixteen 8-bit general-purpose registers. N +is a digit from `0' to `7'); for instance, both `r0h' and `r7l' are +valid register names. You can also use the eight predefined symbols `rN' to refer to the H8/300 registers as 16-bit registers (you must use this form for @@ -7035,10 +7047,10 @@  File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax -8.8.2.3 Addressing Modes -........................ +Addressing Modes +................ -as understands the following addressing modes for the H8/300: + as understands the following addressing modes for the H8/300: `rN' Register direct @@ -7080,20 +7092,20 @@  File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent -8.8.3 Floating Point --------------------- +Floating Point +-------------- -The H8/300 family has no hardware floating point, but the `.float' + The H8/300 family has no hardware floating point, but the `.float' directive generates IEEE floating-point numbers for compatibility with other development tools.  File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent -8.8.4 H8/300 Machine Directives -------------------------------- +H8/300 Machine Directives +------------------------- -`as' has the following machine-dependent directives for the H8/300: + `as' has the following machine-dependent directives for the H8/300: `.h8300h' Recognize and emit additional instructions for the H8/300H @@ -7121,10 +7133,10 @@  File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent -8.8.5 Opcodes -------------- +Opcodes +------- -For detailed information on the H8/300 machine instruction set, see + For detailed information on the H8/300 machine instruction set, see `H8/300 Series Programming Manual'. For information specific to the H8/300H, see `H8/300H Series Programming Manual' (Renesas). @@ -7141,7 +7153,7 @@ imm immediate data disp:N N-bit displacement from a register pcrel:N N-bit displacement relative to program counter - + add.b #imm,rd * andc #imm,ccr add.b rs,rd band #imm,rd add.w rs,rd band #imm,@rd @@ -7157,7 +7169,7 @@ * and.w #imm,rd bhi pcrel:8 * and.l #imm,rd * bhi pcrel:16 * and.l rs,rd bls pcrel:8 - + * bls pcrel:16 bld #imm,rd bcc pcrel:8 bld #imm,@rd * bcc pcrel:16 bld #imm,@abs:8 @@ -7208,7 +7220,7 @@ bixor #imm,rd * divxs.w rs,rd bixor #imm,@rd eepmov bixor #imm,@abs:8 * eepmovw - + * exts.w rd mov.w rs,@abs:16 * exts.l rd * mov.l #imm,rd * extu.w rd * mov.l rs,rd @@ -7259,7 +7271,7 @@ mov.w @abs:16,rd * rotxl.l rs mov.w rs,@(disp:16,rd) rotxr.b rs mov.w rs,@-rd * rotxr.w rs - + * rotxr.l rs * stc ccr,@(disp:24,rd) bpt * stc ccr,@-rd rte * stc ccr,@abs:16 @@ -7298,8 +7310,8 @@  File: as.info, Node: H8/500-Dependent, Next: HPPA-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies -8.9 H8/500 Dependent Features -============================= +H8/500 Dependent Features +========================= * Menu: @@ -7312,17 +7324,17 @@  File: as.info, Node: H8/500 Options, Next: H8/500 Syntax, Up: H8/500-Dependent -8.9.1 Options -------------- +Options +------- -`as' has no additional command-line options for the Renesas (formerly -Hitachi) H8/500 family. + `as' has no additional command-line options for the Renesas +(formerly Hitachi) H8/500 family.  File: as.info, Node: H8/500 Syntax, Next: H8/500 Floating Point, Prev: H8/500 Options, Up: H8/500-Dependent -8.9.2 Syntax ------------- +Syntax +------ * Menu: @@ -7333,10 +7345,10 @@  File: as.info, Node: H8/500-Chars, Next: H8/500-Regs, Up: H8/500 Syntax -8.9.2.1 Special Characters -.......................... +Special Characters +.................. -`!' is the line comment character. + `!' is the line comment character. `;' can be used instead of a newline to separate statements. @@ -7345,11 +7357,11 @@  File: as.info, Node: H8/500-Regs, Next: H8/500-Addressing, Prev: H8/500-Chars, Up: H8/500 Syntax -8.9.2.2 Register Names -...................... +Register Names +.............. -You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', -`r6', and `r7' to refer to the H8/500 registers. + You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', +`r5', `r6', and `r7' to refer to the H8/500 registers. The H8/500 also has these control registers: @@ -7382,10 +7394,10 @@  File: as.info, Node: H8/500-Addressing, Prev: H8/500-Regs, Up: H8/500 Syntax -8.9.2.3 Addressing Modes -........................ +Addressing Modes +................ -as understands the following addressing modes for the H8/500: + as understands the following addressing modes for the H8/500: `RN' Register direct @@ -7419,29 +7431,30 @@  File: as.info, Node: H8/500 Floating Point, Next: H8/500 Directives, Prev: H8/500 Syntax, Up: H8/500-Dependent -8.9.3 Floating Point --------------------- +Floating Point +-------------- -The H8/500 family has no hardware floating point, but the `.float' + The H8/500 family has no hardware floating point, but the `.float' directive generates IEEE floating-point numbers for compatibility with other development tools.  File: as.info, Node: H8/500 Directives, Next: H8/500 Opcodes, Prev: H8/500 Floating Point, Up: H8/500-Dependent -8.9.4 H8/500 Machine Directives -------------------------------- +H8/500 Machine Directives +------------------------- -`as' has no machine-dependent directives for the H8/500. However, on -this platform the `.int' and `.word' directives generate 16-bit numbers. + `as' has no machine-dependent directives for the H8/500. However, +on this platform the `.int' and `.word' directives generate 16-bit +numbers.  File: as.info, Node: H8/500 Opcodes, Prev: H8/500 Directives, Up: H8/500-Dependent -8.9.5 Opcodes -------------- +Opcodes +------- -For detailed information on the H8/500 machine instruction set, see + For detailed information on the H8/500 machine instruction set, see `H8/500 Series Programming Manual' (Renesas M21T001). `as' implements all the standard H8/500 opcodes. No additional @@ -7476,7 +7489,7 @@ sp stack pointer (`r7') sr status register sz size; `.b' or `.w'. If omitted, default `.w' - + ldc[.b] ea,crb bcc[.w] pcrel16 ldc[.w] ea,sr bcc[.b] pcrel8 add[:q] sz qim,ea_noimm bhs[.w] pcrel16 @@ -7499,7 +7512,7 @@ bhi[.b] pcrel8 bmi[.b] pcrel8 bls[.w] pcrel16 bge[.w] pcrel16 bls[.b] pcrel8 bge[.b] pcrel8 - + blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem bgt[.w] pcrel16 movfpe[.b] ea,rd @@ -7554,8 +7567,8 @@  File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/500-Dependent, Up: Machine Dependencies -8.10 HPPA Dependent Features -============================ +HPPA Dependent Features +======================= * Menu: @@ -7569,11 +7582,11 @@  File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent -8.10.1 Notes ------------- +Notes +----- -As a back end for GNU CC `as' has been throughly tested and should work -extremely well. We have tested it only minimally on hand written + As a back end for GNU CC `as' has been throughly tested and should +work extremely well. We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers. @@ -7589,20 +7602,21 @@  File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent -8.10.2 Options --------------- +Options +------- -`as' has no machine-dependent command-line options for the HPPA. + `as' has no machine-dependent command-line options for the HPPA.  File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent -8.10.3 Syntax -------------- +Syntax +------ -The assembler syntax closely follows the HPPA instruction set reference -manual; assembler directives and general syntax closely follow the HPPA -assembly language reference manual, with a few noteworthy differences. + The assembler syntax closely follows the HPPA instruction set +reference manual; assembler directives and general syntax closely +follow the HPPA assembly language reference manual, with a few +noteworthy differences. First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers @@ -7631,21 +7645,22 @@  File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent -8.10.4 Floating Point ---------------------- +Floating Point +-------------- -The HPPA family uses IEEE floating-point numbers. + The HPPA family uses IEEE floating-point numbers.  File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent -8.10.5 HPPA Assembler Directives --------------------------------- +HPPA Assembler Directives +------------------------- -`as' for the HPPA supports many additional directives for compatibility -with the native assembler. This section describes them only briefly. -For detailed information on HPPA-specific assembler directives, see -`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). + `as' for the HPPA supports many additional directives for +compatibility with the native assembler. This section describes them +only briefly. For detailed information on HPPA-specific assembler +directives, see `HP9000 Series 800 Assembly Language Reference Manual' +(HP 92432-90001). `as' does _not_ support the following assembler directives described in the HP manual: @@ -7798,69 +7813,31 @@ `access=EXPR' (value for "access rights" field), `sort=EXPR' (sorting order for this subspace in link), `code_only' (subsection contains only code), `unloadable' (subsection cannot be loaded - into memory), `comdat' (subsection is comdat), `common' - (subsection is common block), `dup_comm' (subsection may have - duplicate names), or `zero' (subsection is all zeros, do not write - in object file). + into memory), `common' (subsection is common block), `dup_comm' + (initialized data may have duplicate names), or `zero' (subsection + is all zeros, do not write in object file). `.nsubspa' always creates a new subspace with the given name, even if one with the same name already exists. - `comdat', `common' and `dup_comm' can be used to implement various - flavors of one-only support when using the SOM linker. The SOM - linker only supports specific combinations of these flags. The - details are not documented. A brief description is provided here. - - `comdat' provides a form of linkonce support. It is useful for - both code and data subspaces. A `comdat' subspace has a key symbol - marked by the `is_comdat' flag or `ST_COMDAT'. Only the first - subspace for any given key is selected. The key symbol becomes - universal in shared links. This is similar to the behavior of - `secondary_def' symbols. - - `common' provides Fortran named common support. It is only useful - for data subspaces. Symbols with the flag `is_common' retain this - flag in shared links. Referencing a `is_common' symbol in a shared - library from outside the library doesn't work. Thus, `is_common' - symbols must be output whenever they are needed. - - `common' and `dup_comm' together provide Cobol common support. - The subspaces in this case must all be the same length. - Otherwise, this support is similar to the Fortran common support. - - `dup_comm' by itself provides a type of one-only support for code. - Only the first `dup_comm' subspace is selected. There is a rather - complex algorithm to compare subspaces. Code symbols marked with - the `dup_common' flag are hidden. This support was intended for - "C++ duplicate inlines". - - A simplified technique is used to mark the flags of symbols based - on the flags of their subspace. A symbol with the scope - SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with - the corresponding settings of `comdat', `common' and `dup_comm' - from the subspace, respectively. This avoids having to introduce - additional directives to mark these symbols. The HP assembler - sets `is_common' from `common'. However, it doesn't set the - `dup_common' from `dup_comm'. It doesn't have `comdat' support. - `.version "STR"' Write STR as version identifier in object code.  File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent -8.10.6 Opcodes --------------- +Opcodes +------- -For detailed information on the HPPA machine instruction set, see + For detailed information on the HPPA machine instruction set, see `PA-RISC Architecture and Instruction Set Reference Manual' (HP 09740-90039).  File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies -8.11 ESA/390 Dependent Features -=============================== +ESA/390 Dependent Features +========================== * Menu: @@ -7874,10 +7851,10 @@  File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent -8.11.1 Notes ------------- +Notes +----- -The ESA/390 `as' port is currently intended to be a back-end for the + The ESA/390 `as' port is currently intended to be a back-end for the GNU CC compiler. It is not HLASM compatible, although it does support a subset of some of the HLASM directives. The only supported binary file format is ELF; none of the usual MVS/VM/OE/USS object file @@ -7893,18 +7870,18 @@  File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent -8.11.2 Options --------------- +Options +------- -`as' has no machine-dependent command-line options for the ESA/390. + `as' has no machine-dependent command-line options for the ESA/390.  File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent -8.11.3 Syntax -------------- +Syntax +------ -The opcode/operand syntax follows the ESA/390 Principles of Operation + The opcode/operand syntax follows the ESA/390 Principles of Operation manual; assembler directives and general syntax are loosely based on the prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives are _not_ supported for the most part, with the exception of those @@ -7957,19 +7934,19 @@  File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent -8.11.4 Floating Point ---------------------- +Floating Point +-------------- -The assembler generates only IEEE floating-point numbers. The older + The assembler generates only IEEE floating-point numbers. The older floating point formats are not supported.  File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent -8.11.5 ESA/390 Assembler Directives ------------------------------------ +ESA/390 Assembler Directives +---------------------------- -`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler + `as' for the ESA/390 supports all of the standard ELF/SVR4 assembler directives that are documented in the main part of this documentation. Several additional directives are supported in order to implement the ESA/390 addressing model. The most important of these are `.using' and @@ -8050,17 +8027,17 @@  File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent -8.11.6 Opcodes --------------- +Opcodes +------- -For detailed information on the ESA/390 machine instruction set, see + For detailed information on the ESA/390 machine instruction set, see `ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).  File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies -8.12 80386 Dependent Features -============================= +80386 Dependent Features +======================== The i386 version `as' supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 @@ -8085,10 +8062,10 @@  File: as.info, Node: i386-Options, Next: i386-Syntax, Up: i386-Dependent -8.12.1 Options --------------- +Options +------- -The i386 version of `as' has a few machine dependent options: + The i386 version of `as' has a few machine dependent options: `--32 | --64' Select the word size, either 32 bits or 64 bits. Selecting 32-bit @@ -8109,10 +8086,10 @@  File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Options, Up: i386-Dependent -8.12.2 AT&T Syntax versus Intel Syntax --------------------------------------- +AT&T Syntax versus Intel Syntax +------------------------------- -`as' now supports assembly using Intel assembler syntax. + `as' now supports assembly using Intel assembler syntax. `.intel_syntax' selects Intel mode, and `.att_syntax' switches back to the usual AT&T mode for compatibility with the output of `gcc'. Either of these directives may have an optional argument, `prefix', or @@ -8157,10 +8134,10 @@  File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent -8.12.3 Instruction Naming -------------------------- +Instruction Naming +------------------ -Instruction mnemonics are suffixed with one character modifiers which + Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters `b', `w', `l' and `q' specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then `as' tries to fill in the missing @@ -8211,10 +8188,10 @@  File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent -8.12.4 Register Naming ----------------------- +Register Naming +--------------- -Register operands are always prefixed with `%'. The 80386 registers + Register operands are always prefixed with `%'. The 80386 registers consist of * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', @@ -8270,16 +8247,16 @@  File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent -8.12.5 Instruction Prefixes ---------------------------- +Instruction Prefixes +-------------------- -Instruction prefixes are used to modify the following instruction. They -are used to repeat string instructions, to provide section overrides, to -perform bus lock operations, and to change operand and address sizes. -(Most instructions that normally operate on 32-bit operands will use -16-bit operands if the instruction has an "operand size" prefix.) -Instruction prefixes are best written on the same line as the -instruction they act upon. For example, the `scas' (scan string) + Instruction prefixes are used to modify the following instruction. +They are used to repeat string instructions, to provide section +overrides, to perform bus lock operations, and to change operand and +address sizes. (Most instructions that normally operate on 32-bit +operands will use 16-bit operands if the instruction has an "operand +size" prefix.) Instruction prefixes are best written on the same line +as the instruction they act upon. For example, the `scas' (scan string) instruction is repeated with: repne scas %es:(%edi),%al @@ -8313,7 +8290,7 @@ * The `rep', `repe', and `repne' prefixes are added to string instructions to make them repeat `%ecx' times (`%cx' times if the - current address size is 16-bits). + current address size is 16-bits). * The `rex' family of prefixes is used by x86-64 to encode extensions to i386 instruction set. The `rex' prefix has four @@ -8331,10 +8308,10 @@  File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent -8.12.6 Memory References ------------------------- +Memory References +----------------- -An Intel syntax indirect memory reference of the form + An Intel syntax indirect memory reference of the form SECTION:[BASE + INDEX*SCALE + DISP] @@ -8401,10 +8378,10 @@  File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent -8.12.7 Handling of Jump Instructions ------------------------------------- +Handling of Jump Instructions +----------------------------- -Jump instructions are always optimized to use the smallest possible + Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word @@ -8424,3 +8401,9030 @@ cx_zero: jmp foo cx_nonzero: + +File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent + +Floating Point +-------------- + + All 80387 floating point types except packed BCD are supported. +(BCD support may be added without much difficulty). These data types +are 16-, 32-, and 64- bit integers, and single (32-bit), double +(64-bit), and extended (80-bit) precision floating point. Each +supported type has an instruction mnemonic suffix and a constructor +associated with it. Instruction mnemonic suffixes specify the operand's +data type. Constructors build these data types into memory. + + * Floating point constructors are `.float' or `.single', `.double', + and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond + to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for + 80-bit (ten byte) real. The 80387 only supports this format via + the `fldt' (load 80-bit real to stack top) and `fstpt' (store + 80-bit real and pop stack) instructions. + + * Integer constructors are `.word', `.long' or `.int', and `.quad' + for the 16-, 32-, and 64-bit integer formats. The corresponding + instruction mnemonic suffixes are `s' (single), `l' (long), and + `q' (quad). As with the 80-bit real format, the 64-bit `q' format + is only present in the `fildq' (load quad integer to stack top) + and `fistpq' (store quad integer and pop stack) instructions. + + Register to register operations should not use instruction mnemonic +suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as +if you wrote `fst %st, %st(1)', since all register to register +operations use 80-bit floating point operands. (Contrast this with +`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating +point format, then stores the result in the 4 byte location `mem') + + +File: as.info, Node: i386-SIMD, Next: i386-16bit, Prev: i386-Float, Up: i386-Dependent + +Intel's MMX and AMD's 3DNow! SIMD Operations +-------------------------------------------- + + `as' supports Intel's MMX instruction set (SIMD instructions for +integer data), available on Intel's Pentium MMX processors and Pentium +II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and +probably others. It also supports AMD's 3DNow! instruction set (SIMD +instructions for 32-bit floating point data) available on AMD's K6-2 +processor and possibly others in the future. + + Currently, `as' does not support Intel's floating point SIMD, Katmai +(KNI). + + The eight 64-bit MMX operands, also used by 3DNow!, are called +`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four +16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit +floating point values. The MMX registers cannot be used at the same +time as the floating point stack. + + See Intel and AMD documentation, keeping in mind that the operand +order in instructions is reversed from the Intel syntax. + + +File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-SIMD, Up: i386-Dependent + +Writing 16-bit Code +------------------- + + While `as' normally writes only "pure" 32-bit i386 code or 64-bit +x86-64 code depending on the default configuration, it also supports +writing code to run in real mode or in 16-bit protected mode code +segments. To do this, put a `.code16' or `.code16gcc' directive before +the assembly language instructions to be run in 16-bit mode. You can +switch `as' back to writing normal 32-bit code with the `.code32' +directive. + + `.code16gcc' provides experimental support for generating 16-bit +code from gcc, and differs from `.code16' in that `call', `ret', +`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' +instructions default to 32-bit size. This is so that the stack pointer +is manipulated in the same way over function calls, allowing access to +function parameters at the same stack offsets as in 32-bit mode. +`.code16gcc' also automatically adds address size prefixes where +necessary to use the 32-bit addressing modes that gcc generates. + + The code which `as' generates in 16-bit mode will not necessarily +run on a 16-bit pre-80386 processor. To write code that runs on such a +processor, you must refrain from using _any_ 32-bit constructs which +require `as' to output address or operand size prefixes. + + Note that writing 16-bit code instructions by explicitly specifying a +prefix or an instruction mnemonic suffix within a 32-bit code section +generates different machine instructions than those generated for a +16-bit code segment. In a 32-bit code section, the following code +generates the machine opcode bytes `66 6a 04', which pushes the value +`4' onto the stack, decrementing `%esp' by 2. + + pushw $4 + + The same code in a 16-bit code section would generate the machine +opcode bytes `6a 04' (ie. without the operand size prefix), which is +correct since the processor default operand size is assumed to be 16 +bits in a 16-bit code section. + + +File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent + +AT&T Syntax bugs +---------------- + + The UnixWare assembler, and probably other AT&T derived ix86 Unix +assemblers, generate floating point instructions with reversed source +and destination registers in certain cases. Unfortunately, gcc and +possibly many other programs use this reversed syntax, so we're stuck +with it. + + For example + + fsub %st,%st(3) + +results in `%st(3)' being updated to `%st - %st(3)' rather than the +expected `%st(3) - %st'. This happens with all the non-commutative +arithmetic floating point operations with two register operands where +the source register is `%st' and the destination register is `%st(i)'. + + +File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent + +Specifying CPU Architecture +--------------------------- + + `as' may be told to assemble for a particular CPU (sub-)architecture +with the `.arch CPU_TYPE' directive. This directive enables a warning +when gas detects an instruction that is not supported on the CPU +specified. The choices for CPU_TYPE are: + +`i8086' `i186' `i286' `i386' +`i486' `i586' `i686' `pentium' +`pentiumpro' `pentiumii' `pentiumiii' `pentium4' +`k6' `athlon' + `sledgehammer' +`.mmx' `.sse' +`.sse2' +`.3dnow' + + Apart from the warning, there are only two other effects on `as' +operation; Firstly, if you specify a CPU other than `i486', then shift +by one instructions such as `sarl $1, %eax' will automatically use a +two byte opcode sequence. The larger three byte opcode sequence is +used on the 486 (and when no architecture is specified) because it +executes faster on the 486. Note that you can explicitly request the +two byte opcode by writing `sarl %eax'. Secondly, if you specify +`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte +offset conditional jumps will be promoted when necessary to a two +instruction sequence consisting of a conditional jump of the opposite +sense around an unconditional jump to the target. + + Following the CPU architecture (but not a sub-architecture, which +are those starting with a dot), you may specify `jumps' or `nojumps' to +control automatic promotion of conditional jumps. `jumps' is the +default, and enables jump promotion; All external jumps will be of the +long variety, and file-local jumps will be promoted as necessary. +(*note i386-Jumps::) `nojumps' leaves external conditional jumps as +byte offset jumps, and warns about file-local conditional jumps that +`as' promotes. Unconditional jumps are treated as for `jumps'. + + For example + + .arch i8086,nojumps + + +File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent + +Notes +----- + + There is some trickery concerning the `mul' and `imul' instructions +that deserves mention. The 16-, 32-, 64- and 128-bit expanding +multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') +can be output only in the one operand form. Thus, `imul %ebx, %eax' +does _not_ select the expanding multiply; the expanding multiply would +clobber the `%edx' register, and this would confuse `gcc' output. Use +`imul %ebx' to get the 64-bit product in `%edx:%eax'. + + We have added a two operand form of `imul' when the first operand is +an immediate mode expression and the second operand is a register. +This is just a shorthand, so that, multiplying `%eax' by 69, for +example, can be done with `imul $69, %eax' rather than `imul $69, %eax, +%eax'. + + +File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies + +Intel i860 Dependent Features +============================= + +* Menu: + +* Notes-i860:: i860 Notes +* Options-i860:: i860 Command-line Options +* Directives-i860:: i860 Machine Directives +* Opcodes for i860:: i860 Opcodes + + +File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent + +i860 Notes +---------- + + This is a fairly complete i860 assembler which is compatible with the +UNIX System V/860 Release 4 assembler. However, it does not currently +support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT'). + + Like the SVR4/860 assembler, the output object format is ELF32. +Currently, this is the only supported object format. If there is +sufficient interest, other formats such as COFF may be implemented. + + Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter +being the default. One difference is that AT&T syntax requires the '%' +prefix on register names while Intel syntax does not. Another +difference is in the specification of relocatable expressions. The +Intel syntax is `ha%expression' whereas the SVR4 syntax is +`[expression]@ha' (and similarly for the "l" and "h" selectors). + + +File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent + +i860 Command-line Options +------------------------- + +SVR4 compatibility options +.......................... + +`-V' + Print assembler version. + +`-Qy' + Ignored. + +`-Qn' + Ignored. + +Other options +............. + +`-EL' + Select little endian output (this is the default). + +`-EB' + Select big endian output. Note that the i860 always reads + instructions as little endian data, so this option only effects + data and not instructions. + +`-mwarn-expand' + Emit a warning message if any pseudo-instruction expansions + occurred. For example, a `or' instruction with an immediate + larger than 16-bits will be expanded into two instructions. This + is a very undesirable feature to rely on, so this flag can help + detect any code where it happens. One use of it, for instance, has + been to find and eliminate any place where `gcc' may emit these + pseudo-instructions. + +`-mxp' + Enable support for the i860XP instructions and control registers. + By default, this option is disabled so that only the base + instruction set (i.e., i860XR) is supported. + +`-mintel-syntax' + The i860 assembler defaults to AT&T/SVR4 syntax. This option + enables the Intel syntax. + + +File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent + +i860 Machine Directives +----------------------- + +`.dual' + Enter dual instruction mode. While this directive is supported, the + preferred way to use dual instruction mode is to explicitly code + the dual bit with the `d.' prefix. + +`.enddual' + Exit dual instruction mode. While this directive is supported, the + preferred way to use dual instruction mode is to explicitly code + the dual bit with the `d.' prefix. + +`.atmp' + Change the temporary register used when expanding pseudo + operations. The default register is `r31'. + + The `.dual', `.enddual', and `.atmp' directives are available only +in the Intel syntax mode. + + Both syntaxes allow for the standard `.align' directive. However, +the Intel syntax additionally allows keywords for the alignment +parameter: "`.align type'", where `type' is one of `.short', `.long', +`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4, +and 8, respectively. + + +File: as.info, Node: Opcodes for i860, Prev: Directives-i860, Up: i860-Dependent + +i860 Opcodes +------------ + + All of the Intel i860XR and i860XP machine instructions are +supported. Please see either _i860 Microprocessor Programmer's +Reference Manual_ or _i860 Microprocessor Architecture_ for more +information. + +Other instruction support (pseudo-instructions) +............................................... + + For compatibility with some other i860 assemblers, a number of +pseudo-instructions are supported. While these are supported, they are +a very undesirable feature that should be avoided - in particular, when +they result in an expansion to multiple actual i860 instructions. Below +are the pseudo-instructions that result in expansions. + * Load large immediate into general register: + + The pseudo-instruction `mov imm,%rn' (where the immediate does not + fit within a signed 16-bit field) will be expanded into: + orh large_imm@h,%r0,%rn + or large_imm@l,%rn,%rn + + * Load/store with relocatable address expression: + + For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will + be expanded into: + orh addr_exp@ha,%rx,%r31 + ld.l addr_exp@l(%r31),%rn + + The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, + fst.x', and `pst.x' as well. + + * Signed large immediate with add/subtract: + + If any of the arithmetic operations `adds, addu, subs, subu' are + used with an immediate larger than 16-bits (signed), then they + will be expanded. For instance, the pseudo-instruction `adds + large_imm,%rx,%rn' expands to: + orh large_imm@h,%r0,%r31 + or large_imm@l,%r31,%r31 + adds %r31,%rx,%rn + + * Unsigned large immediate with logical operations: + + Logical operations (`or, andnot, or, xor') also result in + expansions. The pseudo-instruction `or large_imm,%rx,%rn' results + in: + orh large_imm@h,%rx,%r31 + or large_imm@l,%r31,%rn + + Similarly for the others, except for `and' which expands to: + andnot (-1 - large_imm)@h,%rx,%r31 + andnot (-1 - large_imm)@l,%r31,%rn + + +File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies + +Intel 80960 Dependent Features +============================== + +* Menu: + +* Options-i960:: i960 Command-line Options +* Floating Point-i960:: Floating Point +* Directives-i960:: i960 Machine Directives +* Opcodes for i960:: i960 Opcodes + + +File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent + +i960 Command-line Options +------------------------- + +`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' + Select the 80960 architecture. Instructions or features not + supported by the selected architecture cause fatal errors. + + `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. + Synonyms are provided for compatibility with other tools. + + If you do not specify any of these options, `as' generates code + for any instruction or feature that is supported by _some_ version + of the 960 (even if this means mixing architectures!). In + principle, `as' attempts to deduce the minimal sufficient + processor type if none is specified; depending on the object code + format, the processor type may be recorded in the object file. If + it is critical that the `as' output match a specific architecture, + specify that architecture explicitly. + +`-b' + Add code to collect information about conditional branches taken, + for later optimization using branch prediction bits. (The + conditional branch instructions have branch prediction bits in the + CA, CB, and CC architectures.) If BR represents a conditional + branch instruction, the following represents the code generated by + the assembler when `-b' is specified: + + call INCREMENT ROUTINE + .word 0 # pre-counter + Label: BR + call INCREMENT ROUTINE + .word 0 # post-counter + + The counter following a branch records the number of times that + branch was _not_ taken; the differenc between the two counters is + the number of times the branch _was_ taken. + + A table of every such `Label' is also generated, so that the + external postprocessor `gbr960' (supplied by Intel) can locate all + the counters. This table is always labeled `__BRANCH_TABLE__'; + this is a local symbol to permit collecting statistics for many + separate object files. The table is word aligned, and begins with + a two-word header. The first word, initialized to 0, is used in + maintaining linked lists of branch tables. The second word is a + count of the number of entries in the table, which follow + immediately: each is a word, pointing to one of the labels + illustrated above. + + +------------+------------+------------+ ... +------------+ + | | | | | | + | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | + | | | | | | + +------------+------------+------------+ ... +------------+ + + __BRANCH_TABLE__ layout + + The first word of the header is used to locate multiple branch + tables, since each object file may contain one. Normally the links + are maintained with a call to an initialization routine, placed at + the beginning of each function in the file. The GNU C compiler + generates these calls automatically when you give it a `-b' option. + For further details, see the documentation of `gbr960'. + +`-no-relax' + Normally, Compare-and-Branch instructions with targets that require + displacements greater than 13 bits (or that have external targets) + are replaced with the corresponding compare (or `chkbit') and + branch instructions. You can use the `-no-relax' option to + specify that `as' should generate errors instead, if the target + displacement is larger than 13 bits. + + This option does not affect the Compare-and-Jump instructions; the + code emitted for them is _always_ adjusted when necessary + (depending on displacement size), regardless of whether you use + `-no-relax'. + + +File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent + +Floating Point +-------------- + + `as' generates IEEE floating-point numbers for the directives +`.float', `.double', `.extended', and `.single'. + + +File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent + +i960 Machine Directives +----------------------- + +`.bss SYMBOL, LENGTH, ALIGN' + Reserve LENGTH bytes in the bss section for a local SYMBOL, + aligned to the power of two specified by ALIGN. LENGTH and ALIGN + must be positive absolute expressions. This directive differs + from `.lcomm' only in that it permits you to specify an alignment. + *Note `.lcomm': Lcomm. + +`.extended FLONUMS' + `.extended' expects zero or more flonums, separated by commas; for + each flonum, `.extended' emits an IEEE extended-format (80-bit) + floating-point number. + +`.leafproc CALL-LAB, BAL-LAB' + You can use the `.leafproc' directive in conjunction with the + optimized `callj' instruction to enable faster calls of leaf + procedures. If a procedure is known to call no other procedures, + you may define an entry point that skips procedure prolog code + (and that does not depend on system-supplied saved context), and + declare it as the BAL-LAB using `.leafproc'. If the procedure + also has an entry point that goes through the normal prolog, you + can specify that entry point as CALL-LAB. + + A `.leafproc' declaration is meant for use in conjunction with the + optimized call instruction `callj'; the directive records the data + needed later to choose between converting the `callj' into a `bal' + or a `call'. + + CALL-LAB is optional; if only one argument is present, or if the + two arguments are identical, the single argument is assumed to be + the `bal' entry point. + +`.sysproc NAME, INDEX' + The `.sysproc' directive defines a name for a system procedure. + After you define it using `.sysproc', you can use NAME to refer to + the system procedure identified by INDEX when calling procedures + with the optimized call instruction `callj'. + + Both arguments are required; INDEX must be between 0 and 31 + (inclusive). + + +File: as.info, Node: Opcodes for i960, Prev: Directives-i960, Up: i960-Dependent + +i960 Opcodes +------------ + + All Intel 960 machine instructions are supported; *note i960 +Command-line Options: Options-i960. for a discussion of selecting the +instruction subset for a particular 960 architecture. + + Some opcodes are processed beyond simply emitting a single +corresponding instruction: `callj', and Compare-and-Branch or +Compare-and-Jump instructions with target displacements larger than 13 +bits. + +* Menu: + +* callj-i960:: `callj' +* Compare-and-branch-i960:: Compare-and-Branch + + +File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 + +`callj' +....... + + You can write `callj' to have the assembler or the linker determine +the most appropriate form of subroutine call: `call', `bal', or +`calls'. If the assembly source contains enough information--a +`.leafproc' or `.sysproc' directive defining the operand--then `as' +translates the `callj'; if not, it simply emits the `callj', leaving it +for the linker to resolve. + + +File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 + +Compare-and-Branch +.................. + + The 960 architectures provide combined Compare-and-Branch +instructions that permit you to store the branch target in the lower 13 +bits of the instruction word itself. However, if you specify a branch +target far enough away that its address won't fit in 13 bits, the +assembler can either issue an error, or convert your Compare-and-Branch +instruction into separate instructions to do the compare and the branch. + + Whether `as' gives an error or expands the instruction depends on +two choices you can make: whether you use the `-no-relax' option, and +whether you use a "Compare and Branch" instruction or a "Compare and +Jump" instruction. The "Jump" instructions are _always_ expanded if +necessary; the "Branch" instructions are expanded when necessary +_unless_ you specify `-no-relax'--in which case `as' gives an error +instead. + + These are the Compare-and-Branch instructions, their "Jump" variants, +and the instruction pairs they may expand into: + + Compare and + Branch Jump Expanded to + ------ ------ ------------ + bbc chkbit; bno + bbs chkbit; bo + cmpibe cmpije cmpi; be + cmpibg cmpijg cmpi; bg + cmpibge cmpijge cmpi; bge + cmpibl cmpijl cmpi; bl + cmpible cmpijle cmpi; ble + cmpibno cmpijno cmpi; bno + cmpibne cmpijne cmpi; bne + cmpibo cmpijo cmpi; bo + cmpobe cmpoje cmpo; be + cmpobg cmpojg cmpo; bg + cmpobge cmpojge cmpo; bge + cmpobl cmpojl cmpo; bl + cmpoble cmpojle cmpo; ble + cmpobne cmpojne cmpo; bne + + +File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies + +IA-64 Dependent Features +======================== + +* Menu: + +* IA-64 Options:: Options +* IA-64 Syntax:: Syntax +* IA-64 Opcodes:: Opcodes + + +File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent + +Options +------- + +`-mconstant-gp' + This option instructs the assembler to mark the resulting object + file as using the "constant GP" model. With this model, it is + assumed that the entire program uses a single global pointer (GP) + value. Note that this option does not in any fashion affect the + machine code emitted by the assembler. All it does is turn on the + EF_IA_64_CONS_GP flag in the ELF file header. + +`-mauto-pic' + This option instructs the assembler to mark the resulting object + file as using the "constant GP without function descriptor" data + model. This model is like the "constant GP" model, except that it + additionally does away with function descriptors. What this means + is that the address of a function refers directly to the + function's code entry-point. Normally, such an address would + refer to a function descriptor, which contains both the code + entry-point and the GP-value needed by the function. Note that + this option does not in any fashion affect the machine code + emitted by the assembler. All it does is turn on the + EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. + +`-milp32' + +`-milp64' + +`-mlp64' + +`-mp64' + These options select the data model. The assembler defaults to + `-mlp64' (LP64 data model). + +`-mle' + +`-mbe' + These options select the byte order. The `-mle' option selects + little-endian byte order (default) and `-mbe' selects big-endian + byte order. Note that IA-64 machine code always uses + little-endian byte order. + +`-munwind-check=warning' + +`-munwind-check=error' + These options control what the assembler will do when performing + consistency checks on unwind directives. `-munwind-check=warning' + will make the assembler issue a warning when an unwind directive + check fails. This is the default. `-munwind-check=error' will + make the assembler issue an error when an unwind directive check + fails. + +`-mhint.b=ok' + +`-mhint.b=warning' + +`-mhint.b=error' + These options control what the assembler will do when the `hint.b' + instruction is used. `-mhint.b=ok' will make the assembler accept + `hint.b'. `-mint.b=warning' will make the assembler issue a + warning when `hint.b' is used. `-mhint.b=error' will make the + assembler treat `hint.b' as an error, which is the default. + +`-x' + +`-xexplicit' + These options turn on dependency violation checking. + +`-xauto' + This option instructs the assembler to automatically insert stop + bits where necessary to remove dependency violations. This is the + default mode. + +`-xnone' + This option turns off dependency violation checking. + +`-xdebug' + This turns on debug output intended to help tracking down bugs in + the dependency violation checker. + +`-xdebugn' + This is a shortcut for -xnone -xdebug. + +`-xdebugx' + This is a shortcut for -xexplicit -xdebug. + + + +File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent + +Syntax +------ + + The assembler syntax closely follows the IA-64 Assembly Language +Reference Guide. + +* Menu: + +* IA-64-Chars:: Special Characters +* IA-64-Regs:: Register Names +* IA-64-Bits:: Bit Names + + +File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax + +Special Characters +.................. + + `//' is the line comment token. + + `;' can be used instead of a newline to separate statements. + + +File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax + +Register Names +.............. + + The 128 integer registers are referred to as `rN'. The 128 +floating-point registers are referred to as `fN'. The 128 application +registers are referred to as `arN'. The 128 control registers are +referred to as `crN'. The 64 one-bit predicate registers are referred +to as `pN'. The 8 branch registers are referred to as `bN'. In +addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' +(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), +`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). + + For convenience, the assembler also defines aliases for all named +application and control registers. For example, `ar.bsp' refers to the +register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to +the end-of-interrupt register (`cr67'). + + +File: as.info, Node: IA-64-Bits, Prev: IA-64-Regs, Up: IA-64 Syntax + +IA-64 Processor-Status-Register (PSR) Bit Names +............................................... + + The assembler defines bit masks for each of the bits in the IA-64 +processor status register. For example, `psr.ic' corresponds to a +value of 0x2000. These masks are primarily intended for use with the +`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere +else where an integer constant is expected. + + +File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent + +Opcodes +------- + + For detailed information on the IA-64 machine instruction set, see +the IA-64 Architecture Handbook +(http://developer.intel.com/design/itanium/arch_spec.htm). + + +File: as.info, Node: IP2K-Dependent, Next: M32R-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies + +IP2K Dependent Features +======================= + +* Menu: + +* IP2K-Opts:: IP2K Options + + +File: as.info, Node: IP2K-Opts, Up: IP2K-Dependent + +IP2K Options +------------ + + The Ubicom IP2K version of `as' has a few machine dependent options: + +`-mip2022ext' + `as' can assemble the extended IP2022 instructions, but it will + only do so if this is specifically allowed via this command line + option. + +`-mip2022' + This option restores the assembler's default behaviour of not + permitting the extended IP2022 instructions to be assembled. + + + +File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies + +M32R Dependent Features +======================= + +* Menu: + +* M32R-Opts:: M32R Options +* M32R-Directives:: M32R Directives +* M32R-Warnings:: M32R Warnings + + +File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent + +M32R Options +------------ + + The Renease M32R version of `as' has a few machine dependent options: + +`-m32rx' + `as' can assemble code for several different members of the + Renesas M32R family. Normally the default is to assemble code for + the M32R microprocessor. This option may be used to change the + default to the M32RX microprocessor, which adds some more + instructions to the basic M32R instruction set, and some + additional parameters to some of the original instructions. + +`-m32r2' + This option changes the target processor to the the M32R2 + microprocessor. + +`-m32r' + This option can be used to restore the assembler's default + behaviour of assembling for the M32R microprocessor. This can be + useful if the default has been changed by a previous command line + option. + +`-little' + This option tells the assembler to produce little-endian code and + data. The default is dependent upon how the toolchain was + configured. + +`-EL' + This is a synonum for _-little_. + +`-big' + This option tells the assembler to produce big-endian code and + data. + +`-EB' + This is a synonum for _-big_. + +`-KPIC' + This option specifies that the output of the assembler should be + marked as position-independent code (PIC). + +`-parallel' + This option tells the assembler to attempts to combine two + sequential instructions into a single, parallel instruction, where + it is legal to do so. + +`-no-parallel' + This option disables a previously enabled _-parallel_ option. + +`-no-bitinst' + This option disables the support for the extended bit-field + instructions provided by the M32R2. If this support needs to be + re-enabled the _-bitinst_ switch can be used to restore it. + +`-O' + This option tells the assembler to attempt to optimize the + instructions that it produces. This includes filling delay slots + and converting sequential instructions into parallel ones. This + option implies _-parallel_. + +`-warn-explicit-parallel-conflicts' + Instructs `as' to produce warning messages when questionable + parallel instructions are encountered. This option is enabled by + default, but `gcc' disables it when it invokes `as' directly. + Questionable instructions are those whoes behaviour would be + different if they were executed sequentially. For example the + code fragment `mv r1, r2 || mv r3, r1' produces a different result + from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 + and then r2 into r1, whereas the later moves r2 into r1 and r3. + +`-Wp' + This is a shorter synonym for the + _-warn-explicit-parallel-conflicts_ option. + +`-no-warn-explicit-parallel-conflicts' + Instructs `as' not to produce warning messages when questionable + parallel instructions are encountered. + +`-Wnp' + This is a shorter synonym for the + _-no-warn-explicit-parallel-conflicts_ option. + +`-ignore-parallel-conflicts' + This option tells the assembler's to stop checking parallel + instructions for contraint violations. This ability is provided + for hardware vendors testing chip designs and should not be used + under normal circumstances. + +`-no-ignore-parallel-conflicts' + This option restores the assembler's default behaviour of checking + parallel instructions to detect constraint violations. + +`-Ip' + This is a shorter synonym for the _-ignore-parallel-conflicts_ + option. + +`-nIp' + This is a shorter synonym for the _-no-ignore-parallel-conflicts_ + option. + +`-warn-unmatched-high' + This option tells the assembler to produce a warning message if a + `.high' pseudo op is encountered without a mathcing `.low' pseudo + op. The presence of such an unmatches pseudo op usually indicates + a programming error. + +`-no-warn-unmatched-high' + Disables a previously enabled _-warn-unmatched-high_ option. + +`-Wuh' + This is a shorter synonym for the _-warn-unmatched-high_ option. + +`-Wnuh' + This is a shorter synonym for the _-no-warn-unmatched-high_ option. + + + +File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent + +M32R Directives +--------------- + + The Renease M32R version of `as' has a few architecture specific +directives: + +`low EXPRESSION' + The `low' directive computes the value of its expression and + places the lower 16-bits of the result into the immediate-field of + the instruction. For example: + + or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 + add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred + +`high EXPRESSION' + The `high' directive computes the value of its expression and + places the upper 16-bits of the result into the immediate-field of + the instruction. For example: + + seth r0, #high(0x12345678) ; compute r0 = 0x12340000 + seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred + +`shigh EXPRESSION' + The `shigh' directive is very similar to the `high' directive. It + also computes the value of its expression and places the upper + 16-bits of the result into the immediate-field of the instruction. + The difference is that `shigh' also checks to see if the lower + 16-bits could be interpreted as a signed number, and if so it + assumes that a borrow will occur from the upper-16 bits. To + compensate for this the `shigh' directive pre-biases the upper 16 + bit value by adding one to it. For example: + + For example: + + seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 + seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 + + In the second example the lower 16-bits are 0x8000. If these are + treated as a signed value and sign extended to 32-bits then the + value becomes 0xffff8000. If this value is then added to + 0x00010000 then the result is 0x00008000. + + This behaviour is to allow for the different semantics of the + `or3' and `add3' instructions. The `or3' instruction treats its + 16-bit immediate argument as unsigned whereas the `add3' treats + its 16-bit immediate as a signed value. So for example: + + seth r0, #shigh(0x00008000) + add3 r0, r0, #low(0x00008000) + + Produces the correct result in r0, whereas: + + seth r0, #shigh(0x00008000) + or3 r0, r0, #low(0x00008000) + + Stores 0xffff8000 into r0. + + Note - the `shigh' directive does not know where in the assembly + source code the lower 16-bits of the value are going set, so it + cannot check to make sure that an `or3' instruction is being used + rather than an `add3' instruction. It is up to the programmer to + make sure that correct directives are used. + +`.m32r' + The directive performs a similar thing as the _-m32r_ command line + option. It tells the assembler to only accept M32R instructions + from now on. An instructions from later M32R architectures are + refused. + +`.m32rx' + The directive performs a similar thing as the _-m32rx_ command + line option. It tells the assembler to start accepting the extra + instructions in the M32RX ISA as well as the ordinary M32R ISA. + +`.m32r2' + The directive performs a similar thing as the _-m32r2_ command + line option. It tells the assembler to start accepting the extra + instructions in the M32R2 ISA as well as the ordinary M32R ISA. + +`.little' + The directive performs a similar thing as the _-little_ command + line option. It tells the assembler to start producing + little-endian code and data. This option should be used with care + as producing mixed-endian binary files is frought with danger. + +`.big' + The directive performs a similar thing as the _-big_ command line + option. It tells the assembler to start producing big-endian code + and data. This option should be used with care as producing + mixed-endian binary files is frought with danger. + + + +File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent + +M32R Warnings +------------- + + There are several warning and error messages that can be produced by +`as' which are specific to the M32R: + +`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' + This message is only produced if warnings for explicit parallel + conflicts have been enabled. It indicates that the assembler has + encountered a parallel instruction in which the destination + register of the left hand instruction is used as an input register + in the right hand instruction. For example in this code fragment + `mv r1, r2 || neg r3, r1' register r1 is the destination of the + move instruction and the input to the neg instruction. + +`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' + This message is only produced if warnings for explicit parallel + conflicts have been enabled. It indicates that the assembler has + encountered a parallel instruction in which the destination + register of the right hand instruction is used as an input + register in the left hand instruction. For example in this code + fragment `mv r1, r2 || neg r2, r3' register r2 is the destination + of the neg instruction and the input to the move instruction. + +`instruction `...' is for the M32RX only' + This message is produced when the assembler encounters an + instruction which is only supported by the M32Rx processor, and + the `-m32rx' command line flag has not been specified to allow + assembly of such instructions. + +`unknown instruction `...'' + This message is produced when the assembler encounters an + instruction which it does not recognise. + +`only the NOP instruction can be issued in parallel on the m32r' + This message is produced when the assembler encounters a parallel + instruction which does not involve a NOP instruction and the + `-m32rx' command line flag has not been specified. Only the M32Rx + processor is able to execute two instructions in parallel. + +`instruction `...' cannot be executed in parallel.' + This message is produced when the assembler encounters a parallel + instruction which is made up of one or two instructions which + cannot be executed in parallel. + +`Instructions share the same execution pipeline' + This message is produced when the assembler encounters a parallel + instruction whoes components both use the same execution pipeline. + +`Instructions write to the same destination register.' + This message is produced when the assembler encounters a parallel + instruction where both components attempt to modify the same + register. For example these code fragments will produce this + message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, + @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx + r3, r4' (Both write to the condition bit) + + + +File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies + +M680x0 Dependent Features +========================= + +* Menu: + +* M68K-Opts:: M680x0 Options +* M68K-Syntax:: Syntax +* M68K-Moto-Syntax:: Motorola Syntax +* M68K-Float:: Floating Point +* M68K-Directives:: 680x0 Machine Directives +* M68K-opcodes:: Opcodes + + +File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent + +M680x0 Options +-------------- + + The Motorola 680x0 version of `as' has a few machine dependent +options: + +`-l' + You can use the `-l' option to shorten the size of references to + undefined symbols. If you do not use the `-l' option, references + to undefined symbols are wide enough for a full `long' (32 bits). + (Since `as' cannot know where these symbols end up, `as' can only + allocate space for the linker to fill in later. Since `as' does + not know how far away these symbols are, it allocates as much + space as it can.) If you use this option, the references are only + one word wide (16 bits). This may be useful if you want the + object file to be as small as possible, and you know that the + relevant symbols are always less than 17 bits away. + +`--register-prefix-optional' + For some configurations, especially those where the compiler + normally does not prepend an underscore to the names of user + variables, the assembler requires a `%' before any use of a + register name. This is intended to let the assembler distinguish + between C variables and functions named `a0' through `a7', and so + on. The `%' is always accepted, but is not required for certain + configurations, notably `sun3'. The `--register-prefix-optional' + option may be used to permit omitting the `%' even for + configurations for which it is normally required. If this is + done, it will generally be impossible to refer to C variables and + functions with the same names as register names. + +`--bitwise-or' + Normally the character `|' is treated as a comment character, which + means that it can not be used in expressions. The `--bitwise-or' + option turns `|' into a normal character. In this mode, you must + either use C style comments, or start comments with a `#' character + at the beginning of a line. + +`--base-size-default-16 --base-size-default-32' + If you use an addressing mode with a base register without + specifying the size, `as' will normally use the full 32 bit value. + For example, the addressing mode `%a0@(%d0)' is equivalent to + `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to + tell `as' to default to using the 16 bit value. In this case, + `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the + `--base-size-default-32' option to restore the default behaviour. + +`--disp-size-default-16 --disp-size-default-32' + If you use an addressing mode with a displacement, and the value + of the displacement is not known, `as' will normally assume that + the value is 32 bits. For example, if the symbol `disp' has not + been defined, `as' will assemble the addressing mode + `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use + the `--disp-size-default-16' option to tell `as' to instead assume + that the displacement is 16 bits. In this case, `as' will + assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You + may use the `--disp-size-default-32' option to restore the default + behaviour. + +`--pcrel' + Always keep branches PC-relative. In the M680x0 architecture all + branches are defined as PC-relative. However, on some processors + they are limited to word displacements maximum. When `as' needs a + long branch that is not available, it normally emits an absolute + jump instead. This option disables this substitution. When this + option is given and no long branches are available, only word + branches will be emitted. An error message will be generated if a + word branch cannot reach its target. This option has no effect on + 68020 and other processors that have long branches. *note Branch + Improvement: M68K-Branch.. + +`-m68000' + `as' can assemble code for several different members of the + Motorola 680x0 family. The default depends upon how `as' was + configured when it was built; normally, the default is to assemble + code for the 68020 microprocessor. The following options may be + used to change the default. These options control which + instructions and addressing modes are permitted. The members of + the 680x0 family are very similar. For detailed information about + the differences, see the Motorola manuals. + + `-m68000' + `-m68ec000' + `-m68hc000' + `-m68hc001' + `-m68008' + `-m68302' + `-m68306' + `-m68307' + `-m68322' + `-m68356' + Assemble for the 68000. `-m68008', `-m68302', and so on are + synonyms for `-m68000', since the chips are the same from the + point of view of the assembler. + + `-m68010' + Assemble for the 68010. + + `-m68020' + `-m68ec020' + Assemble for the 68020. This is normally the default. + + `-m68030' + `-m68ec030' + Assemble for the 68030. + + `-m68040' + `-m68ec040' + Assemble for the 68040. + + `-m68060' + `-m68ec060' + Assemble for the 68060. + + `-mcpu32' + `-m68330' + `-m68331' + `-m68332' + `-m68333' + `-m68334' + `-m68336' + `-m68340' + `-m68341' + `-m68349' + `-m68360' + Assemble for the CPU32 family of chips. + + `-m5200' + + `-m5202' + + `-m5204' + + `-m5206' + + `-m5206e' + + `-m521x' + + `-m5249' + + `-m528x' + + `-m5307' + + `-m5407' + + `-m547x' + + `-m548x' + + `-mcfv4' + + `-mcfv4e' + Assemble for the ColdFire family of chips. + + `-m68881' + `-m68882' + Assemble 68881 floating point instructions. This is the + default for the 68020, 68030, and the CPU32. The 68040 and + 68060 always support floating point instructions. + + `-mno-68881' + Do not assemble 68881 floating point instructions. This is + the default for 68000 and the 68010. The 68040 and 68060 + always support floating point instructions, even if this + option is used. + + `-m68851' + Assemble 68851 MMU instructions. This is the default for the + 68020, 68030, and 68060. The 68040 accepts a somewhat + different set of MMU instructions; `-m68851' and `-m68040' + should not be used together. + + `-mno-68851' + Do not assemble 68851 MMU instructions. This is the default + for the 68000, 68010, and the CPU32. The 68040 accepts a + somewhat different set of MMU instructions. + + +File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent + +Syntax +------ + + This syntax for the Motorola 680x0 was developed at MIT. + + The 680x0 version of `as' uses instructions names and syntax +compatible with the Sun assembler. Intervening periods are ignored; +for example, `movl' is equivalent to `mov.l'. + + In the following table APC stands for any of the address registers +(`%a0' through `%a7'), the program counter (`%pc'), the zero-address +relative to the program counter (`%zpc'), a suppressed address register +(`%za0' through `%za7'), or it may be omitted entirely. The use of +SIZE means one of `w' or `l', and it may be omitted, along with the +leading colon, unless a scale is also specified. The use of SCALE +means one of `1', `2', `4', or `8', and it may always be omitted along +with the leading colon. + + The following addressing modes are understood: +"Immediate" + `#NUMBER' + +"Data Register" + `%d0' through `%d7' + +"Address Register" + `%a0' through `%a7' + `%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is + also known as `%fp', the Frame Pointer. + +"Address Register Indirect" + `%a0@' through `%a7@' + +"Address Register Postincrement" + `%a0@+' through `%a7@+' + +"Address Register Predecrement" + `%a0@-' through `%a7@-' + +"Indirect Plus Offset" + `APC@(NUMBER)' + +"Index" + `APC@(NUMBER,REGISTER:SIZE:SCALE)' + + The NUMBER may be omitted. + +"Postindex" + `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' + + The ONUMBER or the REGISTER, but not both, may be omitted. + +"Preindex" + `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' + + The NUMBER may be omitted. Omitting the REGISTER produces the + Postindex addressing mode. + +"Absolute" + `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'. + + +File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent + +Motorola Syntax +--------------- + + The standard Motorola syntax for this chip differs from the syntax +already discussed (*note Syntax: M68K-Syntax.). `as' can accept +Motorola syntax for operands, even if MIT syntax is used for other +operands in the same instruction. The two kinds of syntax are fully +compatible. + + In the following table APC stands for any of the address registers +(`%a0' through `%a7'), the program counter (`%pc'), the zero-address +relative to the program counter (`%zpc'), or a suppressed address +register (`%za0' through `%za7'). The use of SIZE means one of `w' or +`l', and it may always be omitted along with the leading dot. The use +of SCALE means one of `1', `2', `4', or `8', and it may always be +omitted along with the leading asterisk. + + The following additional addressing modes are understood: + +"Address Register Indirect" + `(%a0)' through `(%a7)' + `%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is + also known as `%fp', the Frame Pointer. + +"Address Register Postincrement" + `(%a0)+' through `(%a7)+' + +"Address Register Predecrement" + `-(%a0)' through `-(%a7)' + +"Indirect Plus Offset" + `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. + + The NUMBER may also appear within the parentheses, as in + `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted + (with an address register, omitting the NUMBER produces Address + Register Indirect mode). + +"Index" + `NUMBER(APC,REGISTER.SIZE*SCALE)' + + The NUMBER may be omitted, or it may appear within the + parentheses. The APC may be omitted. The REGISTER and the APC + may appear in either order. If both APC and REGISTER are address + registers, and the SIZE and SCALE are omitted, then the first + register is taken as the base register, and the second as the + index register. + +"Postindex" + `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' + + The ONUMBER, or the REGISTER, or both, may be omitted. Either the + NUMBER or the APC may be omitted, but not both. + +"Preindex" + `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' + + The NUMBER, or the APC, or the REGISTER, or any two of them, may + be omitted. The ONUMBER may be omitted. The REGISTER and the APC + may appear in either order. If both APC and REGISTER are address + registers, and the SIZE and SCALE are omitted, then the first + register is taken as the base register, and the second as the + index register. + + +File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent + +Floating Point +-------------- + + Packed decimal (P) format floating literals are not supported. Feel +free to add the code! + + The floating point formats generated by directives are these. + +`.float' + `Single' precision floating point constants. + +`.double' + `Double' precision floating point constants. + +`.extend' +`.ldouble' + `Extended' precision (`long double') floating point constants. + + +File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent + +680x0 Machine Directives +------------------------ + + In order to be compatible with the Sun assembler the 680x0 assembler +understands the following directives. + +`.data1' + This directive is identical to a `.data 1' directive. + +`.data2' + This directive is identical to a `.data 2' directive. + +`.even' + This directive is a special case of the `.align' directive; it + aligns the output to an even byte boundary. + +`.skip' + This directive is identical to a `.space' directive. + + +File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent + +Opcodes +------- + +* Menu: + +* M68K-Branch:: Branch Improvement +* M68K-Chars:: Special Characters + + +File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes + +Branch Improvement +.................. + + Certain pseudo opcodes are permitted for branch instructions. They +expand to the shortest branch instruction that reach the target. +Generally these mnemonics are made by substituting `j' for `b' at the +start of a Motorola mnemonic. + + The following table summarizes the pseudo-operations. A `*' flags +cases that are more fully described after the table: + + Displacement + +------------------------------------------------------------ + | 68020 68000/10, not PC-relative OK + Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** + +------------------------------------------------------------ + jbsr |bsrs bsrw bsrl jsr + jra |bras braw bral jmp + * jXX |bXXs bXXw bXXl bNXs;jmp + * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp + fjXX | N/A fbXXw fbXXl N/A + + XX: condition + NX: negative of condition XX + `*'--see full description below + `**'--this expansion mode is disallowed by `--pcrel' +`jbsr' +`jra' + These are the simplest jump pseudo-operations; they always map to + one particular machine instruction, depending on the displacement + to the branch target. This instruction will be a byte or word + branch is that is sufficient. Otherwise, a long branch will be + emitted if available. If no long branches are available and the + `--pcrel' option is not given, an absolute long jump will be + emitted instead. If no long branches are available, the `--pcrel' + option is given, and a word branch cannot reach the target, an + error message is generated. + + In addition to standard branch operands, `as' allows these + pseudo-operations to have all operands that are allowed for jsr + and jmp, substituting these instructions if the operand given is + not valid for a branch instruction. + +`jXX' + Here, `jXX' stands for an entire family of pseudo-operations, + where XX is a conditional branch or condition-code test. The full + list of pseudo-ops in this family is: + jhi jls jcc jcs jne jeq jvc + jvs jpl jmi jge jlt jgt jle + + Usually, each of these pseudo-operations expands to a single branch + instruction. However, if a word branch is not sufficient, no long + branches are available, and the `--pcrel' option is not given, `as' + issues a longer code fragment in terms of NX, the opposite + condition to XX. For example, under these conditions: + jXX foo + gives + bNXs oof + jmp foo + oof: + +`dbXX' + The full family of pseudo-operations covered here is + dbhi dbls dbcc dbcs dbne dbeq dbvc + dbvs dbpl dbmi dbge dblt dbgt dble + dbf dbra dbt + + Motorola `dbXX' instructions allow word displacements only. When + a word displacement is sufficient, each of these pseudo-operations + expands to the corresponding Motorola instruction. When a word + displacement is not sufficient and long branches are available, + when the source reads `dbXX foo', `as' emits + dbXX oo1 + bras oo2 + oo1:bral foo + oo2: + + If, however, long branches are not available and the `--pcrel' + option is not given, `as' emits + dbXX oo1 + bras oo2 + oo1:jmp foo + oo2: + +`fjXX' + This family includes + fjne fjeq fjge fjlt fjgt fjle fjf + fjt fjgl fjgle fjnge fjngl fjngle fjngt + fjnle fjnlt fjoge fjogl fjogt fjole fjolt + fjor fjseq fjsf fjsne fjst fjueq fjuge + fjugt fjule fjult fjun + + Each of these pseudo-operations always expands to a single Motorola + coprocessor branch instruction, word or long. All Motorola + coprocessor branch instructions allow both word and long + displacements. + + + +File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes + +Special Characters +.................. + + The immediate character is `#' for Sun compatibility. The +line-comment character is `|' (unless the `--bitwise-or' option is +used). If a `#' appears at the beginning of a line, it is treated as a +comment unless it looks like `# line file', in which case it is treated +normally. + + +File: as.info, Node: M68HC11-Dependent, Next: M88K-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies + +M68HC11 and M68HC12 Dependent Features +====================================== + +* Menu: + +* M68HC11-Opts:: M68HC11 and M68HC12 Options +* M68HC11-Syntax:: Syntax +* M68HC11-Modifiers:: Symbolic Operand Modifiers +* M68HC11-Directives:: Assembler Directives +* M68HC11-Float:: Floating Point +* M68HC11-opcodes:: Opcodes + + +File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent + +M68HC11 and M68HC12 Options +--------------------------- + + The Motorola 68HC11 and 68HC12 version of `as' have a few machine +dependent options. + +`-m68hc11' + This option switches the assembler in the M68HC11 mode. In this + mode, the assembler only accepts 68HC11 operands and mnemonics. It + produces code for the 68HC11. + +`-m68hc12' + This option switches the assembler in the M68HC12 mode. In this + mode, the assembler also accepts 68HC12 operands and mnemonics. It + produces code for the 68HC12. A few 68HC11 instructions are + replaced by some 68HC12 instructions as recommended by Motorola + specifications. + +`-m68hcs12' + This option switches the assembler in the M68HCS12 mode. This + mode is similar to `-m68hc12' but specifies to assemble for the + 68HCS12 series. The only difference is on the assembling of the + `movb' and `movw' instruction when a PC-relative operand is used. + +`-mshort' + This option controls the ABI and indicates to use a 16-bit integer + ABI. It has no effect on the assembled instructions. This is the + default. + +`-mlong' + This option controls the ABI and indicates to use a 32-bit integer + ABI. + +`-mshort-double' + This option controls the ABI and indicates to use a 32-bit float + ABI. This is the default. + +`-mlong-double' + This option controls the ABI and indicates to use a 64-bit float + ABI. + +`--strict-direct-mode' + You can use the `--strict-direct-mode' option to disable the + automatic translation of direct page mode addressing into extended + mode when the instruction does not support direct mode. For + example, the `clr' instruction does not support direct page mode + addressing. When it is used with the direct page mode, `as' will + ignore it and generate an absolute addressing. This option + prevents `as' from doing this, and the wrong usage of the direct + page mode will raise an error. + +`--short-branchs' + The `--short-branchs' option turns off the translation of relative + branches into absolute branches when the branch offset is out of + range. By default `as' transforms the relative branch (`bsr', + `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', `bls', + `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch when + the offset is out of the -128 .. 127 range. In that case, the + `bsr' instruction is translated into a `jsr', the `bra' + instruction is translated into a `jmp' and the conditional branchs + instructions are inverted and followed by a `jmp'. This option + disables these translations and `as' will generate an error if a + relative branch is out of range. This option does not affect the + optimization associated to the `jbra', `jbsr' and `jbXX' pseudo + opcodes. + +`--force-long-branchs' + The `--force-long-branchs' option forces the translation of + relative branches into absolute branches. This option does not + affect the optimization associated to the `jbra', `jbsr' and + `jbXX' pseudo opcodes. + +`--print-insn-syntax' + You can use the `--print-insn-syntax' option to obtain the syntax + description of the instruction when an error is detected. + +`--print-opcodes' + The `--print-opcodes' option prints the list of all the + instructions with their syntax. The first item of each line + represents the instruction name and the rest of the line indicates + the possible operands for that instruction. The list is printed in + alphabetical order. Once the list is printed `as' exits. + +`--generate-example' + The `--generate-example' option is similar to `--print-opcodes' + but it generates an example for each instruction instead. + + +File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent + +Syntax +------ + + In the M68HC11 syntax, the instruction name comes first and it may +be followed by one or several operands (up to three). Operands are +separated by comma (`,'). In the normal mode, `as' will complain if too +many operands are specified for a given instruction. In the MRI mode +(turned on with `-M' option), it will treat them as comments. Example: + + inx + lda #23 + bset 2,x #4 + brclr *bot #8 foo + + The following addressing modes are understood for 68HC11 and 68HC12: +"Immediate" + `#NUMBER' + +"Address Register" + `NUMBER,X', `NUMBER,Y' + + The NUMBER may be omitted in which case 0 is assumed. + +"Direct Addressing mode" + `*SYMBOL', or `*DIGITS' + +"Absolute" + `SYMBOL', or `DIGITS' + + The M68HC12 has other more complex addressing modes. All of them are +supported and they are represented below: + +"Constant Offset Indexed Addressing Mode" + `NUMBER,REG' + + The NUMBER may be omitted in which case 0 is assumed. The + register can be either `X', `Y', `SP' or `PC'. The assembler will + use the smaller post-byte definition according to the constant + value (5-bit constant offset, 9-bit constant offset or 16-bit + constant offset). If the constant is not known by the assembler + it will use the 16-bit constant offset post-byte and the value + will be resolved at link time. + +"Offset Indexed Indirect" + `[NUMBER,REG]' + + The register can be either `X', `Y', `SP' or `PC'. + +"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" + `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' + + The number must be in the range `-8'..`+8' and must not be 0. The + register can be either `X', `Y', `SP' or `PC'. + +"Accumulator Offset" + `ACC,REG' + + The accumulator register can be either `A', `B' or `D'. The + register can be either `X', `Y', `SP' or `PC'. + +"Accumulator D offset indexed-indirect" + `[D,REG]' + + The register can be either `X', `Y', `SP' or `PC'. + + + For example: + + ldab 1024,sp + ldd [10,x] + orab 3,+x + stab -2,y- + ldx a,pc + sty [d,sp] + + +File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent + +Symbolic Operand Modifiers +-------------------------- + + The assembler supports several modifiers when using symbol addresses +in 68HC11 and 68HC12 instruction operands. The general syntax is the +following: + + %modifier(symbol) + +`%addr' + This modifier indicates to the assembler and linker to use the + 16-bit physical address corresponding to the symbol. This is + intended to be used on memory window systems to map a symbol in + the memory bank window. If the symbol is in a memory expansion + part, the physical address corresponds to the symbol address + within the memory bank window. If the symbol is not in a memory + expansion part, this is the symbol address (using or not using the + %addr modifier has no effect in that case). + +`%page' + This modifier indicates to use the memory page number corresponding + to the symbol. If the symbol is in a memory expansion part, its + page number is computed by the linker as a number used to map the + page containing the symbol in the memory bank window. If the + symbol is not in a memory expansion part, the page number is 0. + +`%hi' + This modifier indicates to use the 8-bit high part of the physical + address of the symbol. + +`%lo' + This modifier indicates to use the 8-bit low part of the physical + address of the symbol. + + + For example a 68HC12 call to a function `foo_example' stored in +memory expansion part could be written as follows: + + call %addr(foo_example),%page(foo_example) + + and this is equivalent to + + call foo_example + + And for 68HC11 it could be written as follows: + + ldab #%page(foo_example) + stab _page_switch + jsr %addr(foo_example) + + +File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent + +Assembler Directives +-------------------- + + The 68HC11 and 68HC12 version of `as' have the following specific +assembler directives: + +`.relax' + The relax directive is used by the `GNU Compiler' to emit a + specific relocation to mark a group of instructions for linker + relaxation. The sequence of instructions within the group must be + known to the linker so that relaxation can be performed. + +`.mode [mshort|mlong|mshort-double|mlong-double]' + This directive specifies the ABI. It overrides the `-mshort', + `-mlong', `-mshort-double' and `-mlong-double' options. + +`.far SYMBOL' + This directive marks the symbol as a `far' symbol meaning that it + uses a `call/rtc' calling convention as opposed to `jsr/rts'. + During a final link, the linker will identify references to the + `far' symbol and will verify the proper calling convention. + +`.interrupt SYMBOL' + This directive marks the symbol as an interrupt entry point. This + information is then used by the debugger to correctly unwind the + frame across interrupts. + +`.xrefb SYMBOL' + This directive is defined for compatibility with the + `Specification for Motorola 8 and 16-Bit Assembly Language Input + Standard' and is ignored. + + + +File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent + +Floating Point +-------------- + + Packed decimal (P) format floating literals are not supported. Feel +free to add the code! + + The floating point formats generated by directives are these. + +`.float' + `Single' precision floating point constants. + +`.double' + `Double' precision floating point constants. + +`.extend' +`.ldouble' + `Extended' precision (`long double') floating point constants. + + +File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent + +Opcodes +------- + +* Menu: + +* M68HC11-Branch:: Branch Improvement + + +File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes + +Branch Improvement +.................. + + Certain pseudo opcodes are permitted for branch instructions. They +expand to the shortest branch instruction that reach the target. +Generally these mnemonics are made by prepending `j' to the start of +Motorola mnemonic. These pseudo opcodes are not affected by the +`--short-branchs' or `--force-long-branchs' options. + + The following table summarizes the pseudo-operations. + + Displacement Width + +-------------------------------------------------------------+ + | Options | + | --short-branchs --force-long-branchs | + +--------------------------+----------------------------------+ + Op |BYTE WORD | BYTE WORD | + +--------------------------+----------------------------------+ + bsr | bsr | jsr | + bra | bra | jmp | + jbsr | bsr jsr | bsr jsr | + jbra | bra jmp | bra jmp | + bXX | bXX | bNX +3; jmp | + jbXX | bXX bNX +3; | bXX bNX +3; jmp | + | jmp | | + +--------------------------+----------------------------------+ + XX: condition + NX: negative of condition XX + +`jbsr' +`jbra' + These are the simplest jump pseudo-operations; they always map to + one particular machine instruction, depending on the displacement + to the branch target. + +`jbXX' + Here, `jbXX' stands for an entire family of pseudo-operations, + where XX is a conditional branch or condition-code test. The full + list of pseudo-ops in this family is: + jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo + jbcs jbne jblt jble jbls jbvc jbmi + + For the cases of non-PC relative displacements and long + displacements, `as' issues a longer code fragment in terms of NX, + the opposite condition to XX. For example, for the non-PC + relative case: + jbXX foo + gives + bNXs oof + jmp foo + oof: + + + +File: as.info, Node: M88K-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies + +Motorola M88K Dependent Features +================================ + +* Menu: + +* M88K Directives:: M88K Machine Directives + + +File: as.info, Node: M88K Directives, Up: M88K-Dependent + +M88K Machine Directives +----------------------- + + The M88K version of the assembler supports the following machine +directives: + +`.align' + This directive aligns the section program counter on the next + 4-byte boundary. + +`.dfloat EXPR' + This assembles a double precision (64-bit) floating point constant. + +`.ffloat EXPR' + This assembles a single precision (32-bit) floating point constant. + +`.half EXPR' + This directive assembles a half-word (16-bit) constant. + +`.word EXPR' + This assembles a word (32-bit) constant. + +`.string "STR"' + This directive behaves like the standard `.ascii' directive for + copying STR into the object file. The string is not terminated + with a null byte. + +`.set SYMBOL, VALUE' + This directive creates a symbol named SYMBOL which is an alias for + another symbol (possibly not yet defined). This should not be + confused with the mnemonic `set', which is a legitimate M88K + instruction. + +`.def SYMBOL, VALUE' + This directive is synonymous with `.set' and is presumably provided + for compatibility with other M88K assemblers. + +`.bss SYMBOL, LENGTH, ALIGN' + Reserve LENGTH bytes in the bss section for a local SYMBOL, + aligned to the power of two specified by ALIGN. LENGTH and ALIGN + must be positive absolute expressions. This directive differs + from `.lcomm' only in that it permits you to specify an alignment. + *Note `.lcomm': Lcomm. + + + +File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: M88K-Dependent, Up: Machine Dependencies + +MIPS Dependent Features +======================= + + GNU `as' for MIPS architectures supports several different MIPS +processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For +information about the MIPS instruction set, see `MIPS RISC +Architecture', by Kane and Heindrich (Prentice-Hall). For an overview +of MIPS assembly conventions, see "Appendix D: Assembly Language +Programming" in the same work. + +* Menu: + +* MIPS Opts:: Assembler options +* MIPS Object:: ECOFF object code +* MIPS Stabs:: Directives for debugging information +* MIPS ISA:: Directives to override the ISA level +* MIPS symbol sizes:: Directives to override the size of symbols +* MIPS autoextend:: Directives for extending MIPS 16 bit instructions +* MIPS insn:: Directive to mark data as an instruction +* MIPS option stack:: Directives to save and restore options +* MIPS ASE instruction generation overrides:: Directives to control + generation of MIPS ASE instructions + + +File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent + +Assembler options +----------------- + + The MIPS configurations of GNU `as' support these special options: + +`-G NUM' + This option sets the largest size of an object that can be + referenced implicitly with the `gp' register. It is only accepted + for targets that use ECOFF format. The default value is 8. + +`-EB' +`-EL' + Any MIPS configuration of `as' can select big-endian or + little-endian output at run time (unlike the other GNU development + tools, which must be configured for one or the other). Use `-EB' + to select big-endian output, and `-EL' for little-endian. + +`-mips1' +`-mips2' +`-mips3' +`-mips4' +`-mips5' +`-mips32' +`-mips32r2' +`-mips64' +`-mips64r2' + Generate code for a particular MIPS Instruction Set Architecture + level. `-mips1' corresponds to the R2000 and R3000 processors, + `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, + and `-mips4' to the R8000 and R10000 processors. `-mips5', + `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to + generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 + RELEASE 2 ISA processors, respectively. You can also switch + instruction sets during the assembly; see *Note Directives to + override the ISA level: MIPS ISA. + +`-mgp32' +`-mfp32' + Some macros have different expansions for 32-bit and 64-bit + registers. The register sizes are normally inferred from the ISA + and ABI, but these flags force a certain group of registers to be + treated as 32 bits wide at all times. `-mgp32' controls the size + of general-purpose registers and `-mfp32' controls the size of + floating-point registers. + + On some MIPS variants there is a 32-bit mode flag; when this flag + is set, 64-bit instructions generate a trap. Also, some 32-bit + OSes only save the 32-bit registers on a context switch, so it is + essential never to use the 64-bit registers. + +`-mgp64' + Assume that 64-bit general purpose registers are available. This + is provided in the interests of symmetry with -gp32. + +`-mips16' +`-no-mips16' + Generate code for the MIPS 16 processor. This is equivalent to + putting `.set mips16' at the start of the assembly file. + `-no-mips16' turns off this option. + +`-mips3d' +`-no-mips3d' + Generate code for the MIPS-3D Application Specific Extension. + This tells the assembler to accept MIPS-3D instructions. + `-no-mips3d' turns off this option. + +`-mdmx' +`-no-mdmx' + Generate code for the MDMX Application Specific Extension. This + tells the assembler to accept MDMX instructions. `-no-mdmx' turns + off this option. + +`-mfix7000' +`-mno-fix7000' + Cause nops to be inserted if the read of the destination register + of an mfhi or mflo instruction occurs in the following two + instructions. + +`-mfix-vr4120' +`-no-mfix-vr4120' + Insert nops to work around certain VR4120 errata. This option is + intended to be used on GCC-generated code: it is not designed to + catch all problems in hand-written assembler code. + +`-mfix-vr4130' +`-no-mfix-vr4130' + Insert nops to work around the VR4130 `mflo'/`mfhi' errata. + +`-m4010' +`-no-m4010' + Generate code for the LSI R4010 chip. This tells the assembler to + accept the R4010 specific instructions (`addciu', `ffc', etc.), + and to not schedule `nop' instructions around accesses to the `HI' + and `LO' registers. `-no-m4010' turns off this option. + +`-m4650' +`-no-m4650' + Generate code for the MIPS R4650 chip. This tells the assembler + to accept the `mad' and `madu' instruction, and to not schedule + `nop' instructions around accesses to the `HI' and `LO' registers. + `-no-m4650' turns off this option. + +`-m3900' +`-no-m3900' +`-m4100' +`-no-m4100' + For each option `-mNNNN', generate code for the MIPS RNNNN chip. + This tells the assembler to accept instructions specific to that + chip, and to schedule for that chip's hazards. + +`-march=CPU' + Generate code for a particular MIPS cpu. It is exactly equivalent + to `-mCPU', except that there are more value of CPU understood. + Valid CPU value are: + + 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, + vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, + rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, + 10000, 12000, mips32-4k, sb1 + +`-mtune=CPU' + Schedule and tune for a particular MIPS cpu. Valid CPU values are + identical to `-march=CPU'. + +`-mabi=ABI' + Record which ABI the source code uses. The recognized arguments + are: `32', `n32', `o64', `64' and `eabi'. + +`-msym32' +`-mno-sym32' + Equivalent to adding `.set sym32' or `.set nosym32' to the + beginning of the assembler input. *Note MIPS symbol sizes::. + +`-nocpp' + This option is ignored. It is accepted for command-line + compatibility with other assemblers, which use it to turn off C + style preprocessing. With GNU `as', there is no need for + `-nocpp', because the GNU assembler itself never runs the C + preprocessor. + +`--construct-floats' +`--no-construct-floats' + The `--no-construct-floats' option disables the construction of + double width floating point constants by loading the two halves of + the value into the two single width floating point registers that + make up the double width register. This feature is useful if the + processor support the FR bit in its status register, and this bit + is known (by the programmer) to be set. This bit prevents the + aliasing of the double width register by the single width + registers. + + By default `--construct-floats' is selected, allowing construction + of these floating point constants. + +`--trap' +`--no-break' + `as' automatically macro expands certain division and + multiplication instructions to check for overflow and division by + zero. This option causes `as' to generate code to take a trap + exception rather than a break exception when an error is detected. + The trap instructions are only supported at Instruction Set + Architecture level 2 and higher. + +`--break' +`--no-trap' + Generate code to take a break exception rather than a trap + exception when an error is detected. This is the default. + +`-mpdr' +`-mno-pdr' + Control generation of `.pdr' sections. Off by default on IRIX, on + elsewhere. + +`-mshared' +`-mno-shared' + When generating code using the Unix calling conventions (selected + by `-KPIC' or `-mcall_shared'), gas will normally generate code + which can go into a shared library. The `-mno-shared' option + tells gas to generate code which uses the calling convention, but + can not go into a shared library. The resulting code is slightly + more efficient. This option only affects the handling of the + `.cpload' and `.cpsetup' pseudo-ops. + + +File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent + +MIPS ECOFF object code +---------------------- + + Assembling for a MIPS ECOFF target supports some additional sections +besides the usual `.text', `.data' and `.bss'. The additional sections +are `.rdata', used for read-only data, `.sdata', used for small data, +and `.sbss', used for small common objects. + + When assembling for ECOFF, the assembler uses the `$gp' (`$28') +register to form the address of a "small object". Any object in the +`.sdata' or `.sbss' sections is considered "small" in this sense. For +external objects, or for objects in the `.bss' section, you can use the +`gcc' `-G' option to control the size of objects addressed via `$gp'; +the default value is 8, meaning that a reference to any object eight +bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from +using the `$gp' register on the basis of object size (but the assembler +uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of +an object in the `.bss' section is set by the `.comm' or `.lcomm' +directive that defines it. The size of an external object may be set +with the `.extern' directive. For example, `.extern sym,4' declares +that the object at `sym' is 4 bytes in length, whie leaving `sym' +otherwise undefined. + + Using small ECOFF objects requires linker support, and assumes that +the `$gp' register is correctly initialized (normally done +automatically by the startup code). MIPS ECOFF assembly code must not +modify the `$gp' register. + + +File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent + +Directives for debugging information +------------------------------------ + + MIPS ECOFF `as' supports several directives used for generating +debugging information which are not support by traditional MIPS +assemblers. These are `.def', `.endef', `.dim', `.file', `.scl', +`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'. +The debugging information generated by the three `.stab' directives can +only be read by GDB, not by traditional MIPS debuggers (this +enhancement is required to fully support C++ debugging). These +directives are primarily used by compilers, not assembly language +programmers! + + +File: as.info, Node: MIPS symbol sizes, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent + +Directives to override the size of symbols +------------------------------------------ + + The n64 ABI allows symbols to have any 64-bit value. Although this +provides a great deal of flexibility, it means that some macros have +much longer expansions than their 32-bit counterparts. For example, +the non-PIC expansion of `dla $4,sym' is usually: + + lui $4,%highest(sym) + lui $1,%hi(sym) + daddiu $4,$4,%higher(sym) + daddiu $1,$1,%lo(sym) + dsll32 $4,$4,0 + daddu $4,$4,$1 + + whereas the 32-bit expansion is simply: + + lui $4,%hi(sym) + daddiu $4,$4,%lo(sym) + + n64 code is sometimes constructed in such a way that all symbolic +constants are known to have 32-bit values, and in such cases, it's +preferable to use the 32-bit expansion instead of the 64-bit expansion. + + You can use the `.set sym32' directive to tell the assembler that, +from this point on, all expressions of the form `SYMBOL' or `SYMBOL + +OFFSET' have 32-bit values. For example: + + .set sym32 + dla $4,sym + lw $4,sym+16 + sw $4,sym+0x8000($4) + + will cause the assembler to treat `sym', `sym+16' and `sym+0x8000' +as 32-bit values. The handling of non-symbolic addresses is not +affected. + + The directive `.set nosym32' ends a `.set sym32' block and reverts +to the normal behavior. It is also possible to change the symbol size +using the command-line options `-msym32' and `-mno-sym32'. + + These options and directives are always accepted, but at present, +they have no effect for anything other than n64. + + +File: as.info, Node: MIPS ISA, Next: MIPS symbol sizes, Prev: MIPS Stabs, Up: MIPS-Dependent + +Directives to override the ISA level +------------------------------------ + + GNU `as' supports an additional directive to change the MIPS +Instruction Set Architecture level on the fly: `.set mipsN'. N should +be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other +than 0 make the assembler accept instructions for the corresponding ISA +level, from that point on in the assembly. `.set mipsN' affects not +only which instructions are permitted, but also how certain macros are +expanded. `.set mips0' restores the ISA level to its original level: +either the level you selected with command line options, or the default +for your configuration. You can use this feature to permit specific +R4000 instructions while assembling in 32 bit mode. Use this directive +with care! + + The directive `.set mips16' puts the assembler into MIPS 16 mode, in +which it will assemble instructions for the MIPS 16 processor. Use +`.set nomips16' to return to normal 32 bit mode. + + Traditional MIPS assemblers do not support this directive. + + +File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS symbol sizes, Up: MIPS-Dependent + +Directives for extending MIPS 16 bit instructions +------------------------------------------------- + + By default, MIPS 16 instructions are automatically extended to 32 +bits when necessary. The directive `.set noautoextend' will turn this +off. When `.set noautoextend' is in effect, any 32 bit instruction +must be explicitly extended with the `.e' modifier (e.g., `li.e +$4,1000'). The directive `.set autoextend' may be used to once again +automatically extend instructions when necessary. + + This directive is only meaningful when in MIPS 16 mode. Traditional +MIPS assemblers do not support this directive. + + +File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent + +Directive to mark data as an instruction +---------------------------------------- + + The `.insn' directive tells `as' that the following data is actually +instructions. This makes a difference in MIPS 16 mode: when loading +the address of a label which precedes instructions, `as' automatically +adds 1 to the value, so that jumping to the loaded address will do the +right thing. + + +File: as.info, Node: MIPS option stack, Next: MIPS ASE instruction generation overrides, Prev: MIPS insn, Up: MIPS-Dependent + +Directives to save and restore options +-------------------------------------- + + The directives `.set push' and `.set pop' may be used to save and +restore the current settings for all the options which are controlled +by `.set'. The `.set push' directive saves the current settings on a +stack. The `.set pop' directive pops the stack and restores the +settings. + + These directives can be useful inside an macro which must change an +option such as the ISA level or instruction reordering but does not want +to change the state of the code which invoked the macro. + + Traditional MIPS assemblers do not support these directives. + + +File: as.info, Node: MIPS ASE instruction generation overrides, Prev: MIPS option stack, Up: MIPS-Dependent + +Directives to control generation of MIPS ASE instructions +--------------------------------------------------------- + + The directive `.set mips3d' makes the assembler accept instructions +from the MIPS-3D Application Specific Extension from that point on in +the assembly. The `.set nomips3d' directive prevents MIPS-3D +instructions from being accepted. + + The directive `.set mdmx' makes the assembler accept instructions +from the MDMX Application Specific Extension from that point on in the +assembly. The `.set nomdmx' directive prevents MDMX instructions from +being accepted. + + Traditional MIPS assemblers do not support these directives. + + +File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies + +MMIX Dependent Features +======================= + +* Menu: + +* MMIX-Opts:: Command-line Options +* MMIX-Expand:: Instruction expansion +* MMIX-Syntax:: Syntax +* MMIX-mmixal:: Differences to `mmixal' syntax and semantics + + +File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent + +Command-line Options +-------------------- + + The MMIX version of `as' has some machine-dependent options. + + When `--fixed-special-register-names' is specified, only the register +names specified in *Note MMIX-Regs:: are recognized in the instructions +`PUT' and `GET'. + + You can use the `--globalize-symbols' to make all symbols global. +This option is useful when splitting up a `mmixal' program into several +files. + + The `--gnu-syntax' turns off most syntax compatibility with +`mmixal'. Its usability is currently doubtful. + + The `--relax' option is not fully supported, but will eventually make +the object file prepared for linker relaxation. + + If you want to avoid inadvertently calling a predefined symbol and +would rather get an error, for example when using `as' with a compiler +or other machine-generated code, specify `--no-predefined-syms'. This +turns off built-in predefined definitions of all such symbols, +including rounding-mode symbols, segment symbols, `BIT' symbols, and +`TRAP' symbols used in `mmix' "system calls". It also turns off +predefined special-register names, except when used in `PUT' and `GET' +instructions. + + By default, some instructions are expanded to fit the size of the +operand or an external symbol (*note MMIX-Expand::). By passing +`--no-expand', no such expansion will be done, instead causing errors +at link time if the operand does not fit. + + The `mmixal' documentation (*note mmixsite::) specifies that global +registers allocated with the `GREG' directive (*note MMIX-greg::) and +initialized to the same non-zero value, will refer to the same global +register. This isn't strictly enforceable in `as' since the final +addresses aren't known until link-time, but it will do an effort unless +the `--no-merge-gregs' option is specified. (Register merging isn't +yet implemented in `ld'.) + + `as' will warn every time it expands an instruction to fit an +operand unless the option `-x' is specified. It is believed that this +behaviour is more useful than just mimicking `mmixal''s behaviour, in +which instructions are only expanded if the `-x' option is specified, +and assembly fails otherwise, when an instruction needs to be expanded. +It needs to be kept in mind that `mmixal' is both an assembler and +linker, while `as' will expand instructions that at link stage can be +contracted. (Though linker relaxation isn't yet implemented in `ld'.) +The option `-x' also imples `--linker-allocated-gregs'. + + If instruction expansion is enabled, `as' can expand a `PUSHJ' +instruction into a series of instructions. The shortest expansion is +to not expand it, but just mark the call as redirectable to a stub, +which `ld' creates at link-time, but only if the original `PUSHJ' +instruction is found not to reach the target. The stub consists of the +necessary instructions to form a jump to the target. This happens if +`as' can assert that the `PUSHJ' instruction can reach such a stub. +The option `--no-pushj-stubs' disables this shorter expansion, and the +longer series of instructions is then created at assembly-time. The +option `--no-stubs' is a synonym, intended for compatibility with +future releases, where generation of stubs for other instructions may +be implemented. + + Usually a two-operand-expression (*note GREG-base::) without a +matching `GREG' directive is treated as an error by `as'. When the +option `--linker-allocated-gregs' is in effect, they are instead passed +through to the linker, which will allocate as many global registers as +is needed. + + +File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent + +Instruction expansion +--------------------- + + When `as' encounters an instruction with an operand that is either +not known or does not fit the operand size of the instruction, `as' +(and `ld') will expand the instruction into a sequence of instructions +semantically equivalent to the operand fitting the instruction. +Expansion will take place for the following instructions: + +`GETA' + Expands to a sequence of four instructions: `SETL', `INCML', + `INCMH' and `INCH'. The operand must be a multiple of four. + +Conditional branches + A branch instruction is turned into a branch with the complemented + condition and prediction bit over five instructions; four + instructions setting `$255' to the operand value, which like with + `GETA' must be a multiple of four, and a final `GO $255,$255,0'. + +`PUSHJ' + Similar to expansion for conditional branches; four instructions + set `$255' to the operand value, followed by a `PUSHGO + $255,$255,0'. + +`JMP' + Similar to conditional branches and `PUSHJ'. The final instruction + is `GO $255,$255,0'. + + The linker `ld' is expected to shrink these expansions for code +assembled with `--relax' (though not currently implemented). + + +File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent + +Syntax +------ + + The assembly syntax is supposed to be upward compatible with that +described in Sections 1.3 and 1.4 of `The Art of Computer Programming, +Volume 1'. Draft versions of those chapters as well as other MMIX +information is located at +. Most code +examples from the mmixal package located there should work unmodified +when assembled and linked as single files, with a few noteworthy +exceptions (*note MMIX-mmixal::). + + Before an instruction is emitted, the current location is aligned to +the next four-byte boundary. If a label is defined at the beginning of +the line, its value will be the aligned value. + + In addition to the traditional hex-prefix `0x', a hexadecimal number +can also be specified by the prefix character `#'. + + After all operands to an MMIX instruction or directive have been +specified, the rest of the line is ignored, treated as a comment. + +* Menu: + +* MMIX-Chars:: Special Characters +* MMIX-Symbols:: Symbols +* MMIX-Regs:: Register Names +* MMIX-Pseudos:: Assembler Directives + + +File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax + +Special Characters +.................. + + The characters `*' and `#' are line comment characters; each start a +comment at the beginning of a line, but only at the beginning of a +line. A `#' prefixes a hexadecimal number if found elsewhere on a line. + + Two other characters, `%' and `!', each start a comment anywhere on +the line. Thus you can't use the `modulus' and `not' operators in +expressions normally associated with these two characters. + + A `;' is a line separator, treated as a new-line, so separate +instructions can be specified on a single line. + + +File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax + +Symbols +....... + + The character `:' is permitted in identifiers. There are two +exceptions to it being treated as any other symbol character: if a +symbol begins with `:', it means that the symbol is in the global +namespace and that the current prefix should not be prepended to that +symbol (*note MMIX-prefix::). The `:' is then not considered part of +the symbol. For a symbol in the label position (first on a line), a `:' +at the end of a symbol is silently stripped off. A label is permitted, +but not required, to be followed by a `:', as with many other assembly +formats. + + The character `@' in an expression, is a synonym for `.', the +current location. + + In addition to the common forward and backward local symbol formats +(*note Symbol Names::), they can be specified with upper-case `B' and +`F', as in `8B' and `9F'. A local label defined for the current +position is written with a `H' appended to the number: + 3H LDB $0,$1,2 + This and traditional local-label formats cannot be mixed: a label +must be defined and referred to using the same format. + + There's a minor caveat: just as for the ordinary local symbols, the +local symbols are translated into ordinary symbols using control +characters are to hide the ordinal number of the symbol. +Unfortunately, these symbols are not translated back in error messages. +Thus you may see confusing error messages when local symbols are used. +Control characters `\003' (control-C) and `\004' (control-D) are used +for the MMIX-specific local-symbol syntax. + + The symbol `Main' is handled specially; it is always global. + + By defining the symbols `__.MMIX.start..text' and +`__.MMIX.start..data', the address of respectively the `.text' and +`.data' segments of the final program can be defined, though when +linking more than one object file, the code or data in the object file +containing the symbol is not guaranteed to be start at that position; +just the final executable. *Note MMIX-loc::. + + +File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax + +Register names +.............. + + Local and global registers are specified as `$0' to `$255'. The +recognized special register names are `rJ', `rA', `rB', `rC', `rD', +`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', +`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', +`rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special +register names. + + Local and global symbols can be equated to register names and used in +place of ordinary registers. + + Similarly for special registers, local and global symbols can be +used. Also, symbols equated from numbers and constant expressions are +allowed in place of a special register, except when either of the +options `--no-predefined-syms' and `--fixed-special-register-names' are +specified. Then only the special register names above are allowed for +the instructions having a special register operand; `GET' and `PUT'. + + +File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax + +Assembler Directives +.................... + +`LOC' + The `LOC' directive sets the current location to the value of the + operand field, which may include changing sections. If the + operand is a constant, the section is set to either `.data' if the + value is `0x2000000000000000' or larger, else it is set to `.text'. + Within a section, the current location may only be changed to + monotonically higher addresses. A LOC expression must be a + previously defined symbol or a "pure" constant. + + An example, which sets the label PREV to the current location, and + updates the current location to eight bytes forward: + prev LOC @+8 + + When a LOC has a constant as its operand, a symbol + `__.MMIX.start..text' or `__.MMIX.start..data' is defined + depending on the address as mentioned above. Each such symbol is + interpreted as special by the linker, locating the section at that + address. Note that if multiple files are linked, the first object + file with that section will be mapped to that address (not + necessarily the file with the LOC definition). + +`LOCAL' + Example: + LOCAL external_symbol + LOCAL 42 + .local asymbol + + This directive-operation generates a link-time assertion that the + operand does not correspond to a global register. The operand is + an expression that at link-time resolves to a register symbol or a + number. A number is treated as the register having that number. + There is one restriction on the use of this directive: the + pseudo-directive must be placed in a section with contents, code + or data. + +`IS' + The `IS' directive: + asymbol IS an_expression + sets the symbol `asymbol' to `an_expression'. A symbol may not be + set more than once using this directive. Local labels may be set + using this directive, for example: + 5H IS @+4 + +`GREG' + This directive reserves a global register, gives it an initial + value and optionally gives it a symbolic name. Some examples: + + areg GREG + breg GREG data_value + GREG data_buffer + .greg creg, another_data_value + + The symbolic register name can be used in place of a (non-special) + register. If a value isn't provided, it defaults to zero. Unless + the option `--no-merge-gregs' is specified, non-zero registers + allocated with this directive may be eliminated by `as'; another + register with the same value used in its place. Any of the + instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', + `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', + `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', + `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can + have a value nearby an initial value in place of its second and + third operands. Here, "nearby" is defined as within the range + 0...255 from the initial value of such an allocated register. + + buffer1 BYTE 0,0,0,0,0 + buffer2 BYTE 0,0,0,0,0 + ... + GREG buffer1 + LDOU $42,buffer2 + In the example above, the `Y' field of the `LDOUI' instruction + (LDOU with a constant Z) will be replaced with the global register + allocated for `buffer1', and the `Z' field will have the value 5, + the offset from `buffer1' to `buffer2'. The result is equivalent + to this code: + buffer1 BYTE 0,0,0,0,0 + buffer2 BYTE 0,0,0,0,0 + ... + tmpreg GREG buffer1 + LDOU $42,tmpreg,(buffer2-buffer1) + + Global registers allocated with this directive are allocated in + order higher-to-lower within a file. Other than that, the exact + order of register allocation and elimination is undefined. For + example, the order is undefined when more than one file with such + directives are linked together. With the options `-x' and + `--linker-allocated-gregs', `GREG' directives for two-operand + cases like the one mentioned above can be omitted. Sufficient + global registers will then be allocated by the linker. + +`BYTE' + The `BYTE' directive takes a series of operands separated by a + comma. If an operand is a string (*note Strings::), each + character of that string is emitted as a byte. Other operands + must be constant expressions without forward references, in the + range 0...255. If you need operands having expressions with + forward references, use `.byte' (*note Byte::). An operand can be + omitted, defaulting to a zero value. + +`WYDE' +`TETRA' +`OCTA' + The directives `WYDE', `TETRA' and `OCTA' emit constants of two, + four and eight bytes size respectively. Before anything else + happens for the directive, the current location is aligned to the + respective constant-size boundary. If a label is defined at the + beginning of the line, its value will be that after the alignment. + A single operand can be omitted, defaulting to a zero value + emitted for the directive. Operands can be expressed as strings + (*note Strings::), in which case each character in the string is + emitted as a separate constant of the size indicated by the + directive. + +`PREFIX' + The `PREFIX' directive sets a symbol name prefix to be prepended to + all symbols (except local symbols, *note MMIX-Symbols::), that are + not prefixed with `:', until the next `PREFIX' directive. Such + prefixes accumulate. For example, + PREFIX a + PREFIX b + c IS 0 + defines a symbol `abc' with the value 0. + +`BSPEC' +`ESPEC' + A pair of `BSPEC' and `ESPEC' directives delimit a section of + special contents (without specified semantics). Example: + BSPEC 42 + TETRA 1,2,3 + ESPEC + The single operand to `BSPEC' must be number in the range 0...255. + The `BSPEC' number 80 is used by the GNU binutils implementation. + + +File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent + +Differences to `mmixal' +----------------------- + + The binutils `as' and `ld' combination has a few differences in +function compared to `mmixal' (*note mmixsite::). + + The replacement of a symbol with a GREG-allocated register (*note +GREG-base::) is not handled the exactly same way in `as' as in +`mmixal'. This is apparent in the `mmixal' example file `inout.mms', +where different registers with different offsets, eventually yielding +the same address, are used in the first instruction. This type of +difference should however not affect the function of any program unless +it has specific assumptions about the allocated register number. + + Line numbers (in the `mmo' object format) are currently not +supported. + + Expression operator precedence is not that of mmixal: operator +precedence is that of the C programming language. It's recommended to +use parentheses to explicitly specify wanted operator precedence +whenever more than one type of operators are used. + + The serialize unary operator `&', the fractional division operator +`//', the logical not operator `!' and the modulus operator `%' are not +available. + + Symbols are not global by default, unless the option +`--globalize-symbols' is passed. Use the `.global' directive to +globalize symbols (*note Global::). + + Operand syntax is a bit stricter with `as' than `mmixal'. For +example, you can't say `addu 1,2,3', instead you must write `addu +$1,$2,3'. + + You can't LOC to a lower address than those already visited (i.e. +"backwards"). + + A LOC directive must come before any emitted code. + + Predefined symbols are visible as file-local symbols after use. (In +the ELF file, that is--the linked mmo file has no notion of a file-local +symbol.) + + Some mapping of constant expressions to sections in LOC expressions +is attempted, but that functionality is easily confused and should be +avoided unless compatibility with `mmixal' is required. A LOC +expression to `0x2000000000000000' or higher, maps to the `.data' +section and lower addresses map to the `.text' section (*note +MMIX-loc::). + + The code and data areas are each contiguous. Sparse programs with +far-away LOC directives will take up the same amount of space as a +contiguous program with zeros filled in the gaps between the LOC +directives. If you need sparse programs, you might try and get the +wanted effect with a linker script and splitting up the code parts into +sections (*note Section::). Assembly code for this, to be compatible +with `mmixal', would look something like: + .if 0 + LOC away_expression + .else + .section away,"ax" + .fi + `as' will not execute the LOC directive and `mmixal' ignores the +lines with `.'. This construct can be used generally to help +compatibility. + + Symbols can't be defined twice-not even to the same value. + + Instruction mnemonics are recognized case-insensitive, though the +`IS' and `GREG' pseudo-operations must be specified in upper-case +characters. + + There's no unicode support. + + The following is a list of programs in `mmix.tar.gz', available at +, last +checked with the version dated 2001-08-25 (md5sum +c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do +not assemble with `as': + +`silly.mms' + LOC to a previous address. + +`sim.mms' + Redefines symbol `Done'. + +`test.mms' + Uses the serial operator `&'. + + +File: as.info, Node: MSP430-Dependent, Next: SH-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies + +MSP 430 Dependent Features +========================== + +* Menu: + +* MSP430 Options:: Options +* MSP430 Syntax:: Syntax +* MSP430 Floating Point:: Floating Point +* MSP430 Directives:: MSP 430 Machine Directives +* MSP430 Opcodes:: Opcodes +* MSP430 Profiling Capability:: Profiling Capability + + +File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent + +Options +------- + + `as' has only -m flag which selects the mpu arch. Currently has no +effect. + + +File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent + +Syntax +------ + +* Menu: + +* MSP430-Macros:: Macros +* MSP430-Chars:: Special Characters +* MSP430-Regs:: Register Names +* MSP430-Ext:: Assembler Extensions + + +File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax + +Macros +...... + + The macro syntax used on the MSP 430 is like that described in the +MSP 430 Family Assembler Specification. Normal `as' macros should +still work. + + Additional built-in macros are: + +`llo(exp)' + Extracts least significant word from 32-bit expression 'exp'. + +`lhi(exp)' + Extracts most significant word from 32-bit expression 'exp'. + +`hlo(exp)' + Extracts 3rd word from 64-bit expression 'exp'. + +`hhi(exp)' + Extracts 4rd word from 64-bit expression 'exp'. + + + They normally being used as an immediate source operand. + mov #llo(1), r10 ; == mov #1, r10 + mov #lhi(1), r10 ; == mov #0, r10 + + +File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax + +Special Characters +.................. + + `;' is the line comment character. + + The character `$' in jump instructions indicates current location and +implemented only for TI syntax compatibility. + + +File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax + +Register Names +.............. + + General-purpose registers are represented by predefined symbols of +the form `rN' (for global registers), where N represents a number +between `0' and `15'. The leading letters may be in either upper or +lower case; for example, `r13' and `R7' are both valid register names. + + Register names `PC', `SP' and `SR' cannot be used as register names +and will be treated as variables. Use `r0', `r1', and `r2' instead. + + +File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax + +Assembler Extensions +.................... + +`@rN' + As destination operand being treated as `0(rn)' + +`0(rN)' + As source operand being treated as `@rn' + +`jCOND +N' + Skips next N bytes followed by jump instruction and equivalent to + `jCOND $+N+2' + + + Also, there are some instructions, which cannot be found in other +assemblers. These are branch instructions, which has different opcodes +upon jump distance. They all got PC relative addressing mode. + +`beq label' + A polymorph instruction which is `jeq label' in case if jump + distance within allowed range for cpu's jump instruction. If not, + this unrolls into a sequence of + jne $+6 + br label + +`bne label' + A polymorph instruction which is `jne label' or `jeq +4; br label' + +`blt label' + A polymorph instruction which is `jl label' or `jge +4; br label' + +`bltn label' + A polymorph instruction which is `jn label' or `jn +2; jmp +4; br + label' + +`bltu label' + A polymorph instruction which is `jlo label' or `jhs +2; br label' + +`bge label' + A polymorph instruction which is `jge label' or `jl +4; br label' + +`bgeu label' + A polymorph instruction which is `jhs label' or `jlo +4; br label' + +`bgt label' + A polymorph instruction which is `jeq +2; jge label' or `jeq +6; + jl +4; br label' + +`bgtu label' + A polymorph instruction which is `jeq +2; jhs label' or `jeq +6; + jlo +4; br label' + +`bleu label' + A polymorph instruction which is `jeq label; jlo label' or `jeq + +2; jhs +4; br label' + +`ble label' + A polymorph instruction which is `jeq label; jl label' or `jeq + +2; jge +4; br label' + +`jump label' + A polymorph instruction which is `jmp label' or `br label' + + +File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent + +Floating Point +-------------- + + The MSP 430 family uses IEEE 32-bit floating-point numbers. + + +File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent + +MSP 430 Machine Directives +-------------------------- + +`.file' + This directive is ignored; it is accepted for compatibility with + other MSP 430 assemblers. + + _Warning:_ in other versions of the GNU assembler, `.file' is + used for the directive called `.app-file' in the MSP 430 + support. + +`.line' + This directive is ignored; it is accepted for compatibility with + other MSP 430 assemblers. + +`.arch' + Currently this directive is ignored; it is accepted for + compatibility with other MSP 430 assemblers. + +`.profiler' + This directive instructs assembler to add new profile entry to the + object file. + + + +File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent + +Opcodes +------- + + `as' implements all the standard MSP 430 opcodes. No additional +pseudo-instructions are needed on this family. + + For information on the 430 machine instruction set, see `MSP430 +User's Manual, document slau049b', Texas Instrument, Inc. + + +File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent + +Profiling Capability +-------------------- + + It is a performance hit to use gcc's profiling approach for this +tiny target. Even more - jtag hardware facility does not perform any +profiling functions. However we've got gdb's built-in simulator where +we can do anything. + + We define new section `.profiler' which holds all profiling +information. We define new pseudo operation `.profiler' which will +instruct assembler to add new profile entry to the object file. Profile +should take place at the present address. + + Pseudo operation format: + + `.profiler flags,function_to_profile [, cycle_corrector, extra]' + + where: + + `flags' is a combination of the following characters: + + `s' + function entry + + `x' + function exit + + `i' + function is in init section + + `f' + function is in fini section + + `l' + library call + + `c' + libc standard call + + `d' + stack value demand + + `I' + interrupt service routine + + `P' + prologue start + + `p' + prologue end + + `E' + epilogue start + + `e' + epilogue end + + `j' + long jump / sjlj unwind + + `a' + an arbitrary code fragment + + `t' + extra parameter saved (a constant value like frame size) + +`function_to_profile' + a function address + +`cycle_corrector' + a value which should be added to the cycle counter, zero if + omitted. + +`extra' + any extra parameter, zero if omitted. + + + For example: + .global fxx + .type fxx,@function + fxx: + .LFrameOffset_fxx=0x08 + .profiler "scdP", fxx ; function entry. + ; we also demand stack value to be saved + push r11 + push r10 + push r9 + push r8 + .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point + ; (this is a prologue end) + ; note, that spare var filled with + ; the farme size + mov r15,r8 + ... + .profiler cdE,fxx ; check stack + pop r8 + pop r9 + pop r10 + pop r11 + .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter + ret ; cause 'ret' insn takes 3 cycles + + +File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies + +PDP-11 Dependent Features +========================= + +* Menu: + +* PDP-11-Options:: Options +* PDP-11-Pseudos:: Assembler Directives +* PDP-11-Syntax:: DEC Syntax versus BSD Syntax +* PDP-11-Mnemonics:: Instruction Naming +* PDP-11-Synthetic:: Synthetic Instructions + + +File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent + +Options +------- + + The PDP-11 version of `as' has a rich set of machine dependent +options. + +Code Generation Options +....................... + +`-mpic | -mno-pic' + Generate position-independent (or position-dependent) code. + + The default is to generate position-independent code. + +Instruction Set Extension Options +................................. + + These options enables or disables the use of extensions over the base +line instruction set as introduced by the first PDP-11 CPU: the KA11. +Most options come in two variants: a `-m'EXTENSION that enables +EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. + + The default is to enable all extensions. + +`-mall | -mall-extensions' + Enable all instruction set extensions. + +`-mno-extensions' + Disable all instruction set extensions. + +`-mcis | -mno-cis' + Enable (or disable) the use of the commercial instruction set, + which consists of these instructions: `ADDNI', `ADDN', `ADDPI', + `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC', + `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI', + `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL', + `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI', + `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC', + `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI', + `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'. + +`-mcsm | -mno-csm' + Enable (or disable) the use of the `CSM' instruction. + +`-meis | -mno-eis' + Enable (or disable) the use of the extended instruction set, which + consists of these instructions: `ASHC', `ASH', `DIV', `MARK', + `MUL', `RTT', `SOB' `SXT', and `XOR'. + +`-mfis | -mkev11' +`-mno-fis | -mno-kev11' + Enable (or disable) the use of the KEV11 floating-point + instructions: `FADD', `FDIV', `FMUL', and `FSUB'. + +`-mfpp | -mfpu | -mfp-11' +`-mno-fpp | -mno-fpu | -mno-fp-11' + Enable (or disable) the use of FP-11 floating-point instructions: + `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF', + `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF', + `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST', + `SUBF', and `TSTF'. + +`-mlimited-eis | -mno-limited-eis' + Enable (or disable) the use of the limited extended instruction + set: `MARK', `RTT', `SOB', `SXT', and `XOR'. + + The -mno-limited-eis options also implies -mno-eis. + +`-mmfpt | -mno-mfpt' + Enable (or disable) the use of the `MFPT' instruction. + +`-mmultiproc | -mno-multiproc' + Enable (or disable) the use of multiprocessor instructions: + `TSTSET' and `WRTLCK'. + +`-mmxps | -mno-mxps' + Enable (or disable) the use of the `MFPS' and `MTPS' instructions. + +`-mspl | -mno-spl' + Enable (or disable) the use of the `SPL' instruction. + + Enable (or disable) the use of the microcode instructions: `LDUB', + `MED', and `XFC'. + +CPU Model Options +................. + + These options enable the instruction set extensions supported by a +particular CPU, and disables all other extensions. + +`-mka11' + KA11 CPU. Base line instruction set only. + +`-mkb11' + KB11 CPU. Enable extended instruction set and `SPL'. + +`-mkd11a' + KD11-A CPU. Enable limited extended instruction set. + +`-mkd11b' + KD11-B CPU. Base line instruction set only. + +`-mkd11d' + KD11-D CPU. Base line instruction set only. + +`-mkd11e' + KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'. + +`-mkd11f | -mkd11h | -mkd11q' + KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended + instruction set, `MFPS', and `MTPS'. + +`-mkd11k' + KD11-K CPU. Enable extended instruction set, `LDUB', `MED', + `MFPS', `MFPT', `MTPS', and `XFC'. + +`-mkd11z' + KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS', + `MFPT', `MTPS', and `SPL'. + +`-mf11' + F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and + `MTPS'. + +`-mj11' + J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT', + `MTPS', `SPL', `TSTSET', and `WRTLCK'. + +`-mt11' + T11 CPU. Enable limited extended instruction set, `MFPS', and + `MTPS'. + +Machine Model Options +..................... + + These options enable the instruction set extensions supported by a +particular machine model, and disables all other extensions. + +`-m11/03' + Same as `-mkd11f'. + +`-m11/04' + Same as `-mkd11d'. + +`-m11/05 | -m11/10' + Same as `-mkd11b'. + +`-m11/15 | -m11/20' + Same as `-mka11'. + +`-m11/21' + Same as `-mt11'. + +`-m11/23 | -m11/24' + Same as `-mf11'. + +`-m11/34' + Same as `-mkd11e'. + +`-m11/34a' + Ame as `-mkd11e' `-mfpp'. + +`-m11/35 | -m11/40' + Same as `-mkd11a'. + +`-m11/44' + Same as `-mkd11z'. + +`-m11/45 | -m11/50 | -m11/55 | -m11/70' + Same as `-mkb11'. + +`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' + Same as `-mj11'. + +`-m11/60' + Same as `-mkd11k'. + + +File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent + +Assembler Directives +-------------------- + + The PDP-11 version of `as' has a few machine dependent assembler +directives. + +`.bss' + Switch to the `bss' section. + +`.even' + Align the location counter to an even number. + + +File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent + +PDP-11 Assembly Language Syntax +------------------------------- + + `as' supports both DEC syntax and BSD syntax. The only difference +is that in DEC syntax, a `#' character is used to denote an immediate +constants, while in BSD syntax the character for this purpose is `$'. + + eneral-purpose registers are named `r0' through `r7'. Mnemonic +alternatives for `r6' and `r7' are `sp' and `pc', respectively. + + Floating-point registers are named `ac0' through `ac3', or +alternatively `fr0' through `fr3'. + + Comments are started with a `#' or a `/' character, and extend to +the end of the line. (FIXME: clash with immediates?) + + +File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent + +Instruction Naming +------------------ + + Some instructions have alternative names. + +`BCC' + `BHIS' + +`BCS' + `BLO' + +`L2DR' + `L2D' + +`L3DR' + `L3D' + +`SYS' + `TRAP' + + +File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent + +Synthetic Instructions +---------------------- + + The `JBR' and `J'CC synthetic instructions are not supported yet. + + +File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies + +picoJava Dependent Features +=========================== + +* Menu: + +* PJ Options:: Options + + +File: as.info, Node: PJ Options, Up: PJ-Dependent + +Options +------- + + `as' has two additional command-line options for the picoJava +architecture. +`-ml' + This option selects little endian data output. + +`-mb' + This option selects big endian data output. + + +File: as.info, Node: PPC-Dependent, Next: Sparc-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies + +PowerPC Dependent Features +========================== + +* Menu: + +* PowerPC-Opts:: Options +* PowerPC-Pseudo:: PowerPC Assembler Directives + + +File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent + +Options +------- + + The PowerPC chip family includes several successive levels, using +the same core instruction set, but including a few additional +instructions at each level. There are exceptions to this however. For +details on what instructions each variant supports, please see the +chip's architecture reference manual. + + The following table lists all available PowerPC options. + +`-mpwrx | -mpwr2' + Generate code for POWER/2 (RIOS2). + +`-mpwr' + Generate code for POWER (RIOS1) + +`-m601' + Generate code for PowerPC 601. + +`-mppc, -mppc32, -m603, -m604' + Generate code for PowerPC 603/604. + +`-m403, -m405' + Generate code for PowerPC 403/405. + +`-m440' + Generate code for PowerPC 440. BookE and some 405 instructions. + +`-m7400, -m7410, -m7450, -m7455' + Generate code for PowerPC 7400/7410/7450/7455. + +`-mppc64, -m620' + Generate code for PowerPC 620/625/630. + +`-mppc64bridge' + Generate code for PowerPC 64, including bridge insns. + +`-mbooke64' + Generate code for 64-bit BookE. + +`-mbooke, mbooke32' + Generate code for 32-bit BookE. + +`-maltivec' + Generate code for processors with AltiVec instructions. + +`-mpower4' + Generate code for Power4 architecture. + +`-mcom' + Generate code Power/PowerPC common instructions. + +`-many' + Generate code for any architecture (PWR/PWRX/PPC). + +`-mregnames' + Allow symbolic names for registers. + +`-mno-regnames' + Do not allow symbolic names for registers. + +`-mrelocatable' + Support for GCC's -mrelocatble option. + +`-mrelocatable-lib' + Support for GCC's -mrelocatble-lib option. + +`-memb' + Set PPC_EMB bit in ELF flags. + +`-mlittle, -mlittle-endian' + Generate code for a little endian machine. + +`-mbig, -mbig-endian' + Generate code for a big endian machine. + +`-msolaris' + Generate code for Solaris. + +`-mno-solaris' + Do not generate code for Solaris. + + +File: as.info, Node: PowerPC-Pseudo, Prev: PowerPC-Opts, Up: PPC-Dependent + +PowerPC Assembler Directives +---------------------------- + + A number of assembler directives are available for PowerPC. The +following table is far from complete. + +`.machine "string"' + This directive allows you to change the machine for which code is + generated. `"string"' may be any of the -m cpu selection options + (without the -m) enclosed in double quotes, `"push"', or `"pop"'. + `.machine "push"' saves the currently selected cpu, which may be + restored with `.machine "pop"'. + + +File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies + +Renesas / SuperH SH Dependent Features +====================================== + +* Menu: + +* SH Options:: Options +* SH Syntax:: Syntax +* SH Floating Point:: Floating Point +* SH Directives:: SH Machine Directives +* SH Opcodes:: Opcodes + + +File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent + +Options +------- + + `as' has following command-line options for the Renesas (formerly +Hitachi) / SuperH SH family. + +`-little' + Generate little endian code. + +`-big' + Generate big endian code. + +`-relax' + Alter jump instructions for long displacements. + +`-small' + Align sections to 4 byte boundaries, not 16. + +`-dsp' + Enable sh-dsp insns, and disable sh3e / sh4 insns. + +`-renesas' + Disable optimization with section symbol for compatibility with + Renesas assembler. + +`-isa=sh4 | sh4a' + Specify the sh4 or sh4a instruction set. + +`-isa=dsp' + Enable sh-dsp insns, and disable sh3e / sh4 insns. + +`-isa=fp' + Enable sh2e, sh3e, sh4, and sh4a insn sets. + +`-isa=all' + Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. + + + +File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent + +Syntax +------ + +* Menu: + +* SH-Chars:: Special Characters +* SH-Regs:: Register Names +* SH-Addressing:: Addressing Modes + + +File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax + +Special Characters +.................. + + `!' is the line comment character. + + You can use `;' instead of a newline to separate statements. + + Since `$' has no special meaning, you may use it in symbol names. + + +File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax + +Register Names +.............. + + You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', +`r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and +`r15' to refer to the SH registers. + + The SH also has these control registers: + +`pr' + procedure register (holds return address) + +`pc' + program counter + +`mach' +`macl' + high and low multiply accumulator registers + +`sr' + status register + +`gbr' + global base register + +`vbr' + vector base register (for interrupt vectors) + + +File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax + +Addressing Modes +................ + + `as' understands the following addressing modes for the SH. `RN' in +the following refers to any of the numbered registers, but _not_ the +control registers. + +`RN' + Register direct + +`@RN' + Register indirect + +`@-RN' + Register indirect with pre-decrement + +`@RN+' + Register indirect with post-increment + +`@(DISP, RN)' + Register indirect with displacement + +`@(R0, RN)' + Register indexed + +`@(DISP, GBR)' + `GBR' offset + +`@(R0, GBR)' + GBR indexed + +`ADDR' +`@(DISP, PC)' + PC relative address (for branch or for addressing memory). The + `as' implementation allows you to use the simpler form ADDR + anywhere a PC relative address is called for; the alternate form + is supported for compatibility with other assemblers. + +`#IMM' + Immediate data + + +File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent + +Floating Point +-------------- + + SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). +Other SH groups can use `.float' directive to generate IEEE +floating-point numbers. + + SH2E and SH3E support single-precision floating point calculations as +well as entirely PCAPI compatible emulation of double-precision +floating point calculations. SH2E and SH3E instructions are a subset of +the floating point calculations conforming to the IEEE754 standard. + + In addition to single-precision and double-precision floating-point +operation capability, the on-chip FPU of SH4 has a 128-bit graphic +engine that enables 32-bit floating-point data to be processed 128 bits +at a time. It also supports 4 * 4 array operations and inner product +operations. Also, a superscalar architecture is employed that enables +simultaneous execution of two instructions (including FPU +instructions), providing performance of up to twice that of +conventional architectures at the same frequency. + + +File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent + +SH Machine Directives +--------------------- + +`uaword' +`ualong' + `as' will issue a warning when a misaligned `.word' or `.long' + directive is used. You may use `.uaword' or `.ualong' to indicate + that the value is intentionally misaligned. + + +File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent + +Opcodes +------- + + For detailed information on the SH machine instruction set, see +`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core +Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH). + + `as' implements all the standard SH opcodes. No additional +pseudo-instructions are needed on this family. Note, however, that +because `as' supports a simpler form of PC-relative addressing, you may +simply write (for example) + + mov.l bar,r0 + +where other assemblers might require an explicit displacement to `bar' +from the program counter: + + mov.l @(DISP, PC) + + Here is a summary of SH opcodes: + + Legend: + Rn a numbered register + Rm another numbered register + #imm immediate data + disp displacement + disp8 8-bit displacement + disp12 12-bit displacement + + add #imm,Rn lds.l @Rn+,PR + add Rm,Rn mac.w @Rm+,@Rn+ + addc Rm,Rn mov #imm,Rn + addv Rm,Rn mov Rm,Rn + and #imm,R0 mov.b Rm,@(R0,Rn) + and Rm,Rn mov.b Rm,@-Rn + and.b #imm,@(R0,GBR) mov.b Rm,@Rn + bf disp8 mov.b @(disp,Rm),R0 + bra disp12 mov.b @(disp,GBR),R0 + bsr disp12 mov.b @(R0,Rm),Rn + bt disp8 mov.b @Rm+,Rn + clrmac mov.b @Rm,Rn + clrt mov.b R0,@(disp,Rm) + cmp/eq #imm,R0 mov.b R0,@(disp,GBR) + cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) + cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) + cmp/gt Rm,Rn mov.l Rm,@-Rn + cmp/hi Rm,Rn mov.l Rm,@Rn + cmp/hs Rm,Rn mov.l @(disp,Rn),Rm + cmp/pl Rn mov.l @(disp,GBR),R0 + cmp/pz Rn mov.l @(disp,PC),Rn + cmp/str Rm,Rn mov.l @(R0,Rm),Rn + div0s Rm,Rn mov.l @Rm+,Rn + div0u mov.l @Rm,Rn + div1 Rm,Rn mov.l R0,@(disp,GBR) + exts.b Rm,Rn mov.w Rm,@(R0,Rn) + exts.w Rm,Rn mov.w Rm,@-Rn + extu.b Rm,Rn mov.w Rm,@Rn + extu.w Rm,Rn mov.w @(disp,Rm),R0 + jmp @Rn mov.w @(disp,GBR),R0 + jsr @Rn mov.w @(disp,PC),Rn + ldc Rn,GBR mov.w @(R0,Rm),Rn + ldc Rn,SR mov.w @Rm+,Rn + ldc Rn,VBR mov.w @Rm,Rn + ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) + ldc.l @Rn+,SR mov.w R0,@(disp,GBR) + ldc.l @Rn+,VBR mova @(disp,PC),R0 + lds Rn,MACH movt Rn + lds Rn,MACL muls Rm,Rn + lds Rn,PR mulu Rm,Rn + lds.l @Rn+,MACH neg Rm,Rn + lds.l @Rn+,MACL negc Rm,Rn + + nop stc VBR,Rn + not Rm,Rn stc.l GBR,@-Rn + or #imm,R0 stc.l SR,@-Rn + or Rm,Rn stc.l VBR,@-Rn + or.b #imm,@(R0,GBR) sts MACH,Rn + rotcl Rn sts MACL,Rn + rotcr Rn sts PR,Rn + rotl Rn sts.l MACH,@-Rn + rotr Rn sts.l MACL,@-Rn + rte sts.l PR,@-Rn + rts sub Rm,Rn + sett subc Rm,Rn + shal Rn subv Rm,Rn + shar Rn swap.b Rm,Rn + shll Rn swap.w Rm,Rn + shll16 Rn tas.b @Rn + shll2 Rn trapa #imm + shll8 Rn tst #imm,R0 + shlr Rn tst Rm,Rn + shlr16 Rn tst.b #imm,@(R0,GBR) + shlr2 Rn xor #imm,R0 + shlr8 Rn xor Rm,Rn + sleep xor.b #imm,@(R0,GBR) + stc GBR,Rn xtrct Rm,Rn + stc SR,Rn + + +File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies + +SuperH SH64 Dependent Features +============================== + +* Menu: + +* SH64 Options:: Options +* SH64 Syntax:: Syntax +* SH64 Directives:: SH64 Machine Directives +* SH64 Opcodes:: Opcodes + + +File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent + +Options +------- + +`-isa=sh4 | sh4a' + Specify the sh4 or sh4a instruction set. + +`-isa=dsp' + Enable sh-dsp insns, and disable sh3e / sh4 insns. + +`-isa=fp' + Enable sh2e, sh3e, sh4, and sh4a insn sets. + +`-isa=all' + Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. + +`-isa=shmedia | -isa=shcompact' + Specify the default instruction set. `SHmedia' specifies the + 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes + compatible with previous SH families. The default depends on the + ABI selected; the default for the 64-bit ABI is SHmedia, and the + default for the 32-bit ABI is SHcompact. If neither the ABI nor + the ISA is specified, the default is 32-bit SHcompact. + + Note that the `.mode' pseudo-op is not permitted if the ISA is not + specified on the command line. + +`-abi=32 | -abi=64' + Specify the default ABI. If the ISA is specified and the ABI is + not, the default ABI depends on the ISA, with SHmedia defaulting + to 64-bit and SHcompact defaulting to 32-bit. + + Note that the `.abi' pseudo-op is not permitted if the ABI is not + specified on the command line. When the ABI is specified on the + command line, any `.abi' pseudo-ops in the source must match it. + +`-shcompact-const-crange' + Emit code-range descriptors for constants in SHcompact code + sections. + +`-no-mix' + Disallow SHmedia code in the same section as constants and + SHcompact code. + +`-no-expand' + Do not expand MOVI, PT, PTA or PTB instructions. + +`-expand-pt32' + With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. + + + +File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent + +Syntax +------ + +* Menu: + +* SH64-Chars:: Special Characters +* SH64-Regs:: Register Names +* SH64-Addressing:: Addressing Modes + + +File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax + +Special Characters +.................. + + `!' is the line comment character. + + You can use `;' instead of a newline to separate statements. + + Since `$' has no special meaning, you may use it in symbol names. + + +File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax + +Register Names +.............. + + You can use the predefined symbols `r0' through `r63' to refer to +the SH64 general registers, `cr0' through `cr63' for control registers, +`tr0' through `tr7' for target address registers, `fr0' through `fr63' +for single-precision floating point registers, `dr0' through `dr62' +(even numbered registers only) for double-precision floating point +registers, `fv0' through `fv60' (multiples of four only) for +single-precision floating point vectors, `fp0' through `fp62' (even +numbered registers only) for single-precision floating point pairs, +`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of +single-precision floating point registers, `pc' for the program +counter, and `fpscr' for the floating point status and control register. + + You can also refer to the control registers by the mnemonics `sr', +`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc', +`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'. + + +File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax + +Addressing Modes +................ + + SH64 operands consist of either a register or immediate value. The +immediate value can be a constant or label reference (or portion of a +label reference), as in this example: + + movi 4,r2 + pt function, tr4 + movi (function >> 16) & 65535,r0 + shori function & 65535, r0 + ld.l r0,4,r0 + + Instruction label references can reference labels in either SHmedia +or SHcompact. To differentiate between the two, labels in SHmedia +sections will always have the least significant bit set (i.e. they will +be odd), which SHcompact labels will have the least significant bit +reset (i.e. they will be even). If you need to reference the actual +address of a label, you can use the `datalabel' modifier, as in this +example: + + .long function + .long datalabel function + + In that example, the first longword may or may not have the least +significant bit set depending on whether the label is an SHmedia label +or an SHcompact label. The second longword will be the actual address +of the label, regardless of what type of label it is. + + +File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent + +SH64 Machine Directives +----------------------- + + In addition to the SH directives, the SH64 provides the following +directives: + +`.mode [shmedia|shcompact]' +`.isa [shmedia|shcompact]' + Specify the ISA for the following instructions (the two directives + are equivalent). Note that programs such as `objdump' rely on + symbolic labels to determine when such mode switches occur (by + checking the least significant bit of the label's address), so + such mode/isa changes should always be followed by a label (in + practice, this is true anyway). Note that you cannot use these + directives if you didn't specify an ISA on the command line. + +`.abi [32|64]' + Specify the ABI for the following instructions. Note that you + cannot use this directive unless you specified an ABI on the + command line, and the ABIs specified must match. + +`.uaquad' + Like .uaword and .ualong, this allows you to specify an + intentionally unaligned quadword (64 bit word). + + + +File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent + +Opcodes +------- + + For detailed information on the SH64 machine instruction set, see +`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). + + `as' implements all the standard SH64 opcodes. In addition, the +following pseudo-opcodes may be expanded into one or more alternate +opcodes: + +`movi' + If the value doesn't fit into a standard `movi' opcode, `as' will + replace the `movi' with a sequence of `movi' and `shori' opcodes. + +`pt' + This expands to a sequence of `movi' and `shori' opcode, followed + by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on + the label referenced. + + + +File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies + +SPARC Dependent Features +======================== + +* Menu: + +* Sparc-Opts:: Options +* Sparc-Aligned-Data:: Option to enforce aligned data +* Sparc-Float:: Floating Point +* Sparc-Directives:: Sparc Machine Directives + + +File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent + +Options +------- + + The SPARC chip family includes several successive levels, using the +same core instruction set, but including a few additional instructions +at each level. There are exceptions to this however. For details on +what instructions each variant supports, please see the chip's +architecture reference manual. + + By default, `as' assumes the core instruction set (SPARC v6), but +"bumps" the architecture level as needed: it switches to successively +higher architectures as it encounters instructions that only exist in +the higher levels. + + If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump +passed sparclite by default, an option must be passed to enable the v9 +instructions. + + GAS treats sparclite as being compatible with v8, unless an +architecture is explicitly requested. SPARC v9 is always incompatible +with sparclite. + +`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' +`-Av8plus | -Av8plusa | -Av9 | -Av9a' + Use one of the `-A' options to select one of the SPARC + architectures explicitly. If you select an architecture + explicitly, `as' reports a fatal error if it encounters an + instruction or feature requiring an incompatible or higher level. + + `-Av8plus' and `-Av8plusa' select a 32 bit environment. + + `-Av9' and `-Av9a' select a 64 bit environment and are not + available unless GAS is explicitly configured with 64 bit + environment support. + + `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with + UltraSPARC extensions. + +`-xarch=v8plus | -xarch=v8plusa' + For compatibility with the Solaris v9 assembler. These options are + equivalent to -Av8plus and -Av8plusa, respectively. + +`-bump' + Warn whenever it is necessary to switch to another level. If an + architecture level is explicitly requested, GAS will not issue + warnings until that level is reached, and will then bump the level + as required (except between incompatible levels). + +`-32 | -64' + Select the word size, either 32 bits or 64 bits. These options + are only available with the ELF object file format, and require + that the necessary BFD support has been included. + + +File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Float, Prev: Sparc-Opts, Up: Sparc-Dependent + +Enforcing aligned data +---------------------- + + SPARC GAS normally permits data to be misaligned. For example, it +permits the `.long' pseudo-op to be used on a byte boundary. However, +the native SunOS and Solaris assemblers issue an error when they see +misaligned data. + + You can use the `--enforce-aligned-data' option to make SPARC GAS +also issue an error about misaligned data, just as the SunOS and Solaris +assemblers do. + + The `--enforce-aligned-data' option is not the default because gcc +issues misaligned data pseudo-ops when it initializes certain packed +data structures (structures defined using the `packed' attribute). You +may have to assemble with GAS in order to initialize packed data +structures in your own code. + + +File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent + +Floating Point +-------------- + + The Sparc uses IEEE floating-point numbers. + + +File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent + +Sparc Machine Directives +------------------------ + + The Sparc version of `as' supports the following additional machine +directives: + +`.align' + This must be followed by the desired alignment in bytes. + +`.common' + This must be followed by a symbol name, a positive number, and + `"bss"'. This behaves somewhat like `.comm', but the syntax is + different. + +`.half' + This is functionally identical to `.short'. + +`.nword' + On the Sparc, the `.nword' directive produces native word sized + value, ie. if assembling with -32 it is equivalent to `.word', if + assembling with -64 it is equivalent to `.xword'. + +`.proc' + This directive is ignored. Any text following it on the same line + is also ignored. + +`.register' + This directive declares use of a global application or system + register. It must be followed by a register name %g2, %g3, %g6 or + %g7, comma and the symbol name for that register. If symbol name + is `#scratch', it is a scratch register, if it is `#ignore', it + just suppresses any errors about using undeclared global register, + but does not emit any information about it into the object file. + This can be useful e.g. if you save the register before use and + restore it after. + +`.reserve' + This must be followed by a symbol name, a positive number, and + `"bss"'. This behaves somewhat like `.lcomm', but the syntax is + different. + +`.seg' + This must be followed by `"text"', `"data"', or `"data1"'. It + behaves like `.text', `.data', or `.data 1'. + +`.skip' + This is functionally identical to the `.space' directive. + +`.word' + On the Sparc, the `.word' directive produces 32 bit values, + instead of the 16 bit values it produces on many other machines. + +`.xword' + On the Sparc V9 processor, the `.xword' directive produces 64 bit + values. + + +File: as.info, Node: TIC54X-Dependent, Next: V850-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies + +TIC54X Dependent Features +========================= + +* Menu: + +* TIC54X-Opts:: Command-line Options +* TIC54X-Block:: Blocking +* TIC54X-Env:: Environment Settings +* TIC54X-Constants:: Constants Syntax +* TIC54X-Subsyms:: String Substitution +* TIC54X-Locals:: Local Label Syntax +* TIC54X-Builtins:: Builtin Assembler Math Functions +* TIC54X-Ext:: Extended Addressing Support +* TIC54X-Directives:: Directives +* TIC54X-Macros:: Macro Features +* TIC54X-MMRegs:: Memory-mapped Registers + + +File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent + +Options +------- + + The TMS320C54x version of `as' has a few machine-dependent options. + + You can use the `-mfar-mode' option to enable extended addressing +mode. All addresses will be assumed to be > 16 bits, and the +appropriate relocation types will be used. This option is equivalent +to using the `.far_mode' directive in the assembly code. If you do not +use the `-mfar-mode' option, all references will be assumed to be 16 +bits. This option may be abbreviated to `-mf'. + + You can use the `-mcpu' option to specify a particular CPU. This +option is equivalent to using the `.version' directive in the assembly +code. For recognized CPU codes, see *Note `.version': +TIC54X-Directives. The default CPU version is `542'. + + You can use the `-merrors-to-file' option to redirect error output +to a file (this provided for those deficient environments which don't +provide adequate output redirection). This option may be abbreviated to +`-me'. + + +File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent + +Blocking +-------- + + A blocked section or memory block is guaranteed not to cross the +blocking boundary (usually a page, or 128 words) if it is smaller than +the blocking size, or to start on a page boundary if it is larger than +the blocking size. + + +File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent + +Environment Settings +-------------------- + + `C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are +added to the list of directories normally searched for source and +include files. `C54XDSP_DIR' will override `A_DIR'. + + +File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent + +Constants Syntax +---------------- + + The TIC54X version of `as' allows the following additional constant +formats, using a suffix to indicate the radix: + + Binary `000000B, 011000b' + Octal `10Q, 224q' + Hexadecimal `45h, 0FH' + + +File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent + +String Substitution +------------------- + + A subset of allowable symbols (which we'll call subsyms) may be +assigned arbitrary string values. This is roughly equivalent to C +preprocessor #define macros. When `as' encounters one of these +symbols, the symbol is replaced in the input stream by its string value. +Subsym names *must* begin with a letter. + + Subsyms may be defined using the `.asg' and `.eval' directives +(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives. + + Expansion is recursive until a previously encountered symbol is +seen, at which point substitution stops. + + In this example, x is replaced with SYM2; SYM2 is replaced with +SYM1, and SYM1 is replaced with x. At this point, x has already been +encountered and the substitution stops. + + .asg "x",SYM1 + .asg "SYM1",SYM2 + .asg "SYM2",x + add x,a ; final code assembled is "add x, a" + + Macro parameters are converted to subsyms; a side effect of this is +the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms +defined within a macro will have global scope, unless the `.var' +directive is used to identify the subsym as a local macro variable +*note `.var': TIC54X-Directives.. + + Substitution may be forced in situations where replacement might be +ambiguous by placing colons on either side of the subsym. The following +code: + + .eval "10",x + LAB:X: add #x, a + + When assembled becomes: + + LAB10 add #10, a + + Smaller parts of the string assigned to a subsym may be accessed with +the following syntax: + +``:SYMBOL(CHAR_INDEX):'' + Evaluates to a single-character string, the character at + CHAR_INDEX. + +``:SYMBOL(START,LENGTH):'' + Evaluates to a substring of SYMBOL beginning at START with length + LENGTH. + + +File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent + +Local Labels +------------ + + Local labels may be defined in two ways: + + * $N, where N is a decimal number between 0 and 9 + + * LABEL?, where LABEL is any legal symbol name. + + Local labels thus defined may be redefined or automatically +generated. The scope of a local label is based on when it may be +undefined or reset. This happens when one of the following situations +is encountered: + + * .newblock directive *note `.newblock': TIC54X-Directives. + + * The current section is changed (.sect, .text, or .data) + + * Entering or leaving an included file + + * The macro scope where the label was defined is exited + + +File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent + +Math Builtins +------------- + + The following built-in functions may be used to generate a +floating-point value. All return a floating-point value except `$cvi', +`$int', and `$sgn', which return an integer value. + +``$acos(EXPR)'' + Returns the floating point arccosine of EXPR. + +``$asin(EXPR)'' + Returns the floating point arcsine of EXPR. + +``$atan(EXPR)'' + Returns the floating point arctangent of EXPR. + +``$atan2(EXPR1,EXPR2)'' + Returns the floating point arctangent of EXPR1 / EXPR2. + +``$ceil(EXPR)'' + Returns the smallest integer not less than EXPR as floating point. + +``$cosh(EXPR)'' + Returns the floating point hyperbolic cosine of EXPR. + +``$cos(EXPR)'' + Returns the floating point cosine of EXPR. + +``$cvf(EXPR)'' + Returns the integer value EXPR converted to floating-point. + +``$cvi(EXPR)'' + Returns the floating point value EXPR converted to integer. + +``$exp(EXPR)'' + Returns the floating point value e ^ EXPR. + +``$fabs(EXPR)'' + Returns the floating point absolute value of EXPR. + +``$floor(EXPR)'' + Returns the largest integer that is not greater than EXPR as + floating point. + +``$fmod(EXPR1,EXPR2)'' + Returns the floating point remainder of EXPR1 / EXPR2. + +``$int(EXPR)'' + Returns 1 if EXPR evaluates to an integer, zero otherwise. + +``$ldexp(EXPR1,EXPR2)'' + Returns the floating point value EXPR1 * 2 ^ EXPR2. + +``$log10(EXPR)'' + Returns the base 10 logarithm of EXPR. + +``$log(EXPR)'' + Returns the natural logarithm of EXPR. + +``$max(EXPR1,EXPR2)'' + Returns the floating point maximum of EXPR1 and EXPR2. + +``$min(EXPR1,EXPR2)'' + Returns the floating point minimum of EXPR1 and EXPR2. + +``$pow(EXPR1,EXPR2)'' + Returns the floating point value EXPR1 ^ EXPR2. + +``$round(EXPR)'' + Returns the nearest integer to EXPR as a floating point number. + +``$sgn(EXPR)'' + Returns -1, 0, or 1 based on the sign of EXPR. + +``$sin(EXPR)'' + Returns the floating point sine of EXPR. + +``$sinh(EXPR)'' + Returns the floating point hyperbolic sine of EXPR. + +``$sqrt(EXPR)'' + Returns the floating point square root of EXPR. + +``$tan(EXPR)'' + Returns the floating point tangent of EXPR. + +``$tanh(EXPR)'' + Returns the floating point hyperbolic tangent of EXPR. + +``$trunc(EXPR)'' + Returns the integer value of EXPR truncated towards zero as + floating point. + + + +File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent + +Extended Addressing +------------------- + + The `LDX' pseudo-op is provided for loading the extended addressing +bits of a label or address. For example, if an address `_label' resides +in extended program memory, the value of `_label' may be loaded as +follows: + ldx #_label,16,a ; loads extended bits of _label + or #_label,a ; loads lower 16 bits of _label + bacc a ; full address is in accumulator A + + +File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent + +Directives +---------- + +`.align [SIZE]' +`.even' + Align the section program counter on the next boundary, based on + SIZE. SIZE may be any power of 2. `.even' is equivalent to + `.align' with a SIZE of 2. + `1' + Align SPC to word boundary + + `2' + Align SPC to longword boundary (same as .even) + + `128' + Align SPC to page boundary + +`.asg STRING, NAME' + Assign NAME the string STRING. String replacement is performed on + STRING before assignment. + +`.eval STRING, NAME' + Evaluate the contents of string STRING and assign the result as a + string to the subsym NAME. String replacement is performed on + STRING before assignment. + +`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' + Reserve space for SYMBOL in the .bss section. SIZE is in words. + If present, BLOCKING_FLAG indicates the allocated space should be + aligned on a page boundary if it would otherwise cross a page + boundary. If present, ALIGNMENT_FLAG causes the assembler to + allocate SIZE on a long word boundary. + +`.byte VALUE [,...,VALUE_N]' +`.ubyte VALUE [,...,VALUE_N]' +`.char VALUE [,...,VALUE_N]' +`.uchar VALUE [,...,VALUE_N]' + Place one or more bytes into consecutive words of the current + section. The upper 8 bits of each word is zero-filled. If a + label is used, it points to the word allocated for the first byte + encountered. + +`.clink ["SECTION_NAME"]' + Set STYP_CLINK flag for this section, which indicates to the + linker that if no symbols from this section are referenced, the + section should not be included in the link. If SECTION_NAME is + omitted, the current section is used. + +`.c_mode' + TBD. + +`.copy "FILENAME" | FILENAME' +`.include "FILENAME" | FILENAME' + Read source statements from FILENAME. The normal include search + path is used. Normally .copy will cause statements from the + included file to be printed in the assembly listing and .include + will not, but this distinction is not currently implemented. + +`.data' + Begin assembling code into the .data section. + +`.double VALUE [,...,VALUE_N]' +`.ldouble VALUE [,...,VALUE_N]' +`.float VALUE [,...,VALUE_N]' +`.xfloat VALUE [,...,VALUE_N]' + Place an IEEE single-precision floating-point representation of + one or more floating-point values into the current section. All + but `.xfloat' align the result on a longword boundary. Values are + stored most-significant word first. + +`.drlist' +`.drnolist' + Control printing of directives to the listing file. Ignored. + +`.emsg STRING' +`.mmsg STRING' +`.wmsg STRING' + Emit a user-defined error, message, or warning, respectively. + +`.far_mode' + Use extended addressing when assembling statements. This should + appear only once per file, and is equivalent to the -mfar-mode + option *note `-mfar-mode': TIC54X-Opts.. + +`.fclist' +`.fcnolist' + Control printing of false conditional blocks to the listing file. + +`.field VALUE [,SIZE]' + Initialize a bitfield of SIZE bits in the current section. If + VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 + bits. If VALUE does not fit into SIZE bits, the value will be + truncated. Successive `.field' directives will pack starting at + the current word, filling the most significant bits first, and + aligning to the start of the next word if the field size does not + fit into the space remaining in the current word. A `.align' + directive with an operand of 1 will force the next `.field' + directive to begin packing into a new word. If a label is used, it + points to the word that contains the specified field. + +`.global SYMBOL [,...,SYMBOL_N]' +`.def SYMBOL [,...,SYMBOL_N]' +`.ref SYMBOL [,...,SYMBOL_N]' + `.def' nominally identifies a symbol defined in the current file + and availalbe to other files. `.ref' identifies a symbol used in + the current file but defined elsewhere. Both map to the standard + `.global' directive. + +`.half VALUE [,...,VALUE_N]' +`.uhalf VALUE [,...,VALUE_N]' +`.short VALUE [,...,VALUE_N]' +`.ushort VALUE [,...,VALUE_N]' +`.int VALUE [,...,VALUE_N]' +`.uint VALUE [,...,VALUE_N]' +`.word VALUE [,...,VALUE_N]' +`.uword VALUE [,...,VALUE_N]' + Place one or more values into consecutive words of the current + section. If a label is used, it points to the word allocated for + the first value encountered. + +`.label SYMBOL' + Define a special SYMBOL to refer to the load time address of the + current section program counter. + +`.length' +`.width' + Set the page length and width of the output listing file. Ignored. + +`.list' +`.nolist' + Control whether the source listing is printed. Ignored. + +`.long VALUE [,...,VALUE_N]' +`.ulong VALUE [,...,VALUE_N]' +`.xlong VALUE [,...,VALUE_N]' + Place one or more 32-bit values into consecutive words in the + current section. The most significant word is stored first. + `.long' and `.ulong' align the result on a longword boundary; + `xlong' does not. + +`.loop [COUNT]' +`.break [CONDITION]' +`.endloop' + Repeatedly assemble a block of code. `.loop' begins the block, and + `.endloop' marks its termination. COUNT defaults to 1024, and + indicates the number of times the block should be repeated. + `.break' terminates the loop so that assembly begins after the + `.endloop' directive. The optional CONDITION will cause the loop + to terminate only if it evaluates to zero. + +`MACRO_NAME .macro [PARAM1][,...PARAM_N]' +`[.mexit]' +`.endm' + See the section on macros for more explanation (*Note + TIC54X-Macros::. + +`.mlib "FILENAME" | FILENAME' + Load the macro library FILENAME. FILENAME must be an archived + library (BFD ar-compatible) of text files, expected to contain + only macro definitions. The standard include search path is used. + +`.mlist' + +`.mnolist' + Control whether to include macro and loop block expansions in the + listing output. Ignored. + +`.mmregs' + Define global symbolic names for the 'c54x registers. Supposedly + equivalent to executing `.set' directives for each register with + its memory-mapped value, but in reality is provided only for + compatibility and does nothing. + +`.newblock' + This directive resets any TIC54X local labels currently defined. + Normal `as' local labels are unaffected. + +`.option OPTION_LIST' + Set listing options. Ignored. + +`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' + Designate SECTION_NAME for blocking. Blocking guarantees that a + section will start on a page boundary (128 words) if it would + otherwise cross a page boundary. Only initialized sections may be + designated with this directive. See also *Note TIC54X-Block::. + +`.sect "SECTION_NAME"' + Define a named initialized section and make it the current section. + +`SYMBOL .set "VALUE"' +`SYMBOL .equ "VALUE"' + Equate a constant VALUE to a SYMBOL, which is placed in the symbol + table. SYMBOL may not be previously defined. + +`.space SIZE_IN_BITS' +`.bes SIZE_IN_BITS' + Reserve the given number of bits in the current section and + zero-fill them. If a label is used with `.space', it points to the + *first* word reserved. With `.bes', the label points to the + *last* word reserved. + +`.sslist' +`.ssnolist' + Controls the inclusion of subsym replacement in the listing + output. Ignored. + +`.string "STRING" [,...,"STRING_N"]' +`.pstring "STRING" [,...,"STRING_N"]' + Place 8-bit characters from STRING into the current section. + `.string' zero-fills the upper 8 bits of each word, while + `.pstring' puts two characters into each word, filling the + most-significant bits first. Unused space is zero-filled. If a + label is used, it points to the first word initialized. + +`[STAG] .struct [OFFSET]' +`[NAME_1] element [COUNT_1]' +`[NAME_2] element [COUNT_2]' +`[TNAME] .tag STAGX [TCOUNT]' +`...' +`[NAME_N] element [COUNT_N]' +`[SSIZE] .endstruct' +`LABEL .tag [STAG]' + Assign symbolic offsets to the elements of a structure. STAG + defines a symbol to use to reference the structure. OFFSET + indicates a starting value to use for the first element + encountered; otherwise it defaults to zero. Each element can have + a named offset, NAME, which is a symbol assigned the value of the + element's offset into the structure. If STAG is missing, these + become global symbols. COUNT adjusts the offset that many times, + as if `element' were an array. `element' may be one of `.byte', + `.word', `.long', `.float', or any equivalent of those, and the + structure offset is adjusted accordingly. `.field' and `.string' + are also allowed; the size of `.field' is one bit, and `.string' + is considered to be one word in size. Only element descriptors, + structure/union tags, `.align' and conditional assembly directives + are allowed within `.struct'/`.endstruct'. `.align' aligns member + offsets to word boundaries only. SSIZE, if provided, will always + be assigned the size of the structure. + + The `.tag' directive, in addition to being used to define a + structure/union element within a structure, may be used to apply a + structure to a symbol. Once applied to LABEL, the individual + structure elements may be applied to LABEL to produce the desired + offsets using LABEL as the structure base. + +`.tab' + Set the tab size in the output listing. Ignored. + +`[UTAG] .union' +`[NAME_1] element [COUNT_1]' +`[NAME_2] element [COUNT_2]' +`[TNAME] .tag UTAGX[,TCOUNT]' +`...' +`[NAME_N] element [COUNT_N]' +`[USIZE] .endstruct' +`LABEL .tag [UTAG]' + Similar to `.struct', but the offset after each element is reset to + zero, and the USIZE is set to the maximum of all defined elements. + Starting offset for the union is always zero. + +`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' + Reserve space for variables in a named, uninitialized section + (similar to .bss). `.usect' allows definitions sections + independent of .bss. SYMBOL points to the first location reserved + by this allocation. The symbol may be used as a variable name. + SIZE is the allocated size in words. BLOCKING_FLAG indicates + whether to block this section on a page boundary (128 words) + (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the + section should be longword-aligned. + +`.var SYM[,..., SYM_N]' + Define a subsym to be a local variable within a macro. See *Note + TIC54X-Macros::. + +`.version VERSION' + Set which processor to build instructions for. Though the + following values are accepted, the op is ignored. + `541' + `542' + `543' + `545' + `545LP' + `546LP' + `548' + `549' + + +File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent + +Macros +------ + + Macros do not require explicit dereferencing of arguments (i.e. +\ARG). + + During macro expansion, the macro parameters are converted to +subsyms. If the number of arguments passed the macro invocation +exceeds the number of parameters defined, the last parameter is +assigned the string equivalent of all remaining arguments. If fewer +arguments are given than parameters, the missing parameters are +assigned empty strings. To include a comma in an argument, you must +enclose the argument in quotes. + + The following built-in subsym functions allow examination of the +string value of subsyms (or ordinary strings). The arguments are +strings unless otherwise indicated (subsyms passed as args will be +replaced by the strings they represent). +``$symlen(STR)'' + Returns the length of STR. + +``$symcmp(STR1,STR2)'' + Returns 0 if STR1 == STR2, non-zero otherwise. + +``$firstch(STR,CH)'' + Returns index of the first occurrence of character constant CH in + STR. + +``$lastch(STR,CH)'' + Returns index of the last occurrence of character constant CH in + STR. + +``$isdefed(SYMBOL)'' + Returns zero if the symbol SYMBOL is not in the symbol table, + non-zero otherwise. + +``$ismember(SYMBOL,LIST)'' + Assign the first member of comma-separated string LIST to SYMBOL; + LIST is reassigned the remainder of the list. Returns zero if + LIST is a null string. Both arguments must be subsyms. + +``$iscons(EXPR)'' + Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, + 4 if a character, 5 if decimal, and zero if not an integer. + +``$isname(NAME)'' + Returns 1 if NAME is a valid symbol name, zero otherwise. + +``$isreg(REG)'' + Returns 1 if REG is a valid predefined register name (AR0-AR7 + only). + +``$structsz(STAG)'' + Returns the size of the structure or union represented by STAG. + +``$structacc(STAG)'' + Returns the reference point of the structure or union represented + by STAG. Always returns zero. + + + +File: as.info, Node: TIC54X-MMRegs, Prev: TIC54X-Macros, Up: TIC54X-Dependent + +Memory-mapped Registers +----------------------- + + The following symbols are recognized as memory-mapped registers: + + + +File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies + +Z8000 Dependent Features +======================== + + The Z8000 as supports both members of the Z8000 family: the +unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with +24 bit addresses. + + When the assembler is in unsegmented mode (specified with the +`unsegm' directive), an address takes up one word (16 bit) sized +register. When the assembler is in segmented mode (specified with the +`segm' directive), a 24-bit address takes up a long (32 bit) register. +*Note Assembler Directives for the Z8000: Z8000 Directives, for a list +of other Z8000 specific assembler directives. + +* Menu: + +* Z8000 Options:: Command-line options for the Z8000 +* Z8000 Syntax:: Assembler syntax for the Z8000 +* Z8000 Directives:: Special directives for the Z8000 +* Z8000 Opcodes:: Opcodes + + +File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent + +Options +------- + +`-z8001' + Generate segmented code by default. + +`-z8002' + Generate unsegmented code by default. + + +File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent + +Syntax +------ + +* Menu: + +* Z8000-Chars:: Special Characters +* Z8000-Regs:: Register Names +* Z8000-Addressing:: Addressing Modes + + +File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax + +Special Characters +.................. + + `!' is the line comment character. + + You can use `;' instead of a newline to separate statements. + + +File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax + +Register Names +.............. + + The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can +refer to different sized groups of registers by register number, with +the prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' +for 64 bit registers. You can also refer to the contents of the first +eight (of the sixteen 16 bit registers) by bytes. They are named `rlN' +and `rhN'. + +_byte registers_ + rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 + rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 + +_word registers_ + r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 + +_long word registers_ + rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 + +_quad word registers_ + rq0 rq4 rq8 rq12 + + +File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax + +Addressing Modes +................ + + as understands the following addressing modes for the Z8000: + +`rlN' +`rhN' +`rN' +`rrN' +`rqN' + Register direct: 8bit, 16bit, 32bit, and 64bit registers. + +`@rN' +`@rrN' + Indirect register: @rrN in segmented mode, @rN in unsegmented + mode. + +`ADDR' + Direct: the 16 bit or 24 bit address (depending on whether the + assembler is in segmented or unsegmented mode) of the operand is + in the instruction. + +`address(rN)' + Indexed: the 16 or 24 bit address is added to the 16 bit register + to produce the final address in memory of the operand. + +`rN(#IMM)' +`rrN(#IMM)' + Base Address: the 16 or 24 bit register is added to the 16 bit sign + extended immediate displacement to produce the final address in + memory of the operand. + +`rN(rM)' +`rrN(rM)' + Base Index: the 16 or 24 bit register rN or rrN is added to the + sign extended 16 bit index register rM to produce the final + address in memory of the operand. + +`#XX' + Immediate data XX. + + +File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent + +Assembler Directives for the Z8000 +---------------------------------- + + The Z8000 port of as includes additional assembler directives, for +compatibility with other Z8000 assemblers. These do not begin with `.' +(unlike the ordinary as directives). + +`segm' +`.z8001' + Generate code for the segmented Z8001. + +`unsegm' +`.z8002' + Generate code for the unsegmented Z8002. + +`name' + Synonym for `.file' + +`global' + Synonym for `.global' + +`wval' + Synonym for `.word' + +`lval' + Synonym for `.long' + +`bval' + Synonym for `.byte' + +`sval' + Assemble a string. `sval' expects one string literal, delimited by + single quotes. It assembles each byte of the string into + consecutive addresses. You can use the escape sequence `%XX' + (where XX represents a two-digit hexadecimal number) to represent + the character whose ASCII value is XX. Use this feature to + describe single quote and other characters that may not appear in + string literals as themselves. For example, the C statement + `char *a = "he said \"it's 50% off\"";' is represented in Z8000 + assembly language (shown with the assembler output in hex at the + left) as + + 68652073 sval 'he said %22it%27s 50%25 off%22%00' + 61696420 + 22697427 + 73203530 + 25206F66 + 662200 + +`rsect' + synonym for `.section' + +`block' + synonym for `.space' + +`even' + special case of `.align'; aligns output to even byte boundary. + + +File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent + +Opcodes +------- + + For detailed information on the Z8000 machine instruction set, see +`Z8000 Technical Manual'. + + The following table summarizes the opcodes and their arguments: + + rs 16 bit source register + rd 16 bit destination register + rbs 8 bit source register + rbd 8 bit destination register + rrs 32 bit source register + rrd 32 bit destination register + rqs 64 bit source register + rqd 64 bit destination register + addr 16/24 bit address + imm immediate data + + adc rd,rs clrb addr cpsir @rd,@rs,rr,cc + adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc + add rd,@rs clrb rbd dab rbd + add rd,addr com @rd dbjnz rbd,disp7 + add rd,addr(rs) com addr dec @rd,imm4m1 + add rd,imm16 com addr(rd) dec addr(rd),imm4m1 + add rd,rs com rd dec addr,imm4m1 + addb rbd,@rs comb @rd dec rd,imm4m1 + addb rbd,addr comb addr decb @rd,imm4m1 + addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 + addb rbd,imm8 comb rbd decb addr,imm4m1 + addb rbd,rbs comflg flags decb rbd,imm4m1 + addl rrd,@rs cp @rd,imm16 di i2 + addl rrd,addr cp addr(rd),imm16 div rrd,@rs + addl rrd,addr(rs) cp addr,imm16 div rrd,addr + addl rrd,imm32 cp rd,@rs div rrd,addr(rs) + addl rrd,rrs cp rd,addr div rrd,imm16 + and rd,@rs cp rd,addr(rs) div rrd,rs + and rd,addr cp rd,imm16 divl rqd,@rs + and rd,addr(rs) cp rd,rs divl rqd,addr + and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) + and rd,rs cpb addr(rd),imm8 divl rqd,imm32 + andb rbd,@rs cpb addr,imm8 divl rqd,rrs + andb rbd,addr cpb rbd,@rs djnz rd,disp7 + andb rbd,addr(rs) cpb rbd,addr ei i2 + andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs + andb rbd,rbs cpb rbd,imm8 ex rd,addr + bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) + bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs + bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs + bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr + bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) + bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs + bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 + bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 + bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 + bitb rbd,rs cpl rrd,@rs ext8f imm8 + bpt cpl rrd,addr exts rrd + call @rd cpl rrd,addr(rs) extsb rd + call addr cpl rrd,imm32 extsl rqd + call addr(rd) cpl rrd,rrs halt + calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs + clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 + clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs + clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 + clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 + clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 + inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) + inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 + incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs + incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs + incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr + incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) + ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 + indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs + inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd + inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr + iret ldib @rd,@rs,rr neg addr(rd) + jp cc,@rd ldir @rd,@rs,rr neg rd + jp cc,addr ldirb @rd,@rs,rr negb @rd + jp cc,addr(rd) ldk rd,imm4 negb addr + jr cc,disp8 ldl @rd,rrs negb addr(rd) + ld @rd,imm16 ldl addr(rd),rrs negb rbd + ld @rd,rs ldl addr,rrs nop + ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs + ld addr(rd),rs ldl rd(rx),rrs or rd,addr + ld addr,imm16 ldl rrd,@rs or rd,addr(rs) + ld addr,rs ldl rrd,addr or rd,imm16 + ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs + ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs + ld rd,@rs ldl rrd,rrs orb rbd,addr + ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) + ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 + ld rd,imm16 ldm @rd,rs,n orb rbd,rbs + ld rd,rs ldm addr(rd),rs,n out @rd,rs + ld rd,rs(imm16) ldm addr,rs,n out imm16,rs + ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs + lda rd,addr ldm rd,addr(rs),n outb imm16,rbs + lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra + lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba + lda rd,rs(rx) ldps addr outib @rd,@rs,ra + ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra + ldb @rd,imm8 ldr disp16,rs pop @rd,@rs + ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs + ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs + ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs + ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs + ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs + ldb rbd,@rs mbit popl addr,@rs + ldb rbd,addr mreq rd popl rrd,@rs + ldb rbd,addr(rs) mres push @rd,@rs + ldb rbd,imm8 mset push @rd,addr + ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) + ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 + push @rd,rs set addr,imm4 subl rrd,imm32 + pushl @rd,@rs set rd,imm4 subl rrd,rrs + pushl @rd,addr set rd,rs tcc cc,rd + pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd + pushl @rd,rrs setb addr(rd),imm4 test @rd + res @rd,imm4 setb addr,imm4 test addr + res addr(rd),imm4 setb rbd,imm4 test addr(rd) + res addr,imm4 setb rbd,rs test rd + res rd,imm4 setflg imm4 testb @rd + res rd,rs sinb rbd,imm16 testb addr + resb @rd,imm4 sinb rd,imm16 testb addr(rd) + resb addr(rd),imm4 sind @rd,@rs,ra testb rbd + resb addr,imm4 sindb @rd,@rs,rba testl @rd + resb rbd,imm4 sinib @rd,@rs,ra testl addr + resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) + resflg imm4 sla rd,imm8 testl rrd + ret cc slab rbd,imm8 trdb @rd,@rs,rba + rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba + rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr + rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr + rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr + rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr + rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr + rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr + rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd + rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr + rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) + rsvd36 sra rd,imm8 tset rd + rsvd38 srab rbd,imm8 tsetb @rd + rsvd78 sral rrd,imm8 tsetb addr + rsvd7e srl rd,imm8 tsetb addr(rd) + rsvd9d srlb rbd,imm8 tsetb rbd + rsvd9f srll rrd,imm8 xor rd,@rs + rsvdb9 sub rd,@rs xor rd,addr + rsvdbf sub rd,addr xor rd,addr(rs) + sbc rd,rs sub rd,addr(rs) xor rd,imm16 + sbcb rbd,rbs sub rd,imm16 xor rd,rs + sc imm8 sub rd,rs xorb rbd,@rs + sda rd,rs subb rbd,@rs xorb rbd,addr + sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) + sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 + sdl rd,rs subb rbd,imm8 xorb rbd,rbs + sdlb rbd,rs subb rbd,rbs xorb rbd,rbs + sdll rrd,rs subl rrd,@rs + set @rd,imm4 subl rrd,addr + set addr(rd),imm4 subl rrd,addr(rs) + + +File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies + +VAX Dependent Features +====================== + +* Menu: + +* VAX-Opts:: VAX Command-Line Options +* VAX-float:: VAX Floating Point +* VAX-directives:: Vax Machine Directives +* VAX-opcodes:: VAX Opcodes +* VAX-branch:: VAX Branch Improvement +* VAX-operands:: VAX Operands +* VAX-no:: Not Supported on VAX + + +File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent + +VAX Command-Line Options +------------------------ + + The Vax version of `as' accepts any of the following options, gives +a warning message that the option was ignored and proceeds. These +options are for compatibility with scripts designed for other people's +assemblers. + +``-D' (Debug)' +``-S' (Symbol Table)' +``-T' (Token Trace)' + These are obsolete options used to debug old assemblers. + +``-d' (Displacement size for JUMPs)' + This option expects a number following the `-d'. Like options + that expect filenames, the number may immediately follow the `-d' + (old standard) or constitute the whole of the command line + argument that follows `-d' (GNU standard). + +``-V' (Virtualize Interpass Temporary File)' + Some other assemblers use a temporary file. This option commanded + them to keep the information in active memory rather than in a + disk file. `as' always does this, so this option is redundant. + +``-J' (JUMPify Longer Branches)' + Many 32-bit computers permit a variety of branch instructions to + do the same job. Some of these instructions are short (and fast) + but have a limited range; others are long (and slow) but can + branch anywhere in virtual memory. Often there are 3 flavors of + branch: short, medium and long. Some other assemblers would emit + short and medium branches, unless told by this option to emit + short and long branches. + +``-t' (Temporary File Directory)' + Some other assemblers may use a temporary file, and this option + takes a filename being the directory to site the temporary file. + Since `as' does not use a temporary disk file, this option makes + no difference. `-t' needs exactly one filename. + + The Vax version of the assembler accepts additional options when +compiled for VMS: + +`-h N' + External symbol or section (used for global variables) names are + not case sensitive on VAX/VMS and always mapped to upper case. + This is contrary to the C language definition which explicitly + distinguishes upper and lower case. To implement a standard + conforming C compiler, names must be changed (mapped) to preserve + the case information. The default mapping is to convert all lower + case characters to uppercase and adding an underscore followed by + a 6 digit hex value, representing a 24 digit binary value. The + one digits in the binary value represent which characters are + uppercase in the original symbol name. + + The `-h N' option determines how we map names. This takes several + values. No `-h' switch at all allows case hacking as described + above. A value of zero (`-h0') implies names should be upper + case, and inhibits the case hack. A value of 2 (`-h2') implies + names should be all lower case, with no case hack. A value of 3 + (`-h3') implies that case should be preserved. The value 1 is + unused. The `-H' option directs `as' to display every mapped + symbol during assembly. + + Symbols whose names include a dollar sign `$' are exceptions to the + general name mapping. These symbols are normally only used to + reference VMS library names. Such symbols are always mapped to + upper case. + +`-+' + The `-+' option causes `as' to truncate any symbol name larger + than 31 characters. The `-+' option also prevents some code + following the `_main' symbol normally added to make the object + file compatible with Vax-11 "C". + +`-1' + This option is ignored for backward compatibility with `as' + version 1.x. + +`-H' + The `-H' option causes `as' to print every symbol which was + changed by case mapping. + + +File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent + +VAX Floating Point +------------------ + + Conversion of flonums to floating point is correct, and compatible +with previous assemblers. Rounding is towards zero if the remainder is +exactly half the least significant bit. + + `D', `F', `G' and `H' floating point formats are understood. + + Immediate floating literals (_e.g._ `S`$6.9') are rendered +correctly. Again, rounding is towards zero in the boundary case. + + The `.float' directive produces `f' format numbers. The `.double' +directive produces `d' format numbers. + + +File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent + +Vax Machine Directives +---------------------- + + The Vax version of the assembler supports four directives for +generating Vax floating point constants. They are described in the +table below. + +`.dfloat' + This expects zero or more flonums, separated by commas, and + assembles Vax `d' format 64-bit floating point constants. + +`.ffloat' + This expects zero or more flonums, separated by commas, and + assembles Vax `f' format 32-bit floating point constants. + +`.gfloat' + This expects zero or more flonums, separated by commas, and + assembles Vax `g' format 64-bit floating point constants. + +`.hfloat' + This expects zero or more flonums, separated by commas, and + assembles Vax `h' format 128-bit floating point constants. + + + +File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent + +VAX Opcodes +----------- + + All DEC mnemonics are supported. Beware that `case...' instructions +have exactly 3 operands. The dispatch table that follows the `case...' +instruction should be made with `.word' statements. This is compatible +with all unix assemblers we know of. + + +File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent + +VAX Branch Improvement +---------------------- + + Certain pseudo opcodes are permitted. They are for branch +instructions. They expand to the shortest branch instruction that +reaches the target. Generally these mnemonics are made by substituting +`j' for `b' at the start of a DEC mnemonic. This feature is included +both for compatibility and to help compilers. If you do not need this +feature, avoid these opcodes. Here are the mnemonics, and the code +they can expand into. + +`jbsb' + `Jsb' is already an instruction mnemonic, so we chose `jbsb'. + (byte displacement) + `bsbb ...' + + (word displacement) + `bsbw ...' + + (long displacement) + `jsb ...' + +`jbr' +`jr' + Unconditional branch. + (byte displacement) + `brb ...' + + (word displacement) + `brw ...' + + (long displacement) + `jmp ...' + +`jCOND' + COND may be any one of the conditional branches `neq', `nequ', + `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs', + `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests + `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs', + `lbc'. NOTCOND is the opposite condition to COND. + (byte displacement) + `bCOND ...' + + (word displacement) + `bNOTCOND foo ; brw ... ; foo:' + + (long displacement) + `bNOTCOND foo ; jmp ... ; foo:' + +`jacbX' + X may be one of `b d f g h l w'. + (word displacement) + `OPCODE ...' + + (long displacement) + OPCODE ..., foo ; + brb bar ; + foo: jmp ... ; + bar: + +`jaobYYY' + YYY may be one of `lss leq'. + +`jsobZZZ' + ZZZ may be one of `geq gtr'. + (byte displacement) + `OPCODE ...' + + (word displacement) + OPCODE ..., foo ; + brb bar ; + foo: brw DESTINATION ; + bar: + + (long displacement) + OPCODE ..., foo ; + brb bar ; + foo: jmp DESTINATION ; + bar: + +`aobleq' +`aoblss' +`sobgeq' +`sobgtr' + + (byte displacement) + `OPCODE ...' + + (word displacement) + OPCODE ..., foo ; + brb bar ; + foo: brw DESTINATION ; + bar: + + (long displacement) + OPCODE ..., foo ; + brb bar ; + foo: jmp DESTINATION ; + bar: + + +File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent + +VAX Operands +------------ + + The immediate character is `$' for Unix compatibility, not `#' as +DEC writes it. + + The indirect character is `*' for Unix compatibility, not `@' as DEC +writes it. + + The displacement sizing character is ``' (an accent grave) for Unix +compatibility, not `^' as DEC writes it. The letter preceding ``' may +have either case. `G' is not understood, but all other letters (`b i l +s w') are understood. + + Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper +and lower case letters are equivalent. + + For instance + tstb *w`$4(r5) + + Any expression is permitted in an operand. Operands are comma +separated. + + +File: as.info, Node: VAX-no, Prev: VAX-operands, Up: Vax-Dependent + +Not Supported on VAX +-------------------- + + Vax bit fields can not be assembled with `as'. Someone can add the +required code if they really need it. + + +File: as.info, Node: V850-Dependent, Next: Xtensa-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies + +v850 Dependent Features +======================= + +* Menu: + +* V850 Options:: Options +* V850 Syntax:: Syntax +* V850 Floating Point:: Floating Point +* V850 Directives:: V850 Machine Directives +* V850 Opcodes:: Opcodes + + +File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent + +Options +------- + + `as' supports the following additional command-line options for the +V850 processor family: + +`-wsigned_overflow' + Causes warnings to be produced when signed immediate values + overflow the space available for then within their opcodes. By + default this option is disabled as it is possible to receive + spurious warnings due to using exact bit patterns as immediate + constants. + +`-wunsigned_overflow' + Causes warnings to be produced when unsigned immediate values + overflow the space available for then within their opcodes. By + default this option is disabled as it is possible to receive + spurious warnings due to using exact bit patterns as immediate + constants. + +`-mv850' + Specifies that the assembled code should be marked as being + targeted at the V850 processor. This allows the linker to detect + attempts to link such code with code assembled for other + processors. + +`-mv850e' + Specifies that the assembled code should be marked as being + targeted at the V850E processor. This allows the linker to detect + attempts to link such code with code assembled for other + processors. + +`-mv850e1' + Specifies that the assembled code should be marked as being + targeted at the V850E1 processor. This allows the linker to + detect attempts to link such code with code assembled for other + processors. + +`-mv850any' + Specifies that the assembled code should be marked as being + targeted at the V850 processor but support instructions that are + specific to the extended variants of the process. This allows the + production of binaries that contain target specific code, but + which are also intended to be used in a generic fashion. For + example libgcc.a contains generic routines used by the code + produced by GCC for all versions of the v850 architecture, + together with support routines only used by the V850E architecture. + +`-mrelax' + Enables relaxation. This allows the .longcall and .longjump pseudo + ops to be used in the assembler source code. These ops label + sections of code which are either a long function call or a long + branch. The assembler will then flag these sections of code and + the linker will attempt to relax them. + + + +File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent + +Syntax +------ + +* Menu: + +* V850-Chars:: Special Characters +* V850-Regs:: Register Names + + +File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax + +Special Characters +.................. + + `#' is the line comment character. + + +File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax + +Register Names +.............. + + `as' supports the following names for registers: +`general register 0' + r0, zero + +`general register 1' + r1 + +`general register 2' + r2, hp + +`general register 3' + r3, sp + +`general register 4' + r4, gp + +`general register 5' + r5, tp + +`general register 6' + r6 + +`general register 7' + r7 + +`general register 8' + r8 + +`general register 9' + r9 + +`general register 10' + r10 + +`general register 11' + r11 + +`general register 12' + r12 + +`general register 13' + r13 + +`general register 14' + r14 + +`general register 15' + r15 + +`general register 16' + r16 + +`general register 17' + r17 + +`general register 18' + r18 + +`general register 19' + r19 + +`general register 20' + r20 + +`general register 21' + r21 + +`general register 22' + r22 + +`general register 23' + r23 + +`general register 24' + r24 + +`general register 25' + r25 + +`general register 26' + r26 + +`general register 27' + r27 + +`general register 28' + r28 + +`general register 29' + r29 + +`general register 30' + r30, ep + +`general register 31' + r31, lp + +`system register 0' + eipc + +`system register 1' + eipsw + +`system register 2' + fepc + +`system register 3' + fepsw + +`system register 4' + ecr + +`system register 5' + psw + +`system register 16' + ctpc + +`system register 17' + ctpsw + +`system register 18' + dbpc + +`system register 19' + dbpsw + +`system register 20' + ctbp + + +File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent + +Floating Point +-------------- + + The V850 family uses IEEE floating-point numbers. + + +File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent + +V850 Machine Directives +----------------------- + +`.offset ' + Moves the offset into the current section to the specified amount. + +`.section "name", ' + This is an extension to the standard .section directive. It sets + the current section to be and creates an alias for this + section called "name". + +`.v850' + Specifies that the assembled code should be marked as being + targeted at the V850 processor. This allows the linker to detect + attempts to link such code with code assembled for other + processors. + +`.v850e' + Specifies that the assembled code should be marked as being + targeted at the V850E processor. This allows the linker to detect + attempts to link such code with code assembled for other + processors. + +`.v850e1' + Specifies that the assembled code should be marked as being + targeted at the V850E1 processor. This allows the linker to + detect attempts to link such code with code assembled for other + processors. + + + +File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent + +Opcodes +------- + + `as' implements all the standard V850 opcodes. + + `as' also implements the following pseudo ops: + +`hi0()' + Computes the higher 16 bits of the given expression and stores it + into the immediate operand field of the given instruction. For + example: + + `mulhi hi0(here - there), r5, r6' + + computes the difference between the address of labels 'here' and + 'there', takes the upper 16 bits of this difference, shifts it + down 16 bits and then mutliplies it by the lower 16 bits in + register 5, putting the result into register 6. + +`lo()' + Computes the lower 16 bits of the given expression and stores it + into the immediate operand field of the given instruction. For + example: + + `addi lo(here - there), r5, r6' + + computes the difference between the address of labels 'here' and + 'there', takes the lower 16 bits of this difference and adds it to + register 5, putting the result into register 6. + +`hi()' + Computes the higher 16 bits of the given expression and then adds + the value of the most significant bit of the lower 16 bits of the + expression and stores the result into the immediate operand field + of the given instruction. For example the following code can be + used to compute the address of the label 'here' and store it into + register 6: + + `movhi hi(here), r0, r6' `movea lo(here), r6, r6' + + The reason for this special behaviour is that movea performs a sign + extension on its immediate operand. So for example if the address + of 'here' was 0xFFFFFFFF then without the special behaviour of the + hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, + then the movea instruction would takes its immediate operand, + 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it + into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). + With the hi() pseudo op adding in the top bit of the lo() pseudo + op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = + 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - + the right value. + +`hilo()' + Computes the 32 bit value of the given expression and stores it + into the immediate operand field of the given instruction (which + must be a mov instruction). For example: + + `mov hilo(here), r6' + + computes the absolute address of label 'here' and puts the result + into register 6. + +`sdaoff()' + Computes the offset of the named variable from the start of the + Small Data Area (whoes address is held in register 4, the GP + register) and stores the result as a 16 bit signed value in the + immediate operand field of the given instruction. For example: + + `ld.w sdaoff(_a_variable)[gp],r6' + + loads the contents of the location pointed to by the label + '_a_variable' into register 6, provided that the label is located + somewhere within +/- 32K of the address held in the GP register. + [Note the linker assumes that the GP register contains a fixed + address set to the address of the label called '__gp'. This can + either be set up automatically by the linker, or specifically set + by using the `--defsym __gp=' command line option]. + +`tdaoff()' + Computes the offset of the named variable from the start of the + Tiny Data Area (whoes address is held in register 30, the EP + register) and stores the result as a 4,5, 7 or 8 bit unsigned + value in the immediate operand field of the given instruction. + For example: + + `sld.w tdaoff(_a_variable)[ep],r6' + + loads the contents of the location pointed to by the label + '_a_variable' into register 6, provided that the label is located + somewhere within +256 bytes of the address held in the EP + register. [Note the linker assumes that the EP register contains + a fixed address set to the address of the label called '__ep'. + This can either be set up automatically by the linker, or + specifically set by using the `--defsym __ep=' command line + option]. + +`zdaoff()' + Computes the offset of the named variable from address 0 and + stores the result as a 16 bit signed value in the immediate + operand field of the given instruction. For example: + + `movea zdaoff(_a_variable),zero,r6' + + puts the address of the label '_a_variable' into register 6, + assuming that the label is somewhere within the first 32K of + memory. (Strictly speaking it also possible to access the last + 32K of memory as well, as the offsets are signed). + +`ctoff()' + Computes the offset of the named variable from the start of the + Call Table Area (whoes address is helg in system register 20, the + CTBP register) and stores the result a 6 or 16 bit unsigned value + in the immediate field of then given instruction or piece of data. + For example: + + `callt ctoff(table_func1)' + + will put the call the function whoes address is held in the call + table at the location labeled 'table_func1'. + +`.longcall `name'' + Indicates that the following sequence of instructions is a long + call to function `name'. The linker will attempt to shorten this + call sequence if `name' is within a 22bit offset of the call. Only + valid if the `-mrelax' command line switch has been enabled. + +`.longjump `name'' + Indicates that the following sequence of instructions is a long + jump to label `name'. The linker will attempt to shorten this code + sequence if `name' is within a 22bit offset of the jump. Only + valid if the `-mrelax' command line switch has been enabled. + + + For information on the V850 instruction set, see `V850 Family +32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. +Ltd. + + +File: as.info, Node: Xtensa-Dependent, Next: Z8000-Dependent, Prev: V850-Dependent, Up: Machine Dependencies + +Xtensa Dependent Features +========================= + + This chapter covers features of the GNU assembler that are specific +to the Xtensa architecture. For details about the Xtensa instruction +set, please consult the `Xtensa Instruction Set Architecture (ISA) +Reference Manual'. + +* Menu: + +* Xtensa Options:: Command-line Options. +* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. +* Xtensa Optimizations:: Assembler Optimizations. +* Xtensa Relaxation:: Other Automatic Transformations. +* Xtensa Directives:: Directives for Xtensa Processors. + + +File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent + +Command Line Options +-------------------- + + The Xtensa version of the GNU assembler supports these special +options: + +`--text-section-literals | --no-text-section-literals' + Control the treatment of literal pools. The default is + `--no-text-section-literals', which places literals in a separate + section in the output file. This allows the literal pool to be + placed in a data RAM/ROM. With `--text-section-literals', the + literals are interspersed in the text section in order to keep + them as close as possible to their references. This may be + necessary for large assembly files, where the literals would + otherwise be out of range of the `L32R' instructions in the text + section. These options only affect literals referenced via + PC-relative `L32R' instructions; literals for absolute mode `L32R' + instructions are handled separately. + +`--absolute-literals | --no-absolute-literals' + Indicate to the assembler whether `L32R' instructions use absolute + or PC-relative addressing. If the processor includes the absolute + addressing option, the default is to use absolute `L32R' + relocations. Otherwise, only the PC-relative `L32R' relocations + can be used. + +`--target-align | --no-target-align' + Enable or disable automatic alignment to reduce branch penalties + at some expense in code size. *Note Automatic Instruction + Alignment: Xtensa Automatic Alignment. This optimization is + enabled by default. Note that the assembler will always align + instructions like `LOOP' that have fixed alignment requirements. + +`--longcalls | --no-longcalls' + Enable or disable transformation of call instructions to allow + calls across a greater range of addresses. *Note Function Call + Relaxation: Xtensa Call Relaxation. This option should be used + when call targets can potentially be out of range. It may degrade + both code size and performance, but the linker can generally + optimize away the unnecessary overhead when a call ends up within + range. The default is `--no-longcalls'. + +`--transform | --no-transform' + Enable or disable all assembler transformations of Xtensa + instructions, including both relaxation and optimization. The + default is `--transform'; `--no-transform' should only be used in + the rare cases when the instructions must be exactly as specified + in the assembly source. Using `--no-transform' causes out of range + instruction operands to be errors. + +`--rename-section OLDNAME=NEWNAME' + Rename the OLDNAME section to NEWNAME. This option can be used + multiple times to rename multiple sections. + + +File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent + +Assembler Syntax +---------------- + + Block comments are delimited by `/*' and `*/'. End of line comments +may be introduced with either `#' or `//'. + + Instructions consist of a leading opcode or macro name followed by +whitespace and an optional comma-separated list of operands: + + OPCODE [OPERAND, ...] + + Instructions must be separated by a newline or semicolon. + + FLIX instructions, which bundle multiple opcodes together in a single +instruction, are specified by enclosing the bundled opcodes inside +braces: + + { + [FORMAT] + OPCODE0 [OPERANDS] + OPCODE1 [OPERANDS] + OPCODE2 [OPERANDS] + ... + } + + The opcodes in a FLIX instruction are listed in the same order as the +corresponding instruction slots in the TIE format declaration. +Directives and labels are not allowed inside the braces of a FLIX +instruction. A particular TIE format name can optionally be specified +immediately after the opening brace, but this is usually unnecessary. +The assembler will automatically search for a format that can encode the +specified opcodes, so the format name need only be specified in rare +cases where there is more than one applicable format and where it +matters which of those formats is used. A FLIX instruction can also be +specified on a single line by separating the opcodes with semicolons: + + { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } + + The assembler can automatically bundle opcodes into FLIX +instructions. It encodes the opcodes in order, one at a time, choosing +the smallest format where each opcode can be encoded and filling unused +instruction slots with no-ops. + +* Menu: + +* Xtensa Opcodes:: Opcode Naming Conventions. +* Xtensa Registers:: Register Naming. + + +File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax + +Opcode Names +............ + + See the `Xtensa Instruction Set Architecture (ISA) Reference Manual' +for a complete list of opcodes and descriptions of their semantics. + + If an opcode name is prefixed with an underscore character (`_'), +`as' will not transform that instruction in any way. The underscore +prefix disables both optimization (*note Xtensa Optimizations: Xtensa +Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa +Relaxation.) for that particular instruction. Only use the underscore +prefix when it is essential to select the exact opcode produced by the +assembler. Using this feature unnecessarily makes the code less +efficient by disabling assembler optimization and less flexible by +disabling relaxation. + + Note that this special handling of underscore prefixes only applies +to Xtensa opcodes, not to either built-in macros or user-defined macros. +When an underscore prefix is used with a macro (e.g., `_MOV'), it +refers to a different macro. The assembler generally provides built-in +macros both with and without the underscore prefix, where the underscore +versions behave as if the underscore carries through to the instructions +in the macros. For example, `_MOV' may expand to `_MOV.N'. + + The underscore prefix only applies to individual instructions, not to +series of instructions. For example, if a series of instructions have +underscore prefixes, the assembler will not transform the individual +instructions, but it may insert other instructions between them (e.g., +to align a `LOOP' instruction). To prevent the assembler from +modifying a series of instructions as a whole, use the `no-transform' +directive. *Note transform: Transform Directive. + + +File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax + +Register Names +.............. + + The assembly syntax for a register file entry is the "short" name for +a TIE register file followed by the index into that register file. For +example, the general-purpose `AR' register file has a short name of +`a', so these registers are named `a0'...`a15'. As a special feature, +`sp' is also supported as a synonym for `a1'. Additional registers may +be added by processor configuration options and by designer-defined TIE +extensions. An initial `$' character is optional in all register names. + + +File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent + +Xtensa Optimizations +-------------------- + + The optimizations currently supported by `as' are generation of +density instructions where appropriate and automatic branch target +alignment. + +* Menu: + +* Density Instructions:: Using Density Instructions. +* Xtensa Automatic Alignment:: Automatic Instruction Alignment. + + +File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations + +Using Density Instructions +.......................... + + The Xtensa instruction set has a code density option that provides +16-bit versions of some of the most commonly used opcodes. Use of these +opcodes can significantly reduce code size. When possible, the +assembler automatically translates instructions from the core Xtensa +instruction set into equivalent instructions from the Xtensa code +density option. This translation can be disabled by using underscore +prefixes (*note Opcode Names: Xtensa Opcodes.), by using the +`--no-transform' command-line option (*note Command Line Options: +Xtensa Options.), or by using the `no-transform' directive (*note +transform: Transform Directive.). + + It is a good idea _not_ to use the density instructions directly. +The assembler will automatically select dense instructions where +possible. If you later need to use an Xtensa processor without the code +density option, the same assembly code will then work without +modification. + + +File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations + +Automatic Instruction Alignment +............................... + + The Xtensa assembler will automatically align certain instructions, +both to optimize performance and to satisfy architectural requirements. + + As an optimization to improve performance, the assembler attempts to +align branch targets so they do not cross instruction fetch boundaries. +(Xtensa processors can be configured with either 32-bit or 64-bit +instruction fetch widths.) An instruction immediately following a call +is treated as a branch target in this context, because it will be the +target of a return from the call. This alignment has the potential to +reduce branch penalties at some expense in code size. The assembler +will not attempt to align labels with the prefixes `.Ln' and `.LM', +since these labels are used for debugging information and are not +typically branch targets. This optimization is enabled by default. +You can disable it with the `--no-target-align' command-line option +(*note Command Line Options: Xtensa Options.). + + The target alignment optimization is done without adding instructions +that could increase the execution time of the program. If there are +density instructions in the code preceding a target, the assembler can +change the target alignment by widening some of those instructions to +the equivalent 24-bit instructions. Extra bytes of padding can be +inserted immediately following unconditional jump and return +instructions. This approach is usually successful in aligning many, +but not all, branch targets. + + The `LOOP' family of instructions must be aligned such that the +first instruction in the loop body does not cross an instruction fetch +boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be +on either a 1 or 2 mod 4 byte boundary). The assembler knows about +this restriction and inserts the minimal number of 2 or 3 byte no-op +instructions to satisfy it. When no-op instructions are added, any +label immediately preceding the original loop will be moved in order to +refer to the loop instruction, not the newly generated no-op +instruction. To preserve binary compatibility across processors with +different fetch widths, the assembler conservatively assumes a 32-bit +fetch width when aligning `LOOP' instructions (except if the first +instruction in the loop is a 64-bit instruction). + + Similarly, the `ENTRY' instruction must be aligned on a 0 mod 4 byte +boundary. The assembler satisfies this requirement by inserting zero +bytes when required. In addition, labels immediately preceding the +`ENTRY' instruction will be moved to the newly aligned instruction +location. + + +File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent + +Xtensa Relaxation +----------------- + + When an instruction operand is outside the range allowed for that +particular instruction field, `as' can transform the code to use a +functionally-equivalent instruction or sequence of instructions. This +process is known as "relaxation". This is typically done for branch +instructions because the distance of the branch targets is not known +until assembly-time. The Xtensa assembler offers branch relaxation and +also extends this concept to function calls, `MOVI' instructions and +other instructions with immediate fields. + +* Menu: + +* Xtensa Branch Relaxation:: Relaxation of Branches. +* Xtensa Call Relaxation:: Relaxation of Function Calls. +* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. + + +File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation + +Conditional Branch Relaxation +............................. + + When the target of a branch is too far away from the branch itself, +i.e., when the offset from the branch to the target is too large to fit +in the immediate field of the branch instruction, it may be necessary to +replace the branch with a branch around a jump. For example, + + beqz a2, L + + may result in: + + bnez.n a2, M + j L + M: + + (The `BNEZ.N' instruction would be used in this example only if the +density option is available. Otherwise, `BNEZ' would be used.) + + This relaxation works well because the unconditional jump instruction +has a much larger offset range than the various conditional branches. +However, an error will occur if a branch target is beyond the range of a +jump instruction. `as' cannot relax unconditional jumps. Similarly, +an error will occur if the original input contains an unconditional +jump to a target that is out of range. + + Branch relaxation is enabled by default. It can be disabled by using +underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the +`--no-transform' command-line option (*note Command Line Options: +Xtensa Options.), or the `no-transform' directive (*note transform: +Transform Directive.). + + +File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation + +Function Call Relaxation +........................ + + Function calls may require relaxation because the Xtensa immediate +call instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a +PC-relative offset of only 512 Kbytes in either direction. For larger +programs, it may be necessary to use indirect calls (`CALLX0', +`CALLX4', `CALLX8' and `CALLX12') where the target address is specified +in a register. The Xtensa assembler can automatically relax immediate +call instructions into indirect call instructions. This relaxation is +done by loading the address of the called function into the callee's +return address register and then using a `CALLX' instruction. So, for +example: + + call8 func + + might be relaxed to: + + .literal .L1, func + l32r a8, .L1 + callx8 a8 + + Because the addresses of targets of function calls are not generally +known until link-time, the assembler must assume the worst and relax all +the calls to functions in other source files, not just those that really +will be out of range. The linker can recognize calls that were +unnecessarily relaxed, and it will remove the overhead introduced by the +assembler for those cases where direct calls are sufficient. + + Call relaxation is disabled by default because it can have a negative +effect on both code size and performance, although the linker can +usually eliminate the unnecessary overhead. If a program is too large +and some of the calls are out of range, function call relaxation can be +enabled using the `--longcalls' command-line option or the `longcalls' +directive (*note longcalls: Longcalls Directive.). + + +File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation + +Other Immediate Field Relaxation +................................ + + The assembler normally performs the following other relaxations. +They can be disabled by using underscore prefixes (*note Opcode Names: +Xtensa Opcodes.), the `--no-transform' command-line option (*note +Command Line Options: Xtensa Options.), or the `no-transform' directive +(*note transform: Transform Directive.). + + The `MOVI' machine instruction can only materialize values in the +range from -2048 to 2047. Values outside this range are best +materialized with `L32R' instructions. Thus: + + movi a0, 100000 + + is assembled into the following machine code: + + .literal .L1, 100000 + l32r a0, .L1 + + The `L8UI' machine instruction can only be used with immediate +offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine +instructions can only be used with offsets from 0 to 510. The `L32I' +machine instruction can only be used with offsets from 0 to 1020. A +load offset outside these ranges can be materalized with an `L32R' +instruction if the destination register of the load is different than +the source address register. For example: + + l32i a1, a0, 2040 + + is translated to: + + .literal .L1, 2040 + l32r a1, .L1 + addi a1, a0, a1 + l32i a1, a1, 0 + +If the load destination and source address register are the same, an +out-of-range offset causes an error. + + The Xtensa `ADDI' instruction only allows immediate operands in the +range from -128 to 127. There are a number of alternate instruction +sequences for the `ADDI' operation. First, if the immediate is 0, the +`ADDI' will be turned into a `MOV.N' instruction (or the equivalent +`OR' instruction if the code density option is not available). If the +`ADDI' immediate is outside of the range -128 to 127, but inside the +range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI' +sequence will be used. Finally, if the immediate is outside of this +range and a free register is available, an `L32R'/`ADD' sequence will +be used with a literal allocated from the literal pool. + + For example: + + addi a5, a6, 0 + addi a5, a6, 512 + addi a5, a6, 513 + addi a5, a6, 50000 + + is assembled into the following: + + .literal .L1, 50000 + mov.n a5, a6 + addmi a5, a6, 0x200 + addmi a5, a6, 0x200 + addi a5, a5, 1 + l32r a5, .L1 + add a5, a6, a5 + + +File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent + +Directives +---------- + + The Xtensa assember supports a region-based directive syntax: + + .begin DIRECTIVE [OPTIONS] + ... + .end DIRECTIVE + + All the Xtensa-specific directives that apply to a region of code use +this syntax. + + The directive applies to code between the `.begin' and the `.end'. +The state of the option after the `.end' reverts to what it was before +the `.begin'. A nested `.begin'/`.end' region can further change the +state of the directive without having to be aware of its outer state. +For example, consider: + + .begin no-transform + L: add a0, a1, a2 + .begin transform + M: add a0, a1, a2 + .end transform + N: add a0, a1, a2 + .end no-transform + + The `ADD' opcodes at `L' and `N' in the outer `no-transform' region +both result in `ADD' machine instructions, but the assembler selects an +`ADD.N' instruction for the `ADD' at `M' in the inner `transform' +region. + + The advantage of this style is that it works well inside macros +which can preserve the context of their callers. + + The following directives are available: + +* Menu: + +* Schedule Directive:: Enable instruction scheduling. +* Longcalls Directive:: Use Indirect Calls for Greater Range. +* Transform Directive:: Disable All Assembler Transformations. +* Literal Directive:: Intermix Literals with Instructions. +* Literal Position Directive:: Specify Inline Literal Pool Locations. +* Literal Prefix Directive:: Specify Literal Section Name Prefix. +* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. + + +File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives + +schedule +........ + + The `schedule' directive is recognized only for compatibility with +Tensilica's assembler. + + .begin [no-]schedule + .end [no-]schedule + + This directive is ignored and has no effect on `as'. + + +File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives + +longcalls +......... + + The `longcalls' directive enables or disables function call +relaxation. *Note Function Call Relaxation: Xtensa Call Relaxation. + + .begin [no-]longcalls + .end [no-]longcalls + + Call relaxation is disabled by default unless the `--longcalls' +command-line option is specified. The `longcalls' directive overrides +the default determined by the command-line options. + + +File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives + +transform +......... + + This directive enables or disables all assembler transformation, +including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and +optimization (*note Xtensa Optimizations: Xtensa Optimizations.). + + .begin [no-]transform + .end [no-]transform + + Transformations are enabled by default unless the `--no-transform' +option is used. The `transform' directive overrides the default +determined by the command-line options. An underscore opcode prefix, +disabling transformation of that opcode, always takes precedence over +both directives and command-line flags. + + +File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives + +literal +....... + + The `.literal' directive is used to define literal pool data, i.e., +read-only 32-bit data accessed via `L32R' instructions. + + .literal LABEL, VALUE[, VALUE...] + + This directive is similar to the standard `.word' directive, except +that the actual location of the literal data is determined by the +assembler and linker, not by the position of the `.literal' directive. +Using this directive gives the assembler freedom to locate the literal +data in the most appropriate place and possibly to combine identical +literals. For example, the code: + + entry sp, 40 + .literal .L1, sym + l32r a4, .L1 + + can be used to load a pointer to the symbol `sym' into register +`a4'. The value of `sym' will not be placed between the `ENTRY' and +`L32R' instructions; instead, the assembler puts the data in a literal +pool. + + Literal pools for absolute mode `L32R' instructions (*note Absolute +Literals Directive::) are placed in a seperate `.lit4' section. By +default literal pools for PC-relative mode `L32R' instructions are +placed in a separate `.literal' section; however, when using the +`--text-section-literals' option (*note Command Line Options: Xtensa +Options.), the literal pools are placed in the current section. These +text section literal pools are created automatically before `ENTRY' +instructions and manually after `.literal_position' directives (*note +literal_position: Literal Position Directive.). If there are no +preceding `ENTRY' instructions, explicit `.literal_position' directives +must be used to place the text section literal pools; otherwise, `as' +will report an error. + + +File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives + +literal_position +................ + + When using `--text-section-literals' to place literals inline in the +section being assembled, the `.literal_position' directive can be used +to mark a potential location for a literal pool. + + .literal_position + + The `.literal_position' directive is ignored when the +`--text-section-literals' option is not used or when `L32R' +instructions use the absolute addressing mode. + + The assembler will automatically place text section literal pools +before `ENTRY' instructions, so the `.literal_position' directive is +only needed to specify some other location for a literal pool. You may +need to add an explicit jump instruction to skip over an inline literal +pool. + + For example, an interrupt vector does not begin with an `ENTRY' +instruction so the assembler will be unable to automatically find a good +place to put a literal pool. Moreover, the code for the interrupt +vector must be at a specific starting address, so the literal pool +cannot come before the start of the code. The literal pool for the +vector must be explicitly positioned in the middle of the vector (before +any uses of the literals, due to the negative offsets used by +PC-relative `L32R' instructions). The `.literal_position' directive +can be used to do this. In the following code, the literal for `M' +will automatically be aligned correctly and is placed after the +unconditional jump. + + .global M + code_start: + j continue + .literal_position + .align 4 + continue: + movi a4, M + + +File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives + +literal_prefix +.............. + + The `literal_prefix' directive allows you to specify different +sections to hold literals from different portions of an assembly file. +With this directive, a single assembly file can be used to generate code +into multiple sections, including literals generated by the assembler. + + .begin literal_prefix [NAME] + .end literal_prefix + + By default the assembler places literal pools in sections separate +from the instructions, using the default literal section names of +`.literal' for PC-relative mode `L32R' instructions and `.lit4' for +absolute mode `L32R' instructions (*note Absolute Literals +Directive::). The `literal_prefix' directive causes different literal +sections to be used for the code inside the delimited region. The new +literal sections are determined by including NAME as a prefix to the +default literal section names. If the NAME argument is omitted, the +literal sections revert to the defaults. This directive has no effect +when using the `--text-section-literals' option (*note Command Line +Options: Xtensa Options.). + + Except for two special cases, the assembler determines the new +literal sections by simply prepending NAME to the default section names, +resulting in `NAME.literal' and `NAME.lit4' sections. The +`literal_prefix' directive is often used with the name of the current +text section as the prefix argument. To facilitate this usage, the +assembler uses special case rules when it recognizes NAME as a text +section name. First, if NAME ends with `.text', that suffix is not +included in the literal section name. For example, if NAME is +`.iram0.text', then the literal sections will be `.iram0.literal' and +`.iram0.lit4'. Second, if NAME begins with `.gnu.linkonce.t.', then +the literal section names are formed by replacing the `.t' substring +with `.literal' and `.lit4'. For example, if NAME is +`.gnu.linkonce.t.func', the literal sections will be +`.gnu.linkonce.literal.func' and `.gnu.linkonce.lit4.func'. + + +File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives + +absolute-literals +................. + + The `absolute-literals' and `no-absolute-literals' directives +control the absolute vs. PC-relative mode for `L32R' instructions. +These are relevant only for Xtensa configurations that include the +absolute addressing option for `L32R' instructions. + + .begin [no-]absolute-literals + .end [no-]absolute-literals + + These directives do not change the `L32R' mode--they only cause the +assembler to emit the appropriate kind of relocation for `L32R' +instructions and to place the literal values in the appropriate section. +To change the `L32R' mode, the program must write the `LITBASE' special +register. It is the programmer's responsibility to keep track of the +mode and indicate to the assembler which mode is used in each region of +code. + + If the Xtensa configuration includes the absolute `L32R' addressing +option, the default is to assume absolute `L32R' addressing unless the +`--no-absolute-literals' command-line option is specified. Otherwise, +the default is to assume PC-relative `L32R' addressing. The +`absolute-literals' directive can then be used to override the default +determined by the command-line options. + + +File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top + +Reporting Bugs +************** + + Your bug reports play an essential role in making `as' reliable. + + Reporting a bug may help you by bringing a solution to your problem, +or it may not. But in any case the principal function of a bug report +is to help the entire community by making the next version of `as' work +better. Bug reports are your contribution to the maintenance of `as'. + + In order for a bug report to serve its purpose, you must include the +information that enables us to fix the bug. + +* Menu: + +* Bug Criteria:: Have you found a bug? +* Bug Reporting:: How to report bugs + + +File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs + +Have You Found a Bug? +===================== + + If you are not sure whether you have found a bug, here are some +guidelines: + + * If the assembler gets a fatal signal, for any input whatever, that + is a `as' bug. Reliable assemblers never crash. + + * If `as' produces an error message for valid input, that is a bug. + + * If `as' does not produce an error message for invalid input, that + is a bug. However, you should note that your idea of "invalid + input" might be our idea of "an extension" or "support for + traditional practice". + + * If you are an experienced user of assemblers, your suggestions for + improvement of `as' are welcome in any case. + + +File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs + +How to Report Bugs +================== + + A number of companies and individuals offer support for GNU +products. If you obtained `as' from a support organization, we +recommend you contact that organization first. + + You can find contact information for many support companies and +individuals in the file `etc/SERVICE' in the GNU Emacs distribution. + + In any event, we also recommend that you send bug reports for `as' +to `bug-binutils@gnu.org'. + + The fundamental principle of reporting bugs usefully is this: +*report all the facts*. If you are not sure whether to state a fact or +leave it out, state it! + + Often people omit facts because they think they know what causes the +problem and assume that some details do not matter. Thus, you might +assume that the name of a symbol you use in an example does not matter. +Well, probably it does not, but one cannot be sure. Perhaps the bug +is a stray memory reference which happens to fetch from the location +where that name is stored in memory; perhaps, if the name were +different, the contents of that location would fool the assembler into +doing the right thing despite the bug. Play it safe and give a +specific, complete example. That is the easiest thing for you to do, +and the most helpful. + + Keep in mind that the purpose of a bug report is to enable us to fix +the bug if it is new to us. Therefore, always write your bug reports +on the assumption that the bug has not been reported previously. + + Sometimes people give a few sketchy facts and ask, "Does this ring a +bell?" This cannot help us fix a bug, so it is basically useless. We +respond by asking for enough details to enable us to investigate. You +might as well expedite matters by sending them to begin with. + + To enable us to fix the bug, you should include all these things: + + * The version of `as'. `as' announces it if you start it with the + `--version' argument. + + Without this, we will not know whether there is any point in + looking for the bug in the current version of `as'. + + * Any patches you may have applied to the `as' source. + + * The type of machine you are using, and the operating system name + and version number. + + * What compiler (and its version) was used to compile `as'--e.g. + "`gcc-2.7'". + + * The command arguments you gave the assembler to assemble your + example and observe the bug. To guarantee you will not omit + something important, list them all. A copy of the Makefile (or + the output from make) is sufficient. + + If we were to try to guess the arguments, we would probably guess + wrong and then we might not encounter the bug. + + * A complete input file that will reproduce the bug. If the bug is + observed when the assembler is invoked via a compiler, send the + assembler source, not the high level language source. Most + compilers will produce the assembler source when run with the `-S' + option. If you are using `gcc', use the options `-v + --save-temps'; this will save the assembler source in a file with + an extension of `.s', and also show you exactly how `as' is being + run. + + * A description of what behavior you observe that you believe is + incorrect. For example, "It gets a fatal signal." + + Of course, if the bug is that `as' gets a fatal signal, then we + will certainly notice it. But if the bug is incorrect output, we + might not notice unless it is glaringly wrong. You might as well + not give us a chance to make a mistake. + + Even if the problem you experience is a fatal signal, you should + still say so explicitly. Suppose something strange is going on, + such as, your copy of `as' is out of synch, or you have + encountered a bug in the C library on your system. (This has + happened!) Your copy might crash and ours would not. If you told + us to expect a crash, then when ours fails to crash, we would know + that the bug was not happening for us. If you had not told us to + expect a crash, then we would not be able to draw any conclusion + from our observations. + + * If you wish to suggest changes to the `as' source, send us context + diffs, as generated by `diff' with the `-u', `-c', or `-p' option. + Always send diffs from the old file to the new file. If you even + discuss something in the `as' source, refer to it by context, not + by line number. + + The line numbers in our development sources will not match those + in your sources. Your line numbers would convey no useful + information to us. + + Here are some things that are not necessary: + + * A description of the envelope of the bug. + + Often people who encounter a bug spend a lot of time investigating + which changes to the input file will make the bug go away and which + changes will not affect it. + + This is often time consuming and not very useful, because the way + we will find the bug is by running a single example under the + debugger with breakpoints, not by pure deduction from a series of + examples. We recommend that you save your time for something else. + + Of course, if you can find a simpler example to report _instead_ + of the original one, that is a convenience for us. Errors in the + output will be easier to spot, running under the debugger will take + less time, and so on. + + However, simplification is not vital; if you do not want to do + this, report the bug anyway and send us the entire test case you + used. + + * A patch for the bug. + + A patch for the bug does help us if it is a good one. But do not + omit the necessary information, such as the test case, on the + assumption that a patch is all we need. We might see problems + with your patch and decide to fix the problem another way, or we + might not understand it at all. + + Sometimes with a program as complicated as `as' it is very hard to + construct an example that will make the program follow a certain + path through the code. If you do not send us the example, we will + not be able to construct one, so we will not be able to verify + that the bug is fixed. + + And if we cannot understand what bug you are trying to fix, or why + your patch should be an improvement, we will not install it. A + test case will help us to understand. + + * A guess about what the bug is or what it depends on. + + Such guesses are usually wrong. Even we cannot guess right about + such things without first using the debugger to find the facts. + + +File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top + +Acknowledgements +**************** + + If you have contributed to GAS and your name isn't listed here, it +is not meant as a slight. We just don't know about it. Send mail to +the maintainer, and we'll correct the situation. Currently the +maintainer is Ken Raeburn (email address `raeburn@cygnus.com'). + + Dean Elsner wrote the original GNU assembler for the VAX.(1) + + Jay Fenlason maintained GAS for a while, adding support for +GDB-specific debug information and the 68k series machines, most of the +preprocessing pass, and extensive changes in `messages.c', +`input-file.c', `write.c'. + + K. Richard Pixley maintained GAS for a while, adding various +enhancements and many bug fixes, including merging support for several +processors, breaking GAS up to handle multiple object file format back +ends (including heavy rewrite, testing, an integration of the coff and +b.out back ends), adding configuration including heavy testing and +verification of cross assemblers and file splits and renaming, +converted GAS to strictly ANSI C including full prototypes, added +support for m680[34]0 and cpu32, did considerable work on i960 +including a COFF port (including considerable amounts of reverse +engineering), a SPARC opcode file rewrite, DECstation, rs6000, and +hp300hpux host ports, updated "know" assertions and made them work, +much other reorganization, cleanup, and lint. + + Ken Raeburn wrote the high-level BFD interface code to replace most +of the code in format-specific I/O modules. + + The original VMS support was contributed by David L. Kashtan. Eric +Youngdale has done much work with it since. + + The Intel 80386 machine description was written by Eliot Dresselhaus. + + Minh Tran-Le at IntelliCorp contributed some AIX 386 support. + + The Motorola 88k machine description was contributed by Devon Bowen +of Buffalo University and Torbjorn Granlund of the Swedish Institute of +Computer Science. + + Keith Knowles at the Open Software Foundation wrote the original +MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format +support (which hasn't been merged in yet). Ralph Campbell worked with +the MIPS code to support a.out format. + + Support for the Zilog Z8k and Renesas H8/300 and H8/500 processors +(tc-z8k, tc-h8300, tc-h8500), and IEEE 695 object file format +(obj-ieee), was written by Steve Chamberlain of Cygnus Support. Steve +also modified the COFF back end to use BFD for some low-level +operations, for use with the H8/300 and AMD 29k targets. + + John Gilmore built the AMD 29000 support, added `.include' support, +and simplified the configuration of which versions accept which +directives. He updated the 68k machine description so that Motorola's +opcodes always produced fixed-size instructions (e.g., `jsr'), while +synthetic instructions remained shrinkable (`jbsr'). John fixed many +bugs, including true tested cross-compilation support, and one bug in +relaxation that took a week and required the proverbial one-bit fix. + + Ian Lance Taylor of Cygnus Support merged the Motorola and MIT +syntax for the 68k, completed support for some COFF targets (68k, i386 +SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, +wrote the initial RS/6000 and PowerPC assembler, and made a few other +minor patches. + + Steve Chamberlain made GAS able to generate listings. + + Hewlett-Packard contributed support for the HP9000/300. + + Jeff Law wrote GAS and BFD support for the native HPPA object format +(SOM) along with a fairly extensive HPPA testsuite (for both SOM and +ELF object formats). This work was supported by both the Center for +Software Science at the University of Utah and Cygnus Support. + + Support for ELF format files has been worked on by Mark Eichin of +Cygnus Support (original, incomplete implementation for SPARC), Pete +Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), +Michael Meissner of the Open Software Foundation (i386 mainly), and Ken +Raeburn of Cygnus Support (sparc, and some initial 64-bit support). + + Linas Vepstas added GAS support for the ESA/390 "IBM 370" +architecture. + + Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote +GAS and BFD support for openVMS/Alpha. + + Timothy Wall, Michael Hayes, and Greg Smart contributed to the +various tic* flavors. + + David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from +Tensilica, Inc. added support for Xtensa processors. + + Several engineers at Cygnus Support have also provided many small +bug fixes and configuration enhancements. + + Many others have contributed large or small bugfixes and +enhancements. If you have contributed significant work and are not +mentioned on this list, and want to be, let us know. Some of the +history has been lost; we are not intentionally leaving anyone out. + + ---------- Footnotes ---------- + + (1) Any more details? + + +File: as.info, Node: GNU Free Documentation License, Next: Index, Prev: Acknowledgements, Up: Top + +GNU Free Documentation License +****************************** + + Version 1.1, March 2000 + Copyright (C) 2000, 2003 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + 0. PREAMBLE + + The purpose of this License is to make a manual, textbook, or other + written document "free" in the sense of freedom: to assure everyone + the effective freedom to copy and redistribute it, with or without + modifying it, either commercially or noncommercially. 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If you have no Front-Cover +Texts, write "no Front-Cover Texts" instead of "Front-Cover Texts being +LIST"; likewise for Back-Cover Texts. + + If your document contains nontrivial examples of program code, we +recommend releasing these examples in parallel under your choice of +free software license, such as the GNU General Public License, to +permit their use in free software. + + +File: as.info, Node: Index, Prev: GNU Free Documentation License, Up: Top + +Index +***** + +* Menu: + +* #: Comments. +* #APP: Preprocessing. +* #NO_APP: Preprocessing. +* $ in symbol names <1>: SH64-Chars. +* $ in symbol names <2>: SH-Chars. +* $ in symbol names <3>: H8/500-Chars. +* $ in symbol names <4>: D30V-Chars. +* $ in symbol names: D10V-Chars. +* $a: ARM Mapping Symbols. +* $acos math builtin, TIC54X: TIC54X-Builtins. +* $asin math builtin, TIC54X: TIC54X-Builtins. +* $atan math builtin, TIC54X: TIC54X-Builtins. +* $atan2 math builtin, TIC54X: TIC54X-Builtins. +* $ceil math builtin, TIC54X: TIC54X-Builtins. +* $cos math builtin, TIC54X: TIC54X-Builtins. +* $cosh math builtin, TIC54X: TIC54X-Builtins. +* $cvf math builtin, TIC54X: TIC54X-Builtins. +* $cvi math builtin, TIC54X: TIC54X-Builtins. +* $d: ARM Mapping Symbols. +* $exp math builtin, TIC54X: TIC54X-Builtins. +* $fabs math builtin, TIC54X: TIC54X-Builtins. +* $firstch subsym builtin, TIC54X: TIC54X-Macros. +* $floor math builtin, TIC54X: TIC54X-Builtins. +* $fmod math builtin, TIC54X: TIC54X-Builtins. +* $int math builtin, TIC54X: TIC54X-Builtins. +* $iscons subsym builtin, TIC54X: TIC54X-Macros. +* $isdefed subsym builtin, TIC54X: TIC54X-Macros. +* $ismember subsym builtin, TIC54X: TIC54X-Macros. +* $isname subsym builtin, TIC54X: TIC54X-Macros. +* $isreg subsym builtin, TIC54X: TIC54X-Macros. +* $lastch subsym builtin, TIC54X: TIC54X-Macros. +* $ldexp math builtin, TIC54X: TIC54X-Builtins. +* $log math builtin, TIC54X: TIC54X-Builtins. +* $log10 math builtin, TIC54X: TIC54X-Builtins. +* $max math builtin, TIC54X: TIC54X-Builtins. +* $min math builtin, TIC54X: TIC54X-Builtins. +* $pow math builtin, TIC54X: TIC54X-Builtins. +* $round math builtin, TIC54X: TIC54X-Builtins. +* $sgn math builtin, TIC54X: TIC54X-Builtins. +* $sin math builtin, TIC54X: TIC54X-Builtins. +* $sinh math builtin, TIC54X: TIC54X-Builtins. +* $sqrt math builtin, TIC54X: TIC54X-Builtins. +* $structacc subsym builtin, TIC54X: TIC54X-Macros. +* $structsz subsym builtin, TIC54X: TIC54X-Macros. +* $symcmp subsym builtin, TIC54X: TIC54X-Macros. +* $symlen subsym builtin, TIC54X: TIC54X-Macros. +* $t: ARM Mapping Symbols. +* $tan math builtin, TIC54X: TIC54X-Builtins. +* $tanh math builtin, TIC54X: TIC54X-Builtins. +* $trunc math builtin, TIC54X: TIC54X-Builtins. +* -+ option, VAX/VMS: VAX-Opts. +* --: Command Line. +* --32 option, i386: i386-Options. +* --32 option, x86-64: i386-Options. +* --64 option, i386: i386-Options. +* --64 option, x86-64: i386-Options. +* --absolute-literals: Xtensa Options. +* --alternate: alternate. +* --base-size-default-16: M68K-Opts. +* --base-size-default-32: M68K-Opts. +* --bitwise-or option, M680x0: M68K-Opts. +* --disp-size-default-16: M68K-Opts. +* --disp-size-default-32: M68K-Opts. +* --emulation=crisaout command line option, CRIS: CRIS-Opts. +* --emulation=criself command line option, CRIS: CRIS-Opts. +* --enforce-aligned-data: Sparc-Aligned-Data. +* --fatal-warnings: W. +* --fixed-special-register-names command line option, MMIX: MMIX-Opts. +* --force-long-branchs: M68HC11-Opts. +* --generate-example: M68HC11-Opts. +* --globalize-symbols command line option, MMIX: MMIX-Opts. +* --gnu-syntax command line option, MMIX: MMIX-Opts. +* --linker-allocated-gregs command line option, MMIX: MMIX-Opts. +* --listing-cont-lines: listing. +* --listing-lhs-width: listing. +* --listing-lhs-width2: listing. +* --listing-rhs-width: listing. +* --longcalls: Xtensa Options. +* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. +* --MD: MD. +* --mul-bug-abort command line option, CRIS: CRIS-Opts. +* --no-absolute-literals: Xtensa Options. +* --no-expand command line option, MMIX: MMIX-Opts. +* --no-longcalls: Xtensa Options. +* --no-merge-gregs command line option, MMIX: MMIX-Opts. +* --no-mul-bug-abort command line option, CRIS: CRIS-Opts. +* --no-predefined-syms command line option, MMIX: MMIX-Opts. +* --no-pushj-stubs command line option, MMIX: MMIX-Opts. +* --no-stubs command line option, MMIX: MMIX-Opts. +* --no-target-align: Xtensa Options. +* --no-text-section-literals: Xtensa Options. +* --no-transform: Xtensa Options. +* --no-underscore command line option, CRIS: CRIS-Opts. +* --no-warn: W. +* --pcrel: M68K-Opts. +* --pic command line option, CRIS: CRIS-Opts. +* --print-insn-syntax: M68HC11-Opts. +* --print-opcodes: M68HC11-Opts. +* --register-prefix-optional option, M680x0: M68K-Opts. +* --relax command line option, MMIX: MMIX-Opts. +* --rename-section: Xtensa Options. +* --short-branchs: M68HC11-Opts. +* --statistics: statistics. +* --strict-direct-mode: M68HC11-Opts. +* --target-align: Xtensa Options. +* --text-section-literals: Xtensa Options. +* --traditional-format: traditional-format. +* --transform: Xtensa Options. +* --underscore command line option, CRIS: CRIS-Opts. +* --warn: W. +* -1 option, VAX/VMS: VAX-Opts. +* -32addr command line option, Alpha: Alpha Options. +* -a: a. +* -A options, i960: Options-i960. +* -ac: a. +* -ad: a. +* -ah: a. +* -al: a. +* -an: a. +* -as: a. +* -Asparclet: Sparc-Opts. +* -Asparclite: Sparc-Opts. +* -Av6: Sparc-Opts. +* -Av8: Sparc-Opts. +* -Av9: Sparc-Opts. +* -Av9a: Sparc-Opts. +* -b option, i960: Options-i960. +* -big: SH Options. +* -big option, M32R: M32R-Opts. +* -construct-floats: MIPS Opts. +* -D: D. +* -D, ignored on VAX: VAX-Opts. +* -d, VAX option: VAX-Opts. +* -dsp: SH Options. +* -eabi= command line option, ARM: ARM Options. +* -EB command line option, ARC: ARC Options. +* -EB command line option, ARM: ARM Options. +* -EB option (MIPS): MIPS Opts. +* -EB option, M32R: M32R-Opts. +* -EL command line option, ARC: ARC Options. +* -EL command line option, ARM: ARM Options. +* -EL option (MIPS): MIPS Opts. +* -EL option, M32R: M32R-Opts. +* -f: f. +* -F command line option, Alpha: Alpha Options. +* -G command line option, Alpha: Alpha Options. +* -g command line option, Alpha: Alpha Options. +* -G option (MIPS): MIPS Opts. +* -H option, VAX/VMS: VAX-Opts. +* -h option, VAX/VMS: VAX-Opts. +* -I PATH: I. +* -ignore-parallel-conflicts option, M32RX: M32R-Opts. +* -Ip option, M32RX: M32R-Opts. +* -J, ignored on VAX: VAX-Opts. +* -K: K. +* -k command line option, ARM: ARM Options. +* -KPIC option, M32R: M32R-Opts. +* -L: L. +* -l option, M680x0: M68K-Opts. +* -little: SH Options. +* -little option, M32R: M32R-Opts. +* -M: M. +* -m11/03: PDP-11-Options. +* -m11/04: PDP-11-Options. +* -m11/05: PDP-11-Options. +* -m11/10: PDP-11-Options. +* -m11/15: PDP-11-Options. +* -m11/20: PDP-11-Options. +* -m11/21: PDP-11-Options. +* -m11/23: PDP-11-Options. +* -m11/24: PDP-11-Options. +* -m11/34: PDP-11-Options. +* -m11/34a: PDP-11-Options. +* -m11/35: PDP-11-Options. +* -m11/40: PDP-11-Options. +* -m11/44: PDP-11-Options. +* -m11/45: PDP-11-Options. +* -m11/50: PDP-11-Options. +* -m11/53: PDP-11-Options. +* -m11/55: PDP-11-Options. +* -m11/60: PDP-11-Options. +* -m11/70: PDP-11-Options. +* -m11/73: PDP-11-Options. +* -m11/83: PDP-11-Options. +* -m11/84: PDP-11-Options. +* -m11/93: PDP-11-Options. +* -m11/94: PDP-11-Options. +* -m32r option, M32R: M32R-Opts. +* -m32rx option, M32R2: M32R-Opts. +* -m32rx option, M32RX: M32R-Opts. +* -m68000 and related options: M68K-Opts. +* -m68hc11: M68HC11-Opts. +* -m68hc12: M68HC11-Opts. +* -m68hcs12: M68HC11-Opts. +* -mall: PDP-11-Options. +* -mall-extensions: PDP-11-Options. +* -mapcs command line option, ARM: ARM Options. +* -mapcs-float command line option, ARM: ARM Options. +* -mapcs-reentrant command line option, ARM: ARM Options. +* -marc[5|6|7|8] command line option, ARC: ARC Options. +* -march= command line option, ARM: ARM Options. +* -matpcs command line option, ARM: ARM Options. +* -mcis: PDP-11-Options. +* -mconstant-gp command line option, IA-64: IA-64 Options. +* -mCPU command line option, Alpha: Alpha Options. +* -mcpu option, cpu: TIC54X-Opts. +* -mcpu= command line option, ARM: ARM Options. +* -mcsm: PDP-11-Options. +* -mdebug command line option, Alpha: Alpha Options. +* -me option, stderr redirect: TIC54X-Opts. +* -meis: PDP-11-Options. +* -merrors-to-file option, stderr redirect: TIC54X-Opts. +* -mf option, far-mode: TIC54X-Opts. +* -mf11: PDP-11-Options. +* -mfar-mode option, far-mode: TIC54X-Opts. +* -mfis: PDP-11-Options. +* -mfloat-abi= command line option, ARM: ARM Options. +* -mfp-11: PDP-11-Options. +* -mfpp: PDP-11-Options. +* -mfpu: PDP-11-Options. +* -mfpu= command line option, ARM: ARM Options. +* -mip2022 option, IP2K: IP2K-Opts. +* -mip2022ext option, IP2022: IP2K-Opts. +* -mj11: PDP-11-Options. +* -mka11: PDP-11-Options. +* -mkb11: PDP-11-Options. +* -mkd11a: PDP-11-Options. +* -mkd11b: PDP-11-Options. +* -mkd11d: PDP-11-Options. +* -mkd11e: PDP-11-Options. +* -mkd11f: PDP-11-Options. +* -mkd11h: PDP-11-Options. +* -mkd11k: PDP-11-Options. +* -mkd11q: PDP-11-Options. +* -mkd11z: PDP-11-Options. +* -mkev11: PDP-11-Options. +* -mlimited-eis: PDP-11-Options. +* -mlong: M68HC11-Opts. +* -mlong-double: M68HC11-Opts. +* -mmfpt: PDP-11-Options. +* -mmicrocode: PDP-11-Options. +* -mmutiproc: PDP-11-Options. +* -mmxps: PDP-11-Options. +* -mno-cis: PDP-11-Options. +* -mno-csm: PDP-11-Options. +* -mno-eis: PDP-11-Options. +* -mno-extensions: PDP-11-Options. +* -mno-fis: PDP-11-Options. +* -mno-fp-11: PDP-11-Options. +* -mno-fpp: PDP-11-Options. +* -mno-fpu: PDP-11-Options. +* -mno-kev11: PDP-11-Options. +* -mno-limited-eis: PDP-11-Options. +* -mno-mfpt: PDP-11-Options. +* -mno-microcode: PDP-11-Options. +* -mno-mutiproc: PDP-11-Options. +* -mno-mxps: PDP-11-Options. +* -mno-pic: PDP-11-Options. +* -mno-spl: PDP-11-Options. +* -mno-sym32: MIPS Opts. +* -mpic: PDP-11-Options. +* -mrelax command line option, V850: V850 Options. +* -mshort: M68HC11-Opts. +* -mshort-double: M68HC11-Opts. +* -mspl: PDP-11-Options. +* -msym32: MIPS Opts. +* -mt11: PDP-11-Options. +* -mthumb command line option, ARM: ARM Options. +* -mthumb-interwork command line option, ARM: ARM Options. +* -mv850 command line option, V850: V850 Options. +* -mv850any command line option, V850: V850 Options. +* -mv850e command line option, V850: V850 Options. +* -mv850e1 command line option, V850: V850 Options. +* -N command line option, CRIS: CRIS-Opts. +* -nIp option, M32RX: M32R-Opts. +* -no-bitinst, M32R2: M32R-Opts. +* -no-construct-floats: MIPS Opts. +* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. +* -no-mdebug command line option, Alpha: Alpha Options. +* -no-parallel option, M32RX: M32R-Opts. +* -no-relax option, i960: Options-i960. +* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. +* -no-warn-unmatched-high option, M32R: M32R-Opts. +* -nocpp ignored (MIPS): MIPS Opts. +* -o: o. +* -O option, M32RX: M32R-Opts. +* -parallel option, M32RX: M32R-Opts. +* -R: R. +* -relax: SH Options. +* -relax command line option, Alpha: Alpha Options. +* -renesas: SH Options. +* -S, ignored on VAX: VAX-Opts. +* -small: SH Options. +* -t, ignored on VAX: VAX-Opts. +* -T, ignored on VAX: VAX-Opts. +* -v: v. +* -V, redundant on VAX: VAX-Opts. +* -version: v. +* -W: W. +* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. +* -warn-unmatched-high option, M32R: M32R-Opts. +* -Wnp option, M32RX: M32R-Opts. +* -Wnuh option, M32RX: M32R-Opts. +* -Wp option, M32RX: M32R-Opts. +* -wsigned_overflow command line option, V850: V850 Options. +* -Wuh option, M32RX: M32R-Opts. +* -wunsigned_overflow command line option, V850: V850 Options. +* -x command line option, MMIX: MMIX-Opts. +* -z8001 command line option, Z8000: Z8000 Options. +* -z8002 command line option, Z8000: Z8000 Options. +* . (symbol): Dot. +* .big directive, M32RX: M32R-Directives. +* .cantunwind directive, ARM: ARM Directives. +* .fnend directive, ARM: ARM Directives. +* .fnstart directive, ARM: ARM Directives. +* .handlerdata directive, ARM: ARM Directives. +* .insn: MIPS insn. +* .little directive, M32RX: M32R-Directives. +* .ltorg directive, ARM: ARM Directives. +* .m32r directive, M32R: M32R-Directives. +* .m32r2 directive, M32R2: M32R-Directives. +* .m32rx directive, M32RX: M32R-Directives. +* .movsp directive, ARM: ARM Directives. +* .o: Object. +* .pad directive, ARM: ARM Directives. +* .param on HPPA: HPPA Directives. +* .personality directive, ARM: ARM Directives. +* .personalityindex directive, ARM: ARM Directives. +* .pool directive, ARM: ARM Directives. +* .save directive, ARM: ARM Directives. +* .set autoextend: MIPS autoextend. +* .set mdmx: MIPS ASE instruction generation overrides. +* .set mips3d: MIPS ASE instruction generation overrides. +* .set mipsN: MIPS ISA. +* .set noautoextend: MIPS autoextend. +* .set nomdmx: MIPS ASE instruction generation overrides. +* .set nomips3d: MIPS ASE instruction generation overrides. +* .set nosym32: MIPS symbol sizes. +* .set pop: MIPS option stack. +* .set push: MIPS option stack. +* .set sym32: MIPS symbol sizes. +* .setfp directive, ARM: ARM Directives. +* .unwind_raw directive, ARM: ARM Directives. +* .v850 directive, V850: V850 Directives. +* .v850e directive, V850: V850 Directives. +* .v850e1 directive, V850: V850 Directives. +* .z8001: Z8000 Directives. +* .z8002: Z8000 Directives. +* 16-bit code, i386: i386-16bit. +* 29K support: AMD29K-Dependent. +* 2byte directive, ARC: ARC Directives. +* 3byte directive, ARC: ARC Directives. +* 3DNow!, i386: i386-SIMD. +* 3DNow!, x86-64: i386-SIMD. +* 430 support: MSP430-Dependent. +* 4byte directive, ARC: ARC Directives. +* : (label): Statements. +* @word modifier, D10V: D10V-Word. +* \" (doublequote character): Strings. +* \\ (\ character): Strings. +* \b (backspace character): Strings. +* \DDD (octal character code): Strings. +* \f (formfeed character): Strings. +* \n (newline character): Strings. +* \r (carriage return character): Strings. +* \t (tab): Strings. +* \XD... (hex character code): Strings. +* _ opcode prefix: Xtensa Opcodes. +* a.out: Object. +* a.out symbol attributes: a.out Symbols. +* A_DIR environment variable, TIC54X: TIC54X-Env. +* ABI options, SH64: SH64 Options. +* ABORT directive: ABORT. +* abort directive: Abort. +* absolute section: Ld Sections. +* absolute-literals directive: Absolute Literals Directive. +* ADDI instructions, relaxation: Xtensa Immediate Relaxation. +* addition, permitted arguments: Infix Ops. +* addresses: Expressions. +* addresses, format of: Secs Background. +* addressing modes, D10V: D10V-Addressing. +* addressing modes, D30V: D30V-Addressing. +* addressing modes, H8/300: H8/300-Addressing. +* addressing modes, H8/500: H8/500-Addressing. +* addressing modes, M680x0: M68K-Syntax. +* addressing modes, M68HC11: M68HC11-Syntax. +* addressing modes, SH: SH-Addressing. +* addressing modes, SH64: SH64-Addressing. +* addressing modes, Z8000: Z8000-Addressing. +* ADR reg,