diff -ur audacious-plugins-2.3-beta1-orig//src/adplug/core/cmf.cxx audacious-plugins-2.3-beta1/src/adplug/core/cmf.cxx
--- audacious-plugins-2.3-beta1-orig//src/adplug/core/cmf.cxx	2010-03-03 18:10:38.000000000 -0500
+++ audacious-plugins-2.3-beta1/src/adplug/core/cmf.cxx	2010-03-03 18:38:13.000000000 -0500
@@ -290,14 +290,14 @@
 						break;
 					}
 					case 0xF1: // MIDI Time Code Quarter Frame
-						this->data[this->iPlayPointer++]; // message data (ignored)
+						this->iPlayPointer++; // message data (ignored)
 						break;
 					case 0xF2: // Song position pointer
-						this->data[this->iPlayPointer++]; // message data (ignored)
-						this->data[this->iPlayPointer++];
+						this->iPlayPointer++; // message data (ignored)
+						this->iPlayPointer++;
 						break;
 					case 0xF3: // Song select
-						this->data[this->iPlayPointer++]; // message data (ignored)
+						this->iPlayPointer++; // message data (ignored)
 						AdPlug_LogWrite("CMF: MIDI Song Select is not implemented.\n");
 						break;
 					case 0xF6: // Tune request
diff -ur audacious-plugins-2.3-beta1-orig//src/psf/peops/registers.c audacious-plugins-2.3-beta1/src/psf/peops/registers.c
--- audacious-plugins-2.3-beta1-orig//src/psf/peops/registers.c	2010-03-03 18:10:38.000000000 -0500
+++ audacious-plugins-2.3-beta1/src/psf/peops/registers.c	2010-03-03 18:22:57.000000000 -0500
@@ -46,6 +46,13 @@
 #include "../peops/registers.h"
 #include "../peops/regs.h"
 
+static void SoundOn(int start,int end,u16 val);
+static void SoundOff(int start,int end,u16 val);
+static void FModOn(int start,int end,u16 val);
+static void NoiseOn(int start,int end,u16 val);
+static void SetVolumeLR(int right, u8 ch,s16 vol);
+static void SetPitch(int ch,u16 val);
+
 ////////////////////////////////////////////////////////////////////////
 // WRITE REGISTERS: called by main emu
 ////////////////////////////////////////////////////////////////////////
diff -ur audacious-plugins-2.3-beta1-orig//src/psf/peops/regs.h audacious-plugins-2.3-beta1/src/psf/peops/regs.h
--- audacious-plugins-2.3-beta1-orig//src/psf/peops/regs.h	2010-03-03 18:10:38.000000000 -0500
+++ audacious-plugins-2.3-beta1/src/psf/peops/regs.h	2010-03-03 18:22:46.000000000 -0500
@@ -25,10 +25,4 @@
 //*************************************************************************//
 
 
-static void SoundOn(int start,int end,u16 val);
-static void SoundOff(int start,int end,u16 val);
-static void FModOn(int start,int end,u16 val);
-static void NoiseOn(int start,int end,u16 val);
-static void SetVolumeLR(int right, u8 ch,s16 vol);
-static void SetPitch(int ch,u16 val);
 void SPUwriteRegister(u32 reg, u16 val);
diff -ur audacious-plugins-2.3-beta1-orig//src/xsf/desmume/armcpu.c audacious-plugins-2.3-beta1/src/xsf/desmume/armcpu.c
--- audacious-plugins-2.3-beta1-orig//src/xsf/desmume/armcpu.c	2010-03-03 18:10:38.000000000 -0500
+++ audacious-plugins-2.3-beta1/src/xsf/desmume/armcpu.c	2010-03-03 18:33:57.000000000 -0500
@@ -125,6 +125,10 @@
 #endif
 
 static u32
+read_cpu_reg( void *instance, u32 reg_num)
+__attribute__ ((unused));
+
+static u32
 read_cpu_reg( void *instance, u32 reg_num) {
   armcpu_t *armcpu = (armcpu_t *)instance;
   u32 reg_value = 0;
@@ -144,6 +148,10 @@
 }
 
 static void
+set_cpu_reg( void *instance, u32 reg_num, u32 value)
+__attribute__ ((unused));
+
+static void
 set_cpu_reg( void *instance, u32 reg_num, u32 value) {
   armcpu_t *armcpu = (armcpu_t *)instance;
 
@@ -403,37 +411,6 @@
 	return MMU.MMU_WAIT16[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF];
 }
  
-
-static BOOL FASTCALL test_EQ(Status_Reg CPSR) { return ( CPSR.bits.Z); }
-static BOOL FASTCALL test_NE(Status_Reg CPSR) { return (!CPSR.bits.Z); }
-static BOOL FASTCALL test_CS(Status_Reg CPSR) { return ( CPSR.bits.C); }
-static BOOL FASTCALL test_CC(Status_Reg CPSR) { return (!CPSR.bits.C); }
-static BOOL FASTCALL test_MI(Status_Reg CPSR) { return ( CPSR.bits.N); }
-static BOOL FASTCALL test_PL(Status_Reg CPSR) { return (!CPSR.bits.N); }
-static BOOL FASTCALL test_VS(Status_Reg CPSR) { return ( CPSR.bits.V); }
-static BOOL FASTCALL test_VC(Status_Reg CPSR) { return (!CPSR.bits.V); }
-static BOOL FASTCALL test_HI(Status_Reg CPSR) { return (CPSR.bits.C) && (!CPSR.bits.Z); }
-static BOOL FASTCALL test_LS(Status_Reg CPSR) { return (CPSR.bits.Z) || (!CPSR.bits.C); }
-static BOOL FASTCALL test_GE(Status_Reg CPSR) { return (CPSR.bits.N==CPSR.bits.V); }
-static BOOL FASTCALL test_LT(Status_Reg CPSR) { return (CPSR.bits.N!=CPSR.bits.V); }
-static BOOL FASTCALL test_GT(Status_Reg CPSR) { return (!CPSR.bits.Z) && (CPSR.bits.N==CPSR.bits.V); }
-static BOOL FASTCALL test_LE(Status_Reg CPSR) { return ( CPSR.bits.Z) || (CPSR.bits.N!=CPSR.bits.V); }
-static BOOL FASTCALL test_AL(Status_Reg CPSR) { return 1; }
-
-static BOOL (FASTCALL* test_conditions[])(Status_Reg CPSR)= {
-	test_EQ , test_NE ,
-	test_CS , test_CC ,
-	test_MI , test_PL ,
-	test_VS , test_VC ,
-	test_HI , test_LS ,
-	test_GE , test_LT ,
-	test_GT , test_LE ,
-	test_AL
-};
-#define TEST_COND2(cond, CPSR) \
-	(cond<15&&test_conditions[cond](CPSR))
-
-
 BOOL armcpu_irqExeption(armcpu_t *armcpu)
 {
     Status_Reg tmp;
@@ -465,52 +442,6 @@
 
 	return TRUE;
 }
-/*
-static BOOL armcpu_prefetchExeption(armcpu_t *armcpu)
-{
-        Status_Reg tmp;
-	if(armcpu->CPSR.bits.I) return FALSE;
-        tmp = armcpu->CPSR;
-	armcpu_switchMode(armcpu, ABT);
-	armcpu->R[14] = armcpu->next_instruction + 4;
-	armcpu->SPSR = tmp;
-	armcpu->CPSR.bits.T = 0;
-	armcpu->CPSR.bits.I = 1;
-	armcpu->next_instruction = armcpu->intVector + 0xC;
-	armcpu->R[15] = armcpu->next_instruction + 8;
-	armcpu->waitIRQ = 0;
-	return TRUE;
-}
-*/
-
-static BOOL armcpu_prefetchExeption(armcpu_t *armcpu)
-{
-    Status_Reg tmp;
-    if(armcpu->CPSR.bits.I) return FALSE;
-    tmp = armcpu->CPSR;
-    armcpu_switchMode(armcpu, ABT);
-
-#ifdef GDB_STUB
-	 armcpu->R[14] = armcpu->next_instruction + 4;
-#else
-    armcpu->R[14] = armcpu->instruct_adr + 4;
-#endif
-
-    armcpu->SPSR = tmp;
-    armcpu->CPSR.bits.T = 0;
-    armcpu->CPSR.bits.I = 1;
-    armcpu->next_instruction = armcpu->intVector + 0xC;
-	armcpu->waitIRQ = 0;
-
-#ifdef GDB_STUB
-	armcpu->R[15] = armcpu->next_instruction + 8;
-#else
-    armcpu->R[15] = armcpu->next_instruction;
-	armcpu_prefetch(armcpu);
-#endif   
-	
-    return TRUE;
-}
 
 BOOL
 armcpu_flagIrq( armcpu_t *armcpu) {
diff -ur audacious-plugins-2.3-beta1-orig//src/xsf/desmume/arm_instructions.c audacious-plugins-2.3-beta1/src/xsf/desmume/arm_instructions.c
--- audacious-plugins-2.3-beta1-orig//src/xsf/desmume/arm_instructions.c	2010-03-03 18:10:38.000000000 -0500
+++ audacious-plugins-2.3-beta1/src/xsf/desmume/arm_instructions.c	2010-03-03 18:35:21.000000000 -0500
@@ -5876,32 +5876,6 @@
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
-{
-     u32 oldmode;
-     u32 i;
-     u32 adr;
-     u32 val;
-
-     if(cpu->CPSR.bits.mode==USR)
-          return 2;
-          
-     oldmode = armcpu_switchMode(cpu, SYS);
-     //execute = FALSE;
-	 LOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND");
-          
-
-     i = cpu->instruction;
-     adr = cpu->R[REG_POS(i,16)];
-     val = READ8(cpu->mem_if->data, adr);
-     cpu->R[REG_POS(i,12)] = val;
-     cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)];
-     
-     armcpu_switchMode(cpu, oldmode);
-     
-     return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
-}
-
 static u32 FASTCALL  OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
 {
      u32 oldmode;
@@ -6168,50 +6142,6 @@
      
      armcpu_switchMode(cpu, oldmode);
 
-     return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
-}
-
-static u32 FASTCALL  OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
-{
-     u32 oldmode;
-     u32 i;
-     u32 adr;
-
-     if(cpu->CPSR.bits.mode==USR)
-          return 2;
-     
-     oldmode = armcpu_switchMode(cpu, SYS);
-          
-
-     i = cpu->instruction;
-     adr = cpu->R[REG_POS(i,16)];
-     WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
-     cpu->R[REG_POS(i,16)] = adr + cpu->R[REG_POS(i,0)];
-     
-     armcpu_switchMode(cpu, oldmode);
-
-     return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
-}
-
-static u32 FASTCALL  OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu)
-{
-     u32 oldmode;
-     u32 i;
-     u32 adr;
-
-     if(cpu->CPSR.bits.mode==USR)
-          return 2;
-     
-     oldmode = armcpu_switchMode(cpu, SYS);
-          
-
-     i = cpu->instruction;
-     adr = cpu->R[REG_POS(i,16)];
-     WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_POS(i,12)]);
-     cpu->R[REG_POS(i,16)] = adr - cpu->R[REG_POS(i,0)];
-     
-     armcpu_switchMode(cpu, oldmode);
-
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }